Kazutoshi Wakabayashi

57 papers A* 4A 7B 1Misc 4Journal 22Unranked 18
YearRankTypeTitle / Venue / Authors
2026 J jnl
Nested-Pipeline Delta-Stepping Scalable FPGA Accelerator for Parallel Single-Source Shortest Path with High-Level Synthesis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Haopeng Meng, Kazutoshi Wakabayashi, Makoto Ikeda
2025 — conf
A High Level Synthesis Tool for Multiple FPGAs.
MCSoC
Kazutoshi Wakabayashi, Wataru Takahashi, Hideharu Amano
2024 — conf
ISP Parameter Optimization and FPGA Implementation for Object Detection in Low-Light Conditions.
COOL CHIPS
Kento Mishima, Naoya Niwa, Kazutoshi Wakabayashi, Hiroe Iwasaki
2021 — conf
A programming environment for multi-FPGA systems based on CyberWorkBench: an integrated design tool.
HEART
Hiroaki Suzuki, Wataru Takahashi, Kazutoshi Wakabayashi, Hideharu Amano
2020 — conf
33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications.
ISSCC
Masanori Hashimoto, Xu Bai, Naoki Banno, Munehiro Tada, Toshitsugu Sakamoto, Jaehoon Yu, Ryutaro Doi, Yusuke Araki, Hidetoshi Onodera, Takashi Imagawa, Hiroyuki Ochi, Kazutoshi Wakabayashi, Yukio Mitsuyama, Tadahiko Sugibayashi
2019 — conf
Convolution Neural Network Development Support System using Approximation Methods to Evaluate Inference Accuracy and Memory Usage in an Embedded System.
SmartWorld/SCALCOM/UIC/ATC/CBDCom/IOP/SCI
Toki Matsumoto, Yukikazu Nakamoto, Ryota Yamamoto, Shinya Honda, Kazutoshi Wakabayashi
2018 J jnl
Sensor Signal Processing Using High-Level Synthesis With a Layered Architecture.
IEEE Embed. Syst. Lett.
Hiroki Hihara, Akira Iwasaki, Masanori Hashimoto, Hiroyuki Ochi, Yukio Mitsuyama, Hidetoshi Onodera, Hiroyuki Kanbara, Kazutoshi Wakabayashi, Tadahiko Sugibayashi, Takashi Takenaka, Hiromitsu Hada, Munehiro Tada, Makoto Miyamura, Toshitsugu Sakamoto
2018 J jnl
Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture With Overlay Via-Switch Crossbars.
IEEE Trans. Very Large Scale Integr. Syst.
Hiroyuki Ochi, Kosei Yamaguchi, Tetsuaki Fujimoto, Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Takashi Imagawa, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Wataru Takahashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Jaehoon Yu, Masanori Hashimoto
2016 B conf
A highly-dense mixed grained reconfigurable architecture with overlay crossbar interconnect using via-switch.
FPL
Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Hiroyuki Ochi, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Masanori Hashimoto
2016 J jnl
Range Limiter Using Connection Bounding Box for SA-Based Placement of Mixed-Grained Reconfigurable Architecture.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Takashi Kishimoto, Wataru Takahashi, Kazutoshi Wakabayashi, Hiroyuki Ochi
2015 — conf
Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis.
ASP-DAC
Masanori Hashimoto, Dawood Alnajiar, Hiroaki Konoura, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Takao Onoye, Hidetoshi Onodera
2014 — conf
Mapping complex algorithm into FPGA with High Level Synthesis reconfigurable chips with High Level Synthesis compared with CPU, GPGPU.
ASP-DAC
Kazutoshi Wakabayashi, Takashi Takenaka, Hiroaki Inoue
2014 J jnl
Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Hiroaki Konoura, Dawood Alnajiar, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Masanori Hashimoto, Takao Onoye, Hidetoshi Onodera
2013 — conf
Mixed-grained reconfigurable architecture supporting flexible reliability and C-based design.
ReConFig
Hiroaki Konoura, Dawood Alnajiar, Yukio Mitsuyama, Hiroyuki Ochi, Takashi Imagawa, Shinichi Noda, Kazutoshi Wakabayashi, Masanori Hashimoto, Takao Onoye
2013 — conf
Reconfigurable chip advantage compared with GPGPU from the compiler perspective.
FPT
Kazutoshi Wakabayashi
2012 J jnl
Divide and conquer high-level synthesis design space exploration.
ACM Trans. Design Autom. Electr. Syst.
Benjamin Carrión Schäfer, Kazutoshi Wakabayashi
2012 J jnl
Machine learning predictive modelling high-level synthesis design space exploration.
IET Comput. Digit. Tech.
Benjamin Carrión Schäfer, Kazutoshi Wakabayashi
2011 J jnl
Iterative Synthesis Methods Estimating Programmable-Wire Congestion in a Dynamically Reconfigurable Processor.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Takao Toi, Takumi Okamoto, Toru Awashima, Kazutoshi Wakabayashi, Hideharu Amano
2011 J jnl
Precision tunable RTL macro-modelling cycle-accurate power estimation.
IET Comput. Digit. Tech.
Benjamin Carrión Schäfer, Kazutoshi Wakabayashi
2010 J jnl
CODES+ISSS 2009 guest editors' introduction.
Des. Autom. Embed. Syst.
Wolfgang Rosenstiel, Kazutoshi Wakabayashi
2010 J jnl
Design Space Exploration Acceleration Through Operation Clustering.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Benjamin Carrión Schäfer, Kazutoshi Wakabayashi
2010 — conf
Design of complex image processing systems in ESL.
ASP-DAC
Benjamin Carrión Schäfer, Ashish Trambadia, Kazutoshi Wakabayashi
2010 A conf
Exploiting power budgeting in thermal-aware dynamic placement for reconfigurable systems.
ISLPED
Shahin Golshan, Eli Bozorgzadeh, Benjamin Carrión Schäfer, Kazutoshi Wakabayashi, Houman Homayoun, Alexander V. Veidenbaum
2010 J jnl
Fixed Point Data Type Modeling for High Level Synthesis.
IEICE Trans. Electron.
Benjamin Carrión Schäfer, Yusuke Iguchi, Wataru Takahashi, Shingo Nagatani, Kazutoshi Wakabayashi
2010 J jnl
Foreword.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Kazutoshi Wakabayashi
2010 J jnl
High-level Synthesis Challenges for Mapping a Complete Program on a Dynamically Reconfigurable Processor.
Inf. Media Technol.
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, Toru Awashima, Kazutoshi Wakabayashi
2010 J jnl
High-level Synthesis Challenges for Mapping a Complete Program on a Dynamically Reconfigurable Processor.
IPSJ Trans. Syst. LSI Des. Methodol.
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, Toru Awashima, Kazutoshi Wakabayashi
2010 — conf
Real-time multimedia with C compiler for Hardware.
ESTIMedia
Kazutoshi Wakabayashi
2010 — conf
Wire congestion aware synthesis for a dynamically reconfigurable processor.
FPT
Takao Toi, Takumi Okamoto, Toru Awashima, Kazutoshi Wakabayashi, Hideharu Amano
2009 — ed.
Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009
ASP-DAC
Kazutoshi Wakabayashi
2009 Misc ed.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2009, Grenoble, France, October 11-16, 2009
CODES+ISSS
Wolfgang Rosenstiel, Kazutoshi Wakabayashi
2008 J jnl
The State of ESL Design [Roundtable].
IEEE Des. Test Comput.
Reinaldo A. Bergamaschi, Luca Benini, Krisztián Flautner, Wido Kruijtzer, Alberto L. Sangiovanni-Vincentelli, Kazutoshi Wakabayashi
2007 J jnl
Max-Flow Scheduling in High-Level Synthesis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Liangwei Ge, Song Chen, Kazutoshi Wakabayashi, Takashi Takenaka, Takeshi Yoshimura
2007 Misc conf
Synthesizing "Verification Aware" Models: Why and How?
VLSI Design
Malay K. Ganai, Akira Mukaiyama, Aarti Gupta, Kazutoshi Wakabayashi
2006 A conf
High-level synthesis challenges and solutions for a dynamically reconfigurable processor.
ICCAD
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, Toru Awashima, Kazutoshi Wakabayashi, Li Jing
2006 J jnl
Unified Representation for Speculative Scheduling: Generalized Condition Vector.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Kazutoshi Wakabayashi
2005 — conf
Are we ready for system-level synthesis?
ASP-DAC
Jason Cong, Tony Ma, Ivo Bolsens, Phil Moorby, Jan M. Rabaey, John Sanguinetti, Kazutoshi Wakabayashi, Yoshi Watanabe
2005 — conf
System LSI design with C-based behavioral synthesis and verification.
ISCAS (6)
Kazutoshi Wakabayashi
2004 — conf
C-based behavioral synthesis and verification analysis on industrial design examples.
ASP-DAC
Kazutoshi Wakabayashi
2004 Misc conf
Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor.
FCCM
Noriaki Suzuki, Shunsuke Kurotaki, Masayasu Suzuki, Naoto Kaneko, Yutaka Yamada, Katsuaki Deguchi, Yohei Hasegawa, Hideharu Amano, Kenichiro Anjo, Masato Motomura, Kazutoshi Wakabayashi, Takeo Toi, Toru Awashima
2004 — conf
Stream applications on the dynamically reconfigurable processor.
FPT
Masayasu Suzuki, Yohei Hasegawa, Yutaka Yamada, Naoto Kaneko, Katsuaki Deguchi, Hideharu Amano, Kenichiro Anjo, Masato Motomura, Kazutoshi Wakabayashi, Takao Toi, Toru Awashima
2003 J jnl
Study and Analysis of System LSI Design Methodologies Using C-Based Behavioral Synthesis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Hidefumi Kurokawa, Hiroyuki Ikegami, Motohide Otsubo, Kiyoshi Asao, Kazuhisa Kirigaya, Katsuya Misu, Satoshi Takahashi, Tetsuji Kawatsu, Kouji Nitta, Hiroshi Ryu, Kazutoshi Wakabayashi, Minoru Tomobe, Wataru Takahashi, Akira Mukouyama, Takashi Takenaka
2002 J jnl
Foreword.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Kazutoshi Wakabayashi
2002 — conf
Property-Specific Testbench Generation for Guided Simulation.
ASP-DAC/VLSI Design
Aarti Gupta, Albert E. Casavant, Pranav Ashar, Sean Liu, Akira Mukaiyama, Kazutoshi Wakabayashi
2001 A conf
Property-specific witness graph generation for guided simulation.
DATE
Albert E. Casavant, Aarti Gupta, S. Liu, Akira Mukaiyama, Kazutoshi Wakabayashi, Pranav Ashar
2000 J jnl
C-based SoC design flow and EDA tools: an ASIC and system vendorperspective.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kazutoshi Wakabayashi, Takumi Okamoto
2000 — conf
Spatial-temporal mapping of real applications on a Dynamically Reconfigurable Logic Engine (DRLE) LSI.
CICC
Koichiro Furuta, Taro Fujii, Masato Motomura, Kazutoshi Wakabayashi, Masakazu Yamashina
1999 A conf
C-based Synthesis Experiences with a Behavior Synthesizer, "Cyber".
DATE
Kazutoshi Wakabayashi
1999 J jnl
Controller-based power management for control-flow intensive designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sujit Dey, Anand Raghunathan, Niraj K. Jha, Kazutoshi Wakabayashi
1997 A* conf
Power Management Techniques for Control-Flow Intensive Designs.
DAC
Anand Raghunathan, Sujit Dey, Niraj K. Jha, Kazutoshi Wakabayashi
1996 A conf
Controller re-specification to minimize switching activity in controller/data path circuits.
ISLPED
Anand Raghunathan, Sujit Dey, Niraj K. Jha, Kazutoshi Wakabayashi
1995 A conf
Design-for-debugging of application specific designs.
ICCAD
Miodrag Potkonjak, Sujit Dey, Kazutoshi Wakabayashi
1995 Misc conf
Efficient throughput optimization of feedback linear computations using generalized Horner's scheme.
ICASSP
Jan M. Rabaey, Miodrag Potkonjak, Kazutoshi Wakabayashi
1995 A* conf
Multi-Level Logic Minimization Based on Multi-Signal Implications.
DAC
Masayuki Yuguchi, Yuichi Nakamura, Kazutoshi Wakabayashi, Tomoyuki Fujita
1992 A* conf
Global Scheduling Independent of Control Dependencies Based on Condition Vectors.
DAC
Kazutoshi Wakabayashi, Hirohito Tanaka
1989 A conf
A resource sharing and control synthesis method for conditional branches.
ICCAD
Kazutoshi Wakabayashi, Takeshi Yoshimura
1985 A* conf
Knowledge-based placement technique for printed wiring boards.
DAC
Gotaro Odawara, Kazuhiko Iijima, Kazutoshi Wakabayashi