Kazutoshi Kobayashi

99 papers A 1B 3C 8Misc 2Journal 37Unranked 48

Year	Rank	Type	Title / Venue / Authors
2025	C	`conf`	A 22-nm Surface Code Decoder Using Greedy Algorithm. ISCAS Junichiro Kadomoto, Ren Aoyama, Kazutoshi Kobayashi
2025	J	`jnl`	An Energy Efficient 2-Read/Write 8T Dual-Port SRAM with Disturbance Aware Self-Adjustable Replica Tracking Circuit. IEICE Trans. Electron. Koji Nii, Kazutoshi Kobayashi
2025	C	`conf`	Comparative Analysis of TID Effects in a 65 nm FD-SOI Process Under Gamma-Ray and Alpha-Ray Irradiation. IOLTS Hikaru Nakamoto, Taiki Ozawa, Ryuichi Nakajima, Haruto Sugisaki, Keita Yoshida, Jun Furuta, Kazutoshi Kobayashi
2025	—	`conf`	Investigation of the Time-Dependent BTI-induced Degradation Distribution for Ring Oscillators in Ultra-Long-Term Stress Conditions. IRPS Tomoharu Kishita, Ryo Kishida, Kazutoshi Kobayashi
2025	—	`conf`	Panel Discussions: "Sustainable AI: Emerging Architectures, Devices, and Quantum Computing Towards Future Computing". COOL CHIPS Tohru Ishihara, Jangwoo Kim, Kazutoshi Kobayashi, Jose Martinez
2025	—	`conf`	Physics-based Modeling to Extend a MOSFET Compact Model for Cryogenic Operation. ASP-DAC Dondee Navarro, Shin Taniguchi, Chika Tanaka, Kazutoshi Kobayashi, Takashi Sato, Michihiro Shintani
2025	J	`jnl`	Radiation-Hardened Flip-Flops in a 65 nm Bulk Process for Terrestrial Applications Coping with Radiation Hardness and Performance Overheads. IEICE Trans. Electron. Shotaro Sugitani, Ryuichi Nakajima, Keita Yoshida, Jun Furuta, Kazutoshi Kobayashi
2024	—	`conf`	A Partially-redundant Flip-flip Suitable for Mitigating Single Event Upsets in a FD-SOI Process with Low Performance Overhead. IRPS Jun Furuta, Shotaro Sugitani, Ryuichi Nakajima, Kazutoshi Kobayashi
2024	Misc	`conf`	A Power Reduction Scheme by Arithmetic Format Conversion for a DSP to Estimate Qubit States Under 4K Cryogenic Environment. QCE Takashi Imagawa, Ryo Kishida, Yuki Koyama, Kazutoshi Kobayashi, Takefumi Miyoshi
2024	—	`conf`	An Approach to Neutron-Induced SER Evaluation Using a Clinical 290 MeV/ u Carbon Beam and Particle Transport Simulations. IRPS Ryuichi Nakajima, Shotaro Sugitani, Haruto Sugisaki, Takafumi Ito, Jun Furuta, Kazutoshi Kobayashi, Makoto Sakai
2024	J	`jnl`	Frequency dependence of soft error rates induced by alpha-particle and heavy ion. IEICE Electron. Express Haruto Sugisaki, Ryuichi Nakajima, Shotaro Sugitani, Jun Furuta, Kazutoshi Kobayashi
2024	J	`jnl`	Measuring SET Pulse Widths in pMOSFETs and nMOSFETs Separately by Heavy Ion and Neutron Irradiation. IEICE Trans. Electron. Jun Furuta, Shotaro Sugitani, Ryuichi Nakajima, Takafumi Ito, Kazutoshi Kobayashi
2024	J	`jnl`	Soft-Error Tolerance by Guard-Gate Structures on Flip-Flops in 22 and 65 nm FD-SOI Technologies. IEICE Trans. Electron. Ryuichi Nakajima, Takafumi Ito, Shotaro Sugitani, Tomoya Kii, Mitsunori Ebara, Jun Furuta, Kazutoshi Kobayashi, Mathieu Louvat, Francois Jacquet, Jean-Christophe Eloy, Olivier Montfort, Lionel Jure, Vincent Huard
2023	—	`conf`	A 13-bit Radiation-Hardened SAR-ADC with Error Correction by Adaptive Topology Transformation. IRPS Yuya Aoki, Tatsuya Iwata, Takuji Miki, Kazutoshi Kobayashi, Takefumi Yoshikawa
2023	J	`jnl`	Disturbance Aware Dynamic Power Reduction in Synchronous 2RW Dual-Port 8T SRAM by Self-Adjusting Wordline Pulse Timing. IEEE J. Solid State Circuits Yoshisato Yokoyama, Koji Nii, Yuichiro Ishii, Shinji Tanaka, Kazutoshi Kobayashi
2023	—	`conf`	Frequency Dependency of Soft Error Rates Based on Dynamic Soft Error Measurements. ICICDT Haruto Sugisaki, Ryuichi Nakajima, Shotaro Sugitani, Jun Furuta, Kazutoshi Kobayashi
2023	J	`jnl`	Nonvolatile Storage Cells Using FiCC for IoT Processors with Intermittent Operations. IEICE Trans. Electron. Yuki Abe, Kazutoshi Kobayashi, Jun Shiomi, Hiroyuki Ochi
2023	—	`conf`	Radiation Hardened Flip-Flops with low Area, Delay and Power Overheads in a 65 nm bulk process. IRPS Shotaro Sugitani, Ryuichi Nakajima, Keita Yoshida, Jun Furuta, Kazutoshi Kobayashi
2023	C	`conf`	Radiation Hardness Evaluations of a Stacked Flip Flop in a 22 nm FD-SOI Process by Heavy-Ion Irradiation. IOLTS Shotaro Sugitani, Ryuichi Nakajima, Takafumi Ito, Jun Furuta, Kazutoshi Kobayashi, Mathieu Louvat, Francois Jacquet, Jean-Christophe Eloy, Olivier Montfort, Lionel Jure, Vincent Huard
2023	—	`conf`	Ring Oscillators with identical Circuit Structure to Measure Bias Temperature Instability. ASICON Daisuke Kikuta, Ryo Kishida, Kazutoshi Kobayashi
2023	—	`conf`	SEU Sensitivity of PMOS and NMOS Transistors in a 65 nm Bulk Process by α-Particle Irradiation. ICICDT Keita Yoshida, Ryuichi Nakajima, Shotaro Sugitani, Takafumi Ito, Jun Furuta, Kazutoshi Kobayashi
2023	—	`conf`	Scalable Highly Integrated Quantum Bit Error Correction System by Classical Electronics. ASICON Kazutoshi Kobayashi
2023	—	`conf`	Ultra Long-term Measurement Results of BTI-induced Aging Degradation on 7-nm Ring Oscillators. IRPS Kazutoshi Kobayashi, Tomoharu Kishita, Hiroki Nakano, Jun Furuta, Mitsuhiko Igarashi, Shigetaka Kumashiro, Michitarou Yabuuchi, Hironori Sakamoto
2022	—	`conf`	An Aging Degradation Suppression Scheme at Constant Performance by Controlling Supply Voltage and Body Bias in a 65 nm Fully-Depleted Silicon-On-Insulator Process. IRPS Ikuo Suda, Ryo Kishida, Kazutoshi Kobayashi
2022	—	`conf`	Nonvolatile Flip-Flops Using FiCC for IoT Processors with Intermittent Operations. MWSCAS Yuki Abe, Kazutoshi Kobayashi, Hiroyuki Ochi
2022	C	`conf`	Radiation Hardened Flip-Flops Minimizing Area, Power, and Delay Overheads with 1/100 Lower α-SER in a 130 nm Bulk Process. IOLTS Ryuichi Nakajima, Kazuya Ioki, Jun Furuta, Kazutoshi Kobayashi
2022	—	`conf`	Zero-standby-power Nonvolatile Standard Cell Memory Using FiCC for IoT Processors with Intermittent Operations. COOL CHIPS Yuki Abe, Kazutoshi Kobayashi, Jun Shiomi, Hiroyuki Ochi
2021	J	`jnl`	A Bit-Error Rate Measurement and Error Analysis of Wireline Data Transmission using Current Source Model for Single Event Effect under Irradiation Environment. J. Electron. Test. Takefumi Yoshikawa, Masahiro Ishimaru, Tatsuya Iwata, Fuma Mori, Kazutoshi Kobayashi
2021	J	`jnl`	An Analysis of Local BTI Variation with Ring-Oscillator in Advanced Processes and Its Impact on Logic Circuit and SRAM. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Mitsuhiko Igarashi, Yuuki Uchida, Yoshio Takazawa, Makoto Yabuuchi, Yasumasa Tsukamoto, Koji Shibutani, Kazutoshi Kobayashi
2021	J	`jnl`	An E-mode p-GaN HEMT monolithically-integrated three-level gate driver operating with a single voltage supply. IEICE Electron. Express Junichiro Nagao, Urmimala Chatterjee, Xiangdong Li, Jun Furuta, Stefaan Decoutere, Kazutoshi Kobayashi
2021	—	`conf`	Bias Temperature Instability Depending on Body Bias through Buried Oxide (BOX) Layer in a 65 nm Fully-Depleted Silicon-On-Insulator Process. IRPS Ryo Kishida, Ikuo Suda, Kazutoshi Kobayashi
2021	J	`jnl`	Cost-Effective Test Screening Method on 40-nm Embedded SRAMs for Low-Power MCUs. IEEE Trans. Very Large Scale Integr. Syst. Yoshisato Yokoyama, Yuichiro Ishii, Koji Nii, Kazutoshi Kobayashi
2021	—	`conf`	Nonvolatile SRAM Using Fishbone-in-Cage Capacitor in a 180 nm Standard CMOS Process for Zero-Standby and Instant-Powerup Embedded Memory on IoT. COOL CHIPS Takaki Urabe, Hiroyuki Ochi, Kazutoshi Kobayashi
2020	J	`jnl`	An Efficient and Accurate Time Step Control Method for Power Device Transient Simulation Utilizing Dominant Time Constant Approximation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shigetaka Kumashiro, Tatsuya Kamei, Akira Hiroki, Kazutoshi Kobayashi
2020	J	`jnl`	Evaluation of Heavy-Ion-Induced Single Event Upset Cross Sections of a 65-nm Thin BOX FD-SOI Flip-Flops Composed of Stacked Inverters. IEICE Trans. Electron. Kentaro Kojima, Kodai Yamada, Jun Furuta, Kazutoshi Kobayashi
2020	J	`jnl`	Universal NBTI Compact Model Replicating AC Stress/Recovery from a Single-shot Long-term DC Measurement. IPSJ Trans. Syst. LSI Des. Methodol. Takumi Hosaka, Shinichi Nishizawa, Ryo Kishida, Takashi Matsumoto, Kazutoshi Kobayashi
2019	—	`conf`	An Accurate Device-Level Simulation Method to Estimate Cross Sections of Single Event Upsets by Silicon Thickness in Raised Layer. IRPS Kentaro Kojima, Kodai Yamada, Jun Furuta, Kazutoshi Kobayashi
2019	J	`jnl`	Characterizing SRAM and FF soft error rates with measurement and simulation. Integr. Masanori Hashimoto, Kazutoshi Kobayashi, Jun Furuta, Shin-ichiro Abe, Yukinobu Watanabe
2019	C	`conf`	Compact Modeling of NBTI Replicating AC Stress / Recovery from a Single-shot Long-term DC Measurement. IOLTS Takumi Hosaka, Shinichi Nishizawa, Ryo Kishida, Takashi Matsumoto, Kazutoshi Kobayashi
2019	C	`conf`	Comparison of Radiation Hardness of Stacked Transmission-Gate Flip Flop and Stacked Tristate-Inverter Flip Flop in a 65 nm Thin BOX FDSOI Process. IOLTS Mitsunori Ebara, Kodai Yamada, Jun Furuta, Kazutoshi Kobayashi
2019	—	`conf`	Impact of Combinational Logic Delay for Single Event Upset on Flip Flops in a 65 nm FDSOI Process. IRPS Jun Furuta, Yuto Tsukita, Kodai Yamada, Mitsunori Ebara, Kentaro Kojima, Kazutoshi Kobayashi
2019	J	`jnl`	Monolithic integration of gate driver and p-GaN power HEMT for MHz-switching implemented by e-mode GaN-on-SOI process. IEICE Electron. Express Yuki Yamashita, Steve Stoffels, Niels Posthuma, Karen Geens, Xiangdong Li, Jun Furuta, Stefaan Decoutere, Kazutoshi Kobayashi
2019	—	`conf`	Monolithically integrated GaN power ICs designed using the MIT virtual source GaNFET (MVSG) compact model for enhancement-mode p-GaN gate power HEMTs, logic transistors and resistors. ESSDERC Shuzhen You, Xiangdong Li, Stefaan Decoutere, Guido Groeseneken, Zhanfei Chen, Jun Liu, Yuki Yamashita, Kazutoshi Kobayashi
2019	—	`conf`	Soft-Error Tolerance Depending on Supply Voltage by Heavy Ions on Radiation-Hardened Flip Flops in a 65 nm Bulk Process. ASICON Yuto Tsukita, Mitsunori Ebara, Jun Furuta, Kazutoshi Kobayashi
2019	—	`conf`	Temperature Dependence of Bias Temperature Instability (BTI) in Long-term Measurement by BTI-sensitive and -insensitive Ring Oscillators Removing Environmental Fluctuation. ASICON Takuya Asuke, Ryo Kishida, Jun Furuta, Kazutoshi Kobayashi
2019	C	`conf`	Total Ionizing Dose Effects by alpha irradiation on circuit performance and SEU tolerance in thin BOX FDSOI process. IOLTS Takashi Yoshida, Kazutoshi Kobayashi, Jun Furuta
2018	J	`jnl`	A Low-Power Radiation-Hardened Flip-Flop with Stacked Transistors in a 65 nm FDSOI Process. IEICE Trans. Electron. Haruki Maruoka, Masashi Hifumi, Jun Furuta, Kazutoshi Kobayashi
2018	—	`conf`	Sensitivity to soft errors of NMOS and PMOS transistors evaluated by latches with stacking structures in a 65 nm FDSOI process. IRPS Kodai Yamada, Haruki Maruoka, Jun Furuta, Kazutoshi Kobayashi
2017	—	`conf`	Circuit-level simulation methodology for Random Telegraph Noise by using Verilog-AMS. ICICDT Takuya Komawaki, Michitarou Yabuuchi, Ryo Kishida, Jun Furuta, Takashi Matsumoto, Kazutoshi Kobayashi
2017	—	`conf`	Highly-reliable integrated circuits for Gro. ASICON Kazutoshi Kobayashi
2017	J	`jnl`	Replication of Random Telegraph Noise by Using a Physical-Based Verilog-AMS Model. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takuya Komawaki, Michitarou Yabuuchi, Ryo Kishida, Jun Furuta, Takashi Matsumoto, Kazutoshi Kobayashi
2016	J	`jnl`	Size Optimization Technique for Logic Circuits that Considers BTI and Process Variations. IPSJ Trans. Syst. LSI Des. Methodol. Michitarou Yabuuchi, Kazutoshi Kobayashi
2015	J	`jnl`	A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOS Technology with Reverse-Body-Bias Assisted Sleep Mode. IEICE Trans. Electron. Koichiro Ishibashi, Nobuyuki Sugii, Shiro Kamohara, Kimiyoshi Usami, Hideharu Amano, Kazutoshi Kobayashi, Cong-Kha Pham
2015	J	`jnl`	Impact of Cell Distance and Well-contact Density on Neutron-induced Multiple Cell Upsets. IEICE Trans. Electron. Jun Furuta, Kazutoshi Kobayashi, Hidetoshi Onodera
2015	—	`conf`	Impact of random telegraph noise on ring oscillators evaluated by circuit-level simulations. ICICDT Azusa Oshima, Pieter Weckx, Ben Kaczer, Kazutoshi Kobayashi, Takashi Matsumoto
2015	—	`conf`	Negative bias temperature instability caused by plasma induced damage in 65 nm bulk and Silicon on thin BOX (SOTB) processes. IRPS Ryo Kishida, Azusa Oshima, Kazutoshi Kobayashi
2015	—	`conf`	Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis. ASP-DAC Masanori Hashimoto, Dawood Alnajiar, Hiroaki Konoura, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Takao Onoye, Hidetoshi Onodera
2014	—	`conf`	A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology. COOL Chips Koichiro Ishibashi, Nobuyuki Sugii, Kimiyoshi Usami, Hideharu Amano, Kazutoshi Kobayashi, Cong-Kha Pham, Hideki Makiyama, Yoshiki Yamamoto, Hirofumi Shinohara, Toshiaki Iwamatsu, Yasuo Yamaguchi, Hidekazu Oda, Takumi Hasegawa, Shinobu Okanishi, Hiroshi Yanagita, Shiro Kamohara, Masaru Kadoshima, Keiichi Maekawa, Tomohiro Yamashita, Duc-Hung Le, Takumu Yomogita, Masaru Kudo, Kuniaki Kitamori, Shuya Kondo, Yuuki Manzawa
2014	—	`conf`	A perpetuum mobile 32bit CPU on 65nm SOTB CMOS technology with reverse-body-bias assisted sleep mode. Hot Chips Symposium Shiro Kamohara, Nobuyuki Sugii, Koichiro Ishibashi, Kimiyoshi Usami, Hideharu Amano, Kazutoshi Kobayashi, Cong-Kha Pham
2014	J	`jnl`	Correlations between BTI-Induced Degradations and Process Variations on ASICs and FPGAs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Michitarou Yabuuchi, Ryo Kishida, Kazutoshi Kobayashi
2014	J	`jnl`	Foreword. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kazutoshi Kobayashi
2014	—	`conf`	Impact of random telegraph noise on CMOS logic circuit reliability. CICC Takashi Matsumoto, Kazutoshi Kobayashi, Hidetoshi Onodera
2014	J	`jnl`	Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hiroaki Konoura, Dawood Alnajiar, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Masanori Hashimoto, Takao Onoye, Hidetoshi Onodera
2013	J	`jnl`	A Radiation-Hard Redundant Flip-Flop to Suppress Multiple Cell Upset by Utilizing the Parasitic Bipolar Effect. IEICE Trans. Electron. Kuiyuan Zhang, Jun Furuta, Ryosuke Yamamoto, Kazutoshi Kobayashi, Hidetoshi Onodera
2012	J	`jnl`	NBTI-Induced Delay Degradation Analysis of FPGA Routing Structures. Inf. Media Technol. Michitarou Yabuuchi, Kazutoshi Kobayashi
2012	J	`jnl`	NBTI-Induced Delay Degradation Analysis of FPGA Routing Structures. IPSJ Trans. Syst. LSI Des. Methodol. Michitarou Yabuuchi, Kazutoshi Kobayashi
2011	—	`conf`	A 65nm flip-flop array to measure soft error resiliency against high-energy neutron and alpha particles. ASP-DAC Jun Furuta, Chikara Hamanaka, Kazutoshi Kobayashi, Hidetoshi Onodera
2011	—	`conf`	Correlations between well potential and SEUs measured by well-potential perturbation detectors in 65nm. A-SSCC Jun Furuta, Ryosuke Yamamoto, Kazutoshi Kobayashi, Hidetoshi Onodera
2011	—	`conf`	Modeling of Random Telegraph Noise under circuit operation - Simulation and measurement of RTN-induced delay fluctuation. ISQED Kyosuke Ito, Takashi Matsumoto, Shinichi Nishizawa, Hiroki Sunagawa, Kazutoshi Kobayashi, Hidetoshi Onodera
2011	J	`jnl`	Variation-Tolerance of a 65-nm Error-Hardened Dual-Modular-Redundancy Flip-Flop Measured by Shift-Register-Based Monitor Structures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Chikara Hamanaka, Ryosuke Yamamoto, Jun Furuta, Kanto Kubota, Kazutoshi Kobayashi, Hidetoshi Onodera
2010	C	`conf`	A Minimal Roll-Back Based Recovery Scheme for Fault Toleration in Pipeline Processors. PRDC Jun Yao, Ryoji Watanabe, Takashi Nakada, Hajime Shimada, Yasuhiko Nakashima, Kazutoshi Kobayashi
2010	—	`conf`	A Stage-Level Recovery Scheme in Scalable Pipeline Modules for High Dependability. IWIA Jun Yao, Hajime Shimada, Kazutoshi Kobayashi
2010	J	`jnl`	An Area/Delay Efficient Dual-Modular Flip-Flop with Higher SEU/SET Immunity. IEICE Trans. Electron. Jun Furuta, Kazutoshi Kobayashi, Hidetoshi Onodera
2010	J	`jnl`	Effect of Regularity-Enhanced Layout on Variability and Circuit Performance of Standard Cells. Inf. Media Technol. Hiroki Sunagawa, Haruhiko Terada, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera
2010	J	`jnl`	Effect of Regularity-Enhanced Layout on Variability and Circuit Performance of Standard Cells. IPSJ Trans. Syst. LSI Des. Methodol. Hiroki Sunagawa, Haruhiko Terada, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera
2010	—	`conf`	Evaluation of FPGA design guardband caused by inhomogeneous NBTI degradation considering process variations. FPT Michitarou Yabuuchi, Kazutoshi Kobayashi
2009	—	`conf`	Erect of regularity-enhanced layout on printability and circuit performance of standard cells. ISQED Hiroki Sunagawa, Haruhiko Terada, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera
2008	B	`conf`	A variation-aware constant-order optimization scheme utilizing delay detectors to search for fastest paths on FPGAS. FPL Kazutoshi Kobayashi, Yohei Kume, Cam Lai Ngo, Yuuri Sugihara, Hidetoshi Onodera
2008	—	`conf`	Best ways to use billions of devices on a chip - Error predictive, defect tolerant and error recovery designs. ASP-DAC Kazutoshi Kobayashi, Hidetoshi Onodera
2008	B	`conf`	Performance optimization by track swapping on critical paths utilizing random variations for FPGAS. FPL Yuuri Sugihara, Yohei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera
2008	A	`conf`	Speed and yield enhancement by track swapping on critical paths utilizing random variations for FPGAs. FPGA Yuuri Sugihara, Yohei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera
2007	J	`jnl`	A 90 nm 48 x 48 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations. IEICE Trans. Electron. Kazutoshi Kobayashi, Kazuya Katsuki, Manabu Kotani, Yuuri Sugihara, Yohei Kume, Hidetoshi Onodera
2007	J	`jnl`	A 90 nm LUT Array for Speed and Yield Enhancement by Utilizing Within-Die Delay Variations. IEICE Trans. Electron. Kazuya Katsuki, Manabu Kotani, Kazutoshi Kobayashi, Hidetoshi Onodera
2007	—	`conf`	A 90nm 8×16 FPGA Enhancing Speed and Yield Utilizing Within-Die Variations. ASP-DAC Yuuri Sugihara, Manabu Kotani, Kazuya Katsuki, Kazutoshi Kobayashi, Hidetoshi Onodera
2006	J	`jnl`	A Leakage Reduction Scheme for Sleep Transistors with Decoupling Capacitors in the Deep Submicron Era. IEICE Trans. Electron. Kazutoshi Kobayashi, Akihiko Higuchi, Hidetoshi Onodera
2006	B	`conf`	A Yield and Speed Enhancement Technique Using Reconfigurable Devices Against Within-Die Variations on the Nanometer Regime. FPL Kazutoshi Kobayashi, Manabu Kotani, Kazuya Katsuki, Y. Takatsukasa, K. Ogata, Yuuri Sugihara, Hidetoshi Onodera
2006	J	`jnl`	Alternate Self-Shielding for High-Speed and Reliable On-Chip Global Interconnect. IEICE Trans. Electron. Yoichi Yuyama, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera
2006	—	`conf`	Measurement results of within-die variations on a 90nm LUT array for speed and yield enhancement of reconfigurable devices. ASP-DAC Kazuya Katsuki, Manabu Kotani, Kazutoshi Kobayashi, Hidetoshi Onodera
2005	J	`jnl`	A Resource-Shared VLIW Processor for Low-Power On-Chip Multiprocessing in the Nanometer Era. IEICE Trans. Electron. Kazutoshi Kobayashi, Masao Aramoto, Hidetoshi Onodera
2005	—	`conf`	A resource-shared VLIW processor architecture for area-efficient on-chip multiprocessing. ASP-DAC Kazutoshi Kobayashi, Masao Aramoto, Yoichi Yuyama, Akihiko Higuchi, Hidetoshi Onodera
2005	—	`conf`	A yield and speed enhancement scheme under within-die variations on 90nm LUT array. CICC Kazuya Katsuki, Manabu Kotani, Kazutoshi Kobayashi, Hidetoshi Onodera
2004	J	`jnl`	A Comprehensive Simulation and Test Environment for Prototype VLSI Verification. IEICE Trans. Inf. Syst. Kazutoshi Kobayashi, Hidetoshi Onodera
2004	—	`conf`	An SoC architecture and its design methodology using unifunctional heterogeneous processor array. ASP-DAC Yoichi Yuyama, Masao Aramoto, Kazutoshi Kobayashi, Hidetoshi Onodera
2004	—	`conf`	RTL/ISS co-modeling methodology for embedded processor using SystemC. ISCAS (5) Yoichi Yuyama, Masao Aramoto, Kazutoshi Kobayashi, Hidetoshi Onodera
2002	—	`conf`	Measurement results of on-chip IR-drop. CICC Kazutoshi Kobayashi, Junji Yamaguchi, Hidetoshi Onodera
2001	—	`conf`	A vector-pipeline DSP for low-rate videophones. ASP-DAC Kazutoshi Kobayashi, Makoto Eguchi, Takuya Iwahashi, Takehide Shibayama, Xiang Li, Kousuke Takai, Hidetoshi Onodera
2001	—	`conf`	ST: PERL package for simulation and test environment. ISCAS (5) Kazutoshi Kobayashi, Hidetoshi Onodera
1998	Misc	`conf`	Real time low bit-rate video coding algorithm using multi-stage hierarchical vector quantization. ICASSP Kazuhiko Terada, Masahiro Takeuchi, Kazutoshi Kobayashi, Keikichi Tamaru
1997	—	`conf`	A functional memory type parallel processor for vector quantization. ASP-DAC Kazutoshi Kobayashi, Masayoshi Kinoshita, Masahiro Takeuchi, Hidetoshi Onodera, Keikichi Tamaru