Kazuteru Namba

82 papers C 7Journal 44Unranked 31
YearRankTypeTitle / Venue / Authors
2026 J jnl
Analysis of a Delay-Element-Based Technique for Enhancing Soft Error Tolerance at Input Nodes Around Clock Edges.
IEEE Trans. Very Large Scale Integr. Syst.
Song Wang, Kazuteru Namba
2024 J jnl
6T-8T Hybrid SRAM for Lower-Power Neural-Network Processing by Lowering Operating Voltage.
IEICE Trans. Inf. Syst.
Ji Wu, Ruoxi Yu, Kazuteru Namba
2024 — conf
A Master-Slave Flip-Flop with Double-Node-Upset Self-Recovery and Soft Error Tolerance around Clock Edges.
ICCE-Taiwan
Song Wang, Kazuteru Namba
2024 — conf
Board design of digital chirp generator for earth observation.
ICCE-Taiwan
Yoshiaki Saito, Kazuteru Namba, Josaphat Tetuko Sri Sumantyo
2024 — conf
Effect of RESET operation of CiM with PCM on recognition accuracy.
ICCE-Taiwan
Kento Yano, You Yin, Kazuteru Namba
2024 C conf
FPGA Cluster Based System with Adaptive TMR/DMR for Soft Error Mitigation.
PRDC
Homu Omura, Kazuteru Namba
2023 — conf
SRAM-based efficiency memory model for quantized convolutional neural networks.
ICCE-Taiwan
Ji Wu, Kazuteru Namba
2022 — conf
A Double Node Upset tolerant SR latch using C-element.
ICCE-TW
Shogo Takahashi, Kazuteru Namba
2022 J jnl
Low Power Neural Network by Reducing SRAM Operating Voltage.
IEEE Access
Keisuke Kozu, Yuya Tanabe, Masato Kitakami, Kazuteru Namba
2022 C conf
Stuck-at Fault Tolerance in DNN Using Statistical data.
PRDC
Tomohiro Ishii, Kazuteru Namba
2021 — conf
Relaxing device requirements for non-linearity in Deep Neural Networks accelerators with Phase Change Memory.
ICCE-TW
Keisuke Kozu, Kazuteru Namba
2020 J jnl
Complete Double Node Upset Tolerant Latch Using C-Element.
IEICE Trans. Inf. Syst.
Yuta Yamamoto, Kazuteru Namba
2020 — conf
Influence of Recognition Performance on Recurrent Neural Network Using Phase-Change Memory as Synapses.
ICCE-TW
Tomohiro Takahashi, Kazuteru Namba
2020 J jnl
Master-Slave FF Using DICE Capable of Tolerating Soft Errors Occurring Around Clock Edge.
IEICE Trans. Inf. Syst.
Kazuteru Namba
2019 J jnl
Coding for Write Latency Reduction in a Multi-Level Cell (MLC) Phase Change Memory (PCM).
IEEE Trans. Computers
Kazuteru Namba, Fabrizio Lombardi
2019 — conf
Low Redundancy Double Error Correction Spotty Codes Combined with Gray Coding for 64 Data Bits Memories of 4-bit Multilevel Cells.
DFT
Shanshan Liu, Pedro Reviriego, Kazuteru Namba, Salvatore Pontarelli, Liyi Xiao, Fabrizio Lombardi
2018 J jnl
A Single and Adjacent Error Correction Code for Fast Decoding of Critical Bits.
IEEE Trans. Computers
Kazuteru Namba, Fabrizio Lombardi
2018 — conf
Construction of Latch Design with Complete Double Node Upset Tolerant Capability Using C-Element.
DFT
Yuta Yamamoto, Kazuteru Namba
2018 J jnl
On Coding for Endurance Enhancement and Error Control of Phase Change Memories With Write Latency Reduction.
IEEE Trans. Very Large Scale Integr. Syst.
Kazuteru Namba, Fabrizio Lombardi
2017 C conf
L band circularly polarized SAR onboard microsatellite.
IGARSS
Josaphat Tetuko Sri Sumantyo, Nobuyoshi Imura, Shunsuke Onishi, Tetsuo Yasaka, Robertus Heru Triharjanto, Koichi Ito, Steven Gao, Kazuteru Namba, Katsumi Hattori, Fumio Yamazaki, Chiharu Hongo, Akira Kato, Daniele Perissin
2016 J jnl
A Calibration Technique for DVMC with Delay Time Controllable Inverter.
IPSJ Trans. Syst. LSI Des. Methodol.
Ri Cui, Kazuteru Namba
2016 J jnl
A Coding Scheme for Write Time Improvement of Phase Change Memory (PCM) Systems.
IEEE Trans. Multi Scale Comput. Syst.
Kazuteru Namba, Fabrizio Lombardi
2016 J jnl
A Novel Scheme for Tolerating Single Event/Multiple Bit Upsets (SEU/MBU) in Non-Volatile Memories.
IEEE Trans. Computers
Wei Wei, Kazuteru Namba, Yong-Bin Kim, Fabrizio Lombardi
2016 — conf
Construction of a soft error (SEU) hardened Latch with high critical charge.
DFT
Hiroki Ueno, Kazuteru Namba
2016 — conf
Design and Comparative Evaluation of a Hybrid Cache Memory at Architectural Level.
ACM Great Lakes Symposium on VLSI
Wei Wei, Kazuteru Namba, Fabrizio Lombardi
2016 J jnl
Parallel Decodable Multi-Level Unequal Burst Error Correcting Codes for Memories of Approximate Systems.
IEEE Trans. Computers
Kazuteru Namba, Fabrizio Lombardi
2016 J jnl
Single Multiscale-Symbol Error Correction Codes for Multiscale Storage Systems.
IEEE Trans. Computers
Kazuteru Namba, Fabrizio Lombardi
2015 — conf
A low area calibration technique of TDC using variable clock generator for accurate on-line delay measurement.
ISQED
Kentaroh Katoh, Kazuteru Namba
2015 J jnl
Non-Binary Orthogonal Latin Square Codes for a Multilevel Phase Charge Memory (PCM).
IEEE Trans. Computers
Kazuteru Namba, Fabrizio Lombardi
2015 — conf
Novel Designs of Embedded Hybrid Cells for High Performance Memory Circuits.
ACM Great Lakes Symposium on VLSI
Fabrizio Lombardi, Wei Wei, Kazuteru Namba
2015 J jnl
Parallel Decodable Two-Level Unequal Burst Error Correcting Codes.
IEEE Trans. Computers
Kazuteru Namba, Fabrizio Lombardi
2014 — conf
Designs and analysis of non-volatile memory cells for single event upset (SEU) tolerance.
DFT
Wei Wei, Fabrizio Lombardi, Kazuteru Namba
2014 J jnl
Improving Small-Delay Fault Coverage of On-Chip Delay Measurement by Segmented Scan and Test Point Insertion.
IEICE Trans. Inf. Syst.
Wenpo Zhang, Kazuteru Namba, Hideo Ito
2014 — conf
New 4T-based DRAM cell designs.
ACM Great Lakes Symposium on VLSI
Wei Wei, Kazuteru Namba, Fabrizio Lombardi
2014 J jnl
Scan Shift Time Reduction Using Test Compaction for On-Chip Delay Measurement.
IEICE Trans. Inf. Syst.
Wenpo Zhang, Kazuteru Namba, Hideo Ito
2013 — conf
A novel scheme for concurrent error detection of OLS parallel decoders.
DFTS
Kazuteru Namba, Fabrizio Lombardi
2013 J jnl
Design for Delay Measurement Aimed at Detecting Small Delay Defects on Global Routing Resources in FPGA.
IEICE Trans. Inf. Syst.
Kazuteru Namba, Nobuhide Takashina, Hideo Ito
2013 J jnl
Extending Non-Volatile Operation to DRAM Cells.
IEEE Access
Wei Wei, Kazuteru Namba, Fabrizio Lombardi
2013 J jnl
Improving Test Coverage by Measuring Path Delay Time Including Transmission Time of FF.
IEICE Trans. Inf. Syst.
Wenpo Zhang, Kazuteru Namba, Hideo Ito
2013 — conf
Testing of switch blocks in TSV-reduced Three-Dimensional FPGA.
DFTS
Kouta Maebashi, Kazuteru Namba, Masato Kitakami
2013 J jnl
Timing-Error-Detecting Dual-Edge-Triggered Flip-Flop.
J. Electron. Test.
Kazuteru Namba, Takashi Katagiri, Hideo Ito
2012 J jnl
An On-Chip Delay Measurement Technique Using Signature Registers for Small-Delay Defect Detection.
IEEE Trans. Very Large Scale Integr. Syst.
Kentaroh Katoh, Kazuteru Namba, Hideo Ito
2012 — conf
Dual-edge-triggered FF with timing error detection capability.
DFT
Kazuteru Namba, Takashi Katagiri, Hideo Ito
2012 — conf
Improving small-delay fault coverage for on-chip delay measurement.
DFT
Wenpo Zhang, Kazuteru Namba, Hideo Ito
2012 — conf
NoC Dynamically Reconfigurable as TAM.
Asian Test Symposium
Takieddine Sbiai, Kazuteru Namba
2011 J jnl
Construction of BILBO FF with Soft-Error-Tolerant Capability.
IEICE Trans. Inf. Syst.
Kazuteru Namba, Hideo Ito
2011 J jnl
Scan FF Reordering for Test Volume Reduction in Chiba-scan Architecture.
IPSJ Trans. Syst. LSI Des. Methodol.
Kiyonori Matsumoto, Kazuteru Namba, Hideo Ito
2011 J jnl
Test Sets for Robust Path Delay Fault Testing on Two-Rail Logic Circuits.
IEEE Trans. Computers
Kazuteru Namba, Hideo Ito
2010 — conf
A Low Area On-chip Delay Measurement System Using Embedded Delay Measurement Circuit.
Asian Test Symposium
Kentaroh Katoh, Kazuteru Namba, Hideo Ito
2010 J jnl
Chiba Scan Delay Fault Testing with Short Test Application Time.
J. Electron. Test.
Kazuteru Namba, Hideo Ito
2010 J jnl
Construction of SEU Tolerant Flip-Flops Allowing Enhanced Scan Delay Fault Testing.
IEEE Trans. Very Large Scale Integr. Syst.
Kazuteru Namba, Takashi Ikeda, Hideo Ito
2010 C conf
Quantitative Evaluation of Integrity for Remote System Using the Internet.
PRDC
Masato Kitakami, Hiroshi Konno, Kazuteru Namba, Hideo Ito
2010 — conf
Single Event Induced Double Node Upset Tolerant Latch.
DFT
Kazuteru Namba, Masatoshi Sakata, Hideo Ito
2010 J jnl
Single-Event-Upset Tolerant RS Flip-Flop with Small Area.
IEICE Trans. Inf. Syst.
Kazuteru Namba, Kengo Nakashima, Hideo Ito
2010 — conf
Soft Error Tolerant BILBO FF.
DFT
Kazuteru Namba, Hideo Ito
2009 — conf
A Delay Measurement Technique Using Signature Registers.
Asian Test Symposium
Kentaroh Katoh, Toru Tanabe, Haque Md Zahidul, Kazuteru Namba, Hideo Ito
2009 J jnl
Analysis of Path Delay Fault Testability for Two-Rail Logic Circuits.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Kazuteru Namba, Hideo Ito
2009 J jnl
Construction of Soft-Error-Tolerant FF with Wide Error Pulse Detecting Capability.
IEICE Trans. Inf. Syst.
Shuangyu Ruan, Kazuteru Namba, Hideo Ito
2009 C conf
Dependability Evaluation for Internet-Based Remote Systems.
PRDC
Masato Kitakami, Akihiro Katada, Kazuteru Namba, Hideo Ito
2009 J jnl
Design for Delay Fault Testability of 2-Rail Logic Circuits.
IEICE Trans. Inf. Syst.
Kentaroh Katoh, Kazuteru Namba, Hideo Ito
2009 J jnl
Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths.
IEICE Trans. Inf. Syst.
Kentaroh Katoh, Kazuteru Namba, Hideo Ito
2009 J jnl
Test Compression for IP Core Testing with Reconfigurable Network and Fixing-Flipping Coding.
J. Electron. Test.
Kazuteru Namba, Yoshikazu Matsui, Hideo Ito
2009 J jnl
Test Compression for Robust Testable Path Delay Fault Testing Using Interleaving and Statistical Coding.
IEICE Trans. Inf. Syst.
Kazuteru Namba, Hideo Ito
2009 — conf
Testing of Switch Blocks in Three-Dimensional FPGA.
DFT
Takumi Hoshi, Kazuteru Namba, Hideo Ito
2008 J jnl
Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger.
J. Electron. Test.
Yoichi Sasaki, Kazuteru Namba, Hideo Ito
2008 — conf
Delay Fault Testability on Two-Rail Logic Circuits.
DFT
Kazuteru Namba, Hideo Ito
2008 C conf
Path Delay Fault Test Set for Two-Rail Logic Circuits.
PRDC
Kazuteru Namba, Hideo Ito
2008 — conf
Soft Error Hardened FF Capable of Detecting Wide Error Pulse.
DFT
Shuangyu Ruan, Kazuteru Namba, Hideo Ito
2008 J jnl
Two-Stage Stuck-at Fault Test Data Compression Using Scan Flip-Flops with Delay Fault Testability.
Inf. Media Technol.
Kentaroh Katoh, Kazuteru Namba, Hideo Ito
2008 J jnl
Two-Stage Stuck-at Fault Test Data Compression Using Scan Flip-Flops with Delay Fault Testability.
IPSJ Trans. Syst. LSI Des. Methodol.
Kentaroh Katoh, Kazuteru Namba, Hideo Ito
2007 J jnl
Nonbinary single-symbol error correcting, adjacent two-symbol transposition error correcting codes over integer rings.
Syst. Comput. Jpn.
Kazuteru Namba, Eiji Fujiwara
2007 — conf
Soft Error Hardened Latch Scheme for Enhanced Scan Based Delay Fault Testing.
DFT
Takashi Ikeda, Kazuteru Namba, Hideo Ito
2006 — conf
Interleaving of Delay Fault Tes Data for Efficient Test Compression with Statistical Coding.
ATS
Kazuteru Namba, Hideo Ito
2006 J jnl
Proposal of Testable Multi-Context FPGA Architecture.
IEICE Trans. Inf. Syst.
Kazuteru Namba, Hideo Ito
2006 J jnl
Redundant Design for Wallace Multiplier.
IEICE Trans. Inf. Syst.
Kazuteru Namba, Hideo Ito
2006 — conf
Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit.
DFT
Yoichi Sasaki, Kazuteru Namba, Hideo Ito
2005 C conf
Design of Defect Tolerant Wallace Multiplier.
PRDC
Kazuteru Namba, Hideo Ito
2005 J jnl
Deterministic Delay Fault BIST Using Adjacency Test Pattern Generation.
IEICE Trans. Inf. Syst.
Kazuteru Namba, Hideo Ito
2005 J jnl
Scan Design for Two-Pattern Test without Extra Latches.
IEICE Trans. Inf. Syst.
Kazuteru Namba, Hideo Ito
2002 J jnl
Two-Level Unequal Error Protection Codes with Burst and Bit Error Correcting Capabilities.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Kazuteru Namba, Eiji Fujiwara
2001 J jnl
A class of systematic m-ary single-symbol error correcting codes.
Syst. Comput. Jpn.
Kazuteru Namba, Eiji Fujiwara
2001 — conf
Unequal Error Protection Codes with Two-Level Burst and Bit Error Correcting Capabilities.
DFT
Kazuteru Namba, Eiji Fujiwara