Kazutami Arimoto

94 papers A* 1A 4B 1C 3Journal 50Unranked 35

Year	Rank	Type	Title / Venue / Authors
2024	—	`conf`	Distributed Hierarchical AI Architecture for Meta-Described Local Dynamic Maps in Autonomous Driving. IIAI-AAI Hiroshi Miyata, Kazutami Arimoto, Masatoshi Saitoh, Atsushi Hayami, Hisayoshi Mizuno, Yukihiko Shimazu, Tomoyuki Yokogawa
2023	—	`conf`	Applying Symbolic Model Checking to Node-graph Style Game Scripts with Time Constraints. GCCE Ryugo Tanaka, Tomoyuki Yokogawa, Sousuke Amasaki, Hirohisa Aman, Kazutami Arimoto
2023	—	`conf`	Enhancing the Generalization Performance of Drowsiness Estimation AI in Drivers Using Time-Series Data from FAUs with Limited Datasets. IIAI-AAI-Winter Tomoya Kubo, Tomoyuki Yokogawa, Kazutami Arimoto, Masaki Hokari, Isao Kayano
2022	—	`conf`	28-m W Fully Embedded AI Techniques with On-site Learning for Low-Power Handy Tactile Sensing System. VLSI-DAT Yuji Yano, Hisashi Iwamoto, Takuma Yoshimura, Yoshihiro Nishida, Tatsuya Mori, Kiyotaka Komoku, Hidekuni Takao, Kazutami Arimoto
2022	—	`conf`	A Visual Modeling Environment for the nuXmv Model Checker Intended for Novice Users. IIAI-AAI Kazuma Toyota, Tomoyuki Yokogawa, Sousuke Amasaki, Hirohisa Aman, Kazutami Arimoto
2022	A*	`conf`	Verifying Game Logic in Unreal Engine 5 Blueprint Visual Scripting System Using Model Checking. ASE Kazuki Wayama, Tomoyuki Yokogawa, Sousuke Amasaki, Hirohisa Aman, Kazutami Arimoto
2021	—	`conf`	Localized Data Transfer System by Vehicles and Cellular Base Station in Local Area. ICC Workshops Hiroshi Miyata, Kazutami Arimoto
2021	—	`conf`	New Value Creation by Nano-Tactile Sensor Chip Exceeding our Fingertip Discrimination Ability. HCS Hidekuni Takao, Kazuki Watatani, Kazutami Arimoto
2020	—	`conf`	A Edge Master Computing for Pineapple Monitoring System with Drone and Data-management. IIAI-AAI Tomoki Kobayashi, Tomoyuki Yokogawa, Nao Igawa, Yoichiro Sato, Kimihoro Sugino, Hiroshi Miyata, Satoshi Fujii, Kazutami Arimoto
2020	—	`conf`	A Node-Style Visual Programming Environment for the nuXmv Model Checker. GCCE Hayato Naito, Tomoyuki Yokogawa, Nao Igawa, Sousuke Amasaki, Hirohisa Aman, Kazutami Arimoto
2020	—	`conf`	Model Checking of Visual Scripts Created by UE4 Blueprints. IIAI-AAI Nao Igawa, Tomoyuki Yokogawa, Mami Takahashi, Kazutami Arimoto
2020	J	`jnl`	Symbolic Representation of Time Petri Nets for Efficient Bounded Model Checking. IEICE Trans. Inf. Syst. Nao Igawa, Tomoyuki Yokogawa, Sousuke Amasaki, Masafumi Kondo, Yoichiro Sato, Kazutami Arimoto
2019	—	`conf`	A Compact Low Power AI Module Mounted on Drone for Plant Monitor System. IIAI-AAI Tomoki Kobayashi, Tomoyuki Yokogawa, Nao Igawa, Yoichiro Sato, Satoshi Fujii, Kazutami Arimoto
2019	—	`conf`	Consistency Verification of UML Sequence Diagrams Modeling Wireless Sensor Networks. IIAI-AAI Akira Matsumoto, Tomoyuki Yokogawa, Sousuke Amasaki, Hirohisa Aman, Kazutami Arimoto
2019	—	`conf`	Radio link design for ITS integrated network using drone. APWCS Satoshi Fujii, Issei Nakaema, Kei Miyagi, Shouichiro Tanifuji, Noriaki Yoshikawa, Kensaku Kinoshita, Kazutami Arimoto
2018	—	`conf`	Interpolation Based Unbounded Model Checking for Time Petri Nets. GCCE Nao Igawa, Tomoyuki Yokogawa, Sousuke Amasaki, Kiyotaka Komoku, Yoichiro Sato, Kazutami Arimoto
2017	—	`conf`	A smart low power R-R-I heartbeat monitor system with contactless UWB sensor. ISOCC Kazutami Arimoto, Daichi Yamashita, Nao Igawa, Tomoyuki Yokogawa, Yoichiro Sato, Isao Kayano, Akio Shiratori
2017	B	`conf`	Tool Support for Consistency Verification of UML Diagrams. PROFES Salilthip Phuklang, Tomoyuki Yokogawa, Pattara Leelaprute, Kazutami Arimoto
2016	—	`conf`	3D ISOCC Kiyotaka Komoku, Kazutami Arimoto, Tomoyuki Yokogawa, Hitoshi Yamauchi, Yoichiro Sato, Hidekuni Takao
2016	J	`jnl`	A Field Programmable Sequencer and Memory with Middle Grained Programmability Optimized for MCU Peripherals. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yoshifumi Kawamura, Naoya Okada, Yoshio Matsuda, Tetsuya Matsumura, Hiroshi Makino, Kazutami Arimoto
2016	—	`conf`	A Serial Booth Multiplier Using Ring Oscillator. CANDAR Daichi Okamoto, Masafumi Kondo, Tomoyuki Yokogawa, Yoshihiro Sejima, Kazutami Arimoto, Yoichiro Sato
2015	J	`jnl`	Bounded model checking of Time Petri Nets using SAT solver. IEICE Electron. Express Tomoyuki Yokogawa, Masafumi Kondo, Hisashi Miyazaki, Sousuke Amasaki, Yoichiro Sato, Kazutami Arimoto
2014	—	`conf`	F5: Low-power radios for sensor networks. ISSCC Woogeun Rhee, Gangadhar Burra, Kazutami Arimoto, Pieter Harpe, Brian Otis, David Ruffieux
2014	C	`conf`	The LSI implementation of a memory based field programmable device for MCU peripherals. DDECS Tetsuya Matsumura, Naoya Okada, Yoshifumi Kawamura, Koji Nii, Kazutami Arimoto, Hiroshi Makino, Yoshio Matsuda
2013	C	`conf`	Consistency Verification of UML Diagrams Based on Process Bisimulation. PRDC Tomoyuki Yokogawa, Sousuke Amasaki, Keisuke Okazaki, Yoichiro Sato, Kazutami Arimoto, Hisashi Miyazaki
2013	J	`jnl`	Low-Power On-Chip Charge-Recycling DC-DC Conversion Circuit and System. IEEE J. Solid State Circuits Kazuhiro Ueda, Fukashi Morishita, Shunsuke Okura, Leona Okamura, Tsutomu Yoshihara, Kazutami Arimoto
2012	—	`conf`	What's next in robots? ∼Sensing, processing, networking toward human brain and body. ISSCC Kazutami Arimoto, Sam Kavusi, Kenneth Salisbury
2011	J	`jnl`	A Scalable Massively Parallel Processor for Real-Time Image Processing. IEEE J. Solid State Circuits Takashi Kurafuji, Masaru Haraguchi, Masami Nakajima, Tetsu Nishijima, Tetsushi Tanizaki, Hiroyuki Yamasaki, Takeaki Sugimura, Yuta Imai, Masakatsu Ishizaki, Takeshi Kumaki, Kan Murata, Kanako Yoshida, Eisuke Shimomura, Hideyuki Noda, Yoshihiro Okuno, Shunsuke Kamijo, Tetsushi Koide, Hans Jürgen Mattausch, Kazutami Arimoto
2011	—	`conf`	An 80 Gbps dependable multicore communication SoC with PCI express I/F and intelligent interrupt controller. COOL Chips Sugako Otani, Hiroyuki Kondo, Itaru Nonomura, Atsuyuki Ikeya, Minoru Uemura, Katsushi Asahina, Kazutami Arimoto, Shin'ichi Miura, Toshihiro Hanawa, Taisuke Boku, Mitsuhisa Sato
2011	—	`conf`	An 80Gb/s dependable communication SoC with PCI express I/F and 8 CPUs. ISSCC Sugako Otani, Hiroyuki Kondo, Itaru Nonomura, Atsuyuki Ikeya, Minoru Uemura, Yasushi Hayakawa, Takeshi Oshita, Satoshi Kaneko, Katsushi Asahina, Kazutami Arimoto, Shin'ichi Miura, Toshihiro Hanawa, Taisuke Boku, Mitsuhisa Sato
2011	—	`conf`	Implementation and evaluation of FAST corner detection on the massively parallel embedded processor MX-G. CVPR Workshops Yushi Moko, Yoshihiro Watanabe, Takashi Komuro, Masatoshi Ishikawa, Masami Nakajima, Kazutami Arimoto
2011	J	`jnl`	Low Power Platform for Embedded Processor LSIs. IEICE Trans. Electron. Toru Shimizu, Kazutami Arimoto, Osamu Nishii, Sugako Otani, Hiroyuki Kondo
2011	—	`conf`	PEARL and PEACH: A Novel PCI Express Direct Link and Its Implementation. IPDPS Workshops Toshihiro Hanawa, Taisuke Boku, Shin'ichi Miura, Mitsuhisa Sato, Kazutami Arimoto
2010	—	`conf`	A scalable massively parallel processor for real-time image processing. ISSCC Takashi Kurafuji, Masaru Haraguchi, Masami Nakajima, Takayuki Gyohten, Tetsu Nishijima, Hiroyuki Yamasaki, Yuta Imai, Masakatsu Ishizaki, Takeshi Kumaki, Yoshihiro Okuno, Tetsushi Koide, Hans Jürgen Mattausch, Kazutami Arimoto
2010	—	`conf`	Dependable SRAM with enhanced read-/write-margins by fine-grained assist bias control for low-voltage operation. SoCC Koji Nii, Makoto Yabuuchi, Hidehiro Fujiwara, Hirofumi Nakano, Kazuya Ishihara, Hiroyuki Kawai, Kazutami Arimoto
2010	—	`conf`	Fusion of MEMS and circuits. ISSCC Satoshi Shigematsu, Kazutami Arimoto, Christoph Hagleitner
2010	—	`conf`	PEARL: Power-Aware, Dependable, and High-Performance Communication Link Using PCI Express. GreenCom/CPSCom Toshihiro Hanawa, Taisuke Boku, Shin'ichi Miura, Mitsuhisa Sato, Kazutami Arimoto
2009	J	`jnl`	A Continuous-Adaptive DDRx Interface with Flexible Round-Trip-Time and Full Self Loop-Backed AC Test. IEICE Trans. Electron. Masaru Haraguchi, Tokuya Osawa, Akira Yamazaki, Chikayoshi Morishima, Toshinori Morihara, Yoshikazu Morooka, Yoshihiro Okuno, Kazutami Arimoto
2009	J	`jnl`	Heterogeneous Multicore SoC With SiP for Secure Multimedia Applications. IEEE J. Solid State Circuits Hiroyuki Kondo, Sugako Otani, Masami Nakajima, Osamu Yamamoto, Norio Masui, Naoto Okumura, Mamoru Sakugawa, Masaya Kitao, Koichi Ishimi, Masayuki Sato, Fumitaka Fukuzawa, Satoshi Imasu, Nobuhiro Kinoshita, Yusuke Ota, Kazutami Arimoto, Toru Shimizu
2009	J	`jnl`	On-Chip Memory Power-Cut Scheme Suitable for Low Power SoC Platform. IEICE Trans. Electron. Hiroki Shimano, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto
2008	J	`jnl`	Design and Implementation of a Configurable Heterogeneous Multicore SoC With Nine CPUs and Two Matrix Processors. IEEE J. Solid State Circuits Hiroyuki Kondo, Masami Nakajima, Norio Masui, Sugako Otani, Naoto Okumura, Yukari Takata, Takashi Nasu, Hirokazu Takata, Takashi Higuchi, Mamoru Sakugawa, Hayato Fujiwara, Kazuya Ishida, Koichi Ishimi, Satoshi Kaneko, Teruyuki Itoh, Masayuki Sato, Osamu Yamamoto, Kazutami Arimoto
2008	—	`conf`	Heterogeneous multicore SoC for secure multimedia applications. CICC Hiroyuki Kondo, Masami Nakajima, Sugako Otani, Osamu Yamamoto, Norio Masui, Naoto Okumura, Mamoru Sakugawa, Masaya Kitao, Koichi Ishimi, Masayuki Sato, Fumitaka Fukuzawa, Kazuhiro Inaoka, Yoshihiro Saito, Kazutami Arimoto, Toru Shimizu
2008	J	`jnl`	Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor. IEICE Trans. Electron. Takeshi Kumaki, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Takayuki Gyohten, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito
2007	J	`jnl`	A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI. IEICE Trans. Electron. Fukashi Morishita, Hideyuki Noda, Isamu Hayashi, Takayuki Gyohten, Mako Okamoto, Takashi Ipposhi, Shigeto Maegawa, Katsumi Dosaka, Kazutami Arimoto
2007	J	`jnl`	A Configurable Enhanced TTRAM Macro for System-Level Power Management Unified Memory. IEEE J. Solid State Circuits Fukashi Morishita, Isamu Hayashi, Takayuki Gyohten, Hideyuki Noda, Takashi Ipposhi, Hiroki Shimano, Katsumi Dosaka, Kazutami Arimoto
2007	—	`conf`	A Continuous-Adaptive DDR2 Interface with Flexible Round-Trip-Time and Full Self Loop-Backed AC Test. ISSCC Masaru Haraguchi, Tokuya Osawa, Akira Yamazaki, Chikayoshi Morishima, Toshinori Morihara, Yoshikazu Morooka, Yoshihiro Okuno, Kazutami Arimoto
2007	J	`jnl`	A High-Density Scalable Twin Transistor RAM (TTRAM) With Verify Control for SOI Platform Memory IPs. IEEE J. Solid State Circuits Kazutami Arimoto, Fukashi Morishita, Isamu Hayashi, Katsumi Dosaka, Hiroki Shimano, Takashi Ipposhi
2007	J	`jnl`	A Voltage Scalable Advanced DFM RAM with Accelerated Screening for Low Power SoC Platform. IEICE Trans. Electron. Hiroki Shimano, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto
2007	J	`jnl`	Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor. IEICE Trans. Inf. Syst. Takeshi Kumaki, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito
2007	J	`jnl`	Continuous Design Efforts for Ubiquitous Network Era under the Physical Limitation of Advanced CMOS. IEICE Trans. Electron. Kazutami Arimoto, Toshihiro Hattori, Hidehiro Takata, Atsushi Hasegawa, Toru Shimizu
2007	—	`conf`	Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor. ISMVL Hirokatsu Shirahama, Akira Mochizuki, Takahiro Hanyu, Masami Nakajima, Kazutami Arimoto
2007	C	`conf`	Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing Engine. ISCAS Takeshi Kumaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito
2007	J	`jnl`	Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer. IEICE Trans. Inf. Syst. Takeshi Kumaki, Yasuto Kuroda, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito
2007	J	`jnl`	The Circuits and Robust Design Methodology of the Massively Parallel Processor Based on the Matrix Architecture. IEEE J. Solid State Circuits Hideyuki Noda, Tetsushi Tanizaki, Takayuki Gyohten, Katsumi Dosaka, Masami Nakajima, Katsuya Mizumoto, Kanako Yoshida, Takenobu Iwao, Tetsu Nishijima, Yoshihiro Okuno, Kazutami Arimoto
2007	J	`jnl`	The Design and Implementation of the Massively Parallel Processor Based on the Matrix Architecture. IEEE J. Solid State Circuits Hideyuki Noda, Masami Nakajima, Katsumi Dosaka, Kiyoshi Nakata, Motoki Higashida, Osamu Yamamoto, Katsuya Mizumoto, Tetsushi Tanizaki, Takayuki Gyohten, Yoshihiro Okuno, Hiroyuki Kondo, Yukihiko Shimazu, Kazutami Arimoto, Kazunori Saito, Toru Shimizu
2006	—	`conf`	A 40GOPS 250mW massively parallel processor based on matrix architecture. ISSCC Masami Nakajima, Hideyuki Noda, Katsumi Dosaka, Kiyoshi Nakata, Motoki Higashida, Osamu Yamamoto, Katsuya Mizumoto, Hiroyuki Kondo, Yukihiko Shimazu, Kazutami Arimoto, Kazunori Saitoh, Toru Shimizu
2006	J	`jnl`	A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC. IEICE Trans. Electron. Hideyuki Noda, Katsumi Dosaka, Hans Jürgen Mattausch, Tetsushi Koide, Fukashi Morishita, Kazutami Arimoto
2006	—	`conf`	A Scalable ET2RAM (SETRAM) with Verify Control for SoC Platform Memory IP on SOI. CICC Kazutami Arimoto, Fukashi Morishita, Isamu Hayashi, Tetsushi Tanizaki, Takashi Ipposhi, Katsumi Dosaka
2006	J	`jnl`	An On-Chip Supply-Voltage Control System Considering PVT Variations for Worst-Caseless Lower Voltage SoC Design. IEICE Trans. Electron. Takayuki Gyohten, Fukashi Morishita, Isamu Hayashi, Mako Okamoto, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Yasutaka Horiba
2005	J	`jnl`	A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications. IEEE J. Solid State Circuits Fukashi Morishita, Isamu Hayashi, Hideto Matsuoka, Kazuhiro Takahashi, Kuniyasu Shigeta, Takayuki Gyohten, Mitsutaka Niiro, Hideyuki Noda, Mako Okamoto, Atsushi Hachisuka, Atsushi Amo, Hiroki Shinkawata, Tatsuo Kasaoka, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara
2005	J	`jnl`	A 322 MHz random-cycle embedded DRAM with high-accuracy sensing and tuning. IEEE J. Solid State Circuits Masahisa Iida, Naoki Kuroda, Hidefumi Otsuka, Masanobu Hirose, Yuji Yamasaki, Kiyoto Ohta, Kazuhiko Shimakawa, Takashi Nakabayashi, Hiroyuki Yamauchi, Tomohiko Sano, Takayuki Gyohten, Masanao Maruta, Akira Yamazaki, Fukashi Morishita, Katsumi Dosaka, Masahiko Takeuchi, Kazutami Arimoto
2005	J	`jnl`	A CAM-Based Signature-Matching Co-processor with Application-Driven Power-Reduction Features. IEICE Trans. Electron. Kazunari Inoue, Hideyuki Noda, Kazutami Arimoto, Hans Jürgen Mattausch, Tetsushi Koide
2005	J	`jnl`	A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros. IEICE Trans. Electron. Akira Yamazaki, Fukashi Morishita, Naoya Watanabe, Teruhiko Amano, Masaru Haraguchi, Hideyuki Noda, Atsushi Hachisuka, Katsumi Dosaka, Kazutami Arimoto, Setsuo Wake, Hideyuki Ozaki, Tsutomu Yoshihara
2005	—	`conf`	A capacitorless twin-transistor random access memory (TTRAM) on SOI. CICC Fukashi Morishita, Hideyuki Noda, Takayuki Gyohten, Mako Okamoto, Takashi Ipposhi, Shigeto Maegawa, Katsumi Dosaka, Kazutami Arimoto
2005	J	`jnl`	A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture. IEEE J. Solid State Circuits Hideyuki Noda, Kazunari Inoue, Masayuki Kuroiwa, Futoshi Igaue, Kouji Yamamoto, Hans Jürgen Mattausch, Tetsushi Koide, Atsushi Amo, Atsushi Hachisuka, Shinya Soeda, Isamu Hayashi, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara
2005	—	`conf`	A soft-error-immune maintenance-free TCAM architecture with associated embedded DRAM. CICC Hideyuki Noda, Katsumi Dosaka, Fukashi Morishita, Kazutami Arimoto
2005	—	`conf`	CAM-based VLSI architecture for Huffman coding with real-time optimization of the code word table [image coding example]. ISCAS (5) Takeshi Kumaki, Yasuto Kuroda, Tetsushi Koide, Hans Jürgen Mattausch, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito
2005	J	`jnl`	Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh. IEICE Trans. Electron. Hideyuki Noda, Kazunari Inoue, Hans Jürgen Mattausch, Tetsushi Koide, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara
2003	J	`jnl`	A Low Power Embedded DRAM Macro for Battery-Operated LSIs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takeshi Fujino, Akira Yamazaki, Yasuhiko Taito, Mitsuya Kinoshita, Fukashi Morishita, Teruhiko Amano, Masaru Haraguchi, Makoto Hatakenaka, Atsushi Amo, Atsushi Hachisuka, Kazutami Arimoto, Hideyuki Ozaki
2003	J	`jnl`	An embedded DRAM with a 143-MHz SRAM interface using a sense-synchronized read/write. IEEE J. Solid State Circuits Yasuhiko Taito, Tetsushi Tanizaki, Mitsuya Kinoshita, Futoshi Igaue, Takeshi Fujino, Kazutami Arimoto
2001	J	`jnl`	Design methodology of embedded DRAM with virtual-socket architecture. IEEE J. Solid State Circuits Tadaaki Yamauchi, Mitsuya Kinoshita, Teruhiko Amano, Katsumi Dosaka, Kazutami Arimoto, Hideyuki Ozaki, Michihiro Yamada, Tsutomu Yoshihara
2001	A	`conf`	Test cost reduction by at-speed BISR for embedded DRAMs. ITC Yoshihiro Nagura, Michael Mullins, Anthony Sauvageau, Yoshinoro Fujiwara, Katsuya Furue, Ryuji Ohmura, Tatsunori Komoike, Takenori Okitaka, Tetsushi Tanizaki, Katsumi Dosaka, Kazutami Arimoto, Yukiyoshi Koda, Tetsuo Tada
2000	J	`jnl`	High-performance embedded SOI DRAM architecture for the low-power supply. IEEE J. Solid State Circuits Tadaaki Yamauchi, Fukashi Morishita, Shigenobu Maeda, Kazutami Arimoto, Kazuyasu Fujishima, Hideyuki Ozaki, Tsutomu Yoshihara
1999	J	`jnl`	A 5.3-GB/s embedded SDRAM core with slight-boost scheme. IEEE J. Solid State Circuits Akira Yamazaki, Tadato Yamagata, Makoto Hatakenaka, Atsushi Miyanishi, Isao Hayashi, Shigeki Tomishima, Atsuo Mangyo, Yoshio Yukinari, Takashi Tatsumi, Masashi Matsumura, Kazutami Arimoto, Michihiro Yamada
1998	J	`jnl`	400-MHz random column operating SDRAM techniques with self-skew compensation. IEEE J. Solid State Circuits Takeshi Hamamoto, Masaki Tsukude, Kazutami Arimoto, Yasuhiro Konishi, Takayuki Miyamoto, Hideyuki Ozaki, Michihiro Yamada
1997	J	`jnl`	A 1-V 46-ns 16-Mb SOI-DRAM with body control technique. IEEE J. Solid State Circuits Ken'ichi Shimomura, Hiroki Shimano, Narumi Sakashita, Fumihiro Okuda, Toshiyuki Oashi, Yasuo Yamaguchi, Takahisa Eimori, Masahide Inuishi, Kazutami Arimoto, Shigeto Maegawa, Yasuo Inoue, Shinji Komori, Kazuo Kyuma
1997	J	`jnl`	A 1.2- to 3.3-V wide voltage-range/low-power DRAM with a charge-transfer presensing scheme. IEEE J. Solid State Circuits Masaki Tsukude, Shigehiro Kuge, Takeshi Fujino, Kazutami Arimoto
1997	J	`jnl`	High-speed/high-bandwidth design methodologies for on-chip DRAM core multimedia system LSI's. IEEE J. Solid State Circuits Takahiro Tsuruda, Mako Kobayashi, Masaki Tsukude, Tadato Yamagata, Kazutami Arimoto, Michihiro Yamada
1996	J	`jnl`	A 1.6-GB/s data-rate 1-Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture. IEEE J. Solid State Circuits Narumi Sakashita, Yasuhiko Nitta, Ken'ichi Shimomura, Fumihiro Okuda, Hiroki Shimano, Satoshi Yamakawa, Masaki Tsukude, Kazutami Arimoto, Shinji Baba, Shinji Komori, Kazuo Kyuma, Akihiko Yasuoka, Haruhiko Abe
1996	J	`jnl`	SOI-DRAM circuit technologies for low power high speed multigiga scale memories. IEEE J. Solid State Circuits Shigehiro Kuge, Fukashi Morishita, Takahiro Tsuruda, Shigeki Tomishima, Masaki Tsukude, Tadato Yamagata, Kazutami Arimoto
1995	J	`jnl`	Low voltage circuit design techniques for battery-operated and/or giga-scale DRAMs. IEEE J. Solid State Circuits Tadato Yamagata, Shigeki Tomishima, Masaki Tsukude, Takahiro Tsuruda, Yasushi Hashizume, Kazutami Arimoto
1994	J	`jnl`	A well-synchronized sensing/equalizing method for sub-1.0-V operating advanced DRAMs. IEEE J. Solid State Circuits Tsukasa Ooishi, Mikio Asakura, Shigeki Tomishima, Hideto Hidaka, Kazutami Arimoto, Kazuyasu Fujishima
1993	J	`jnl`	Highly Reliable Testing of ULSI Memories with On-Chip Voltage-Down Converters. IEEE Des. Test Comput. Masaki Tsukude, Kazutami Arimoto, Hideto Hidaka, Yasuhiro Konishi, Masanori Hayashikoshi, Katsuhiro Suma, Kazuyasu Fujishima
1992	J	`jnl`	A 34-ns 16-Mb DRAM with controllable voltage down-converter. IEEE J. Solid State Circuits Hideto Hidaka, Kazutami Arimoto, Kazutoshi Hirayama, Masanori Hayashikoshi, Mikio Asakura, Masaki Tsukude, Tsukasa Oishi, Shinji Kawai, Katsuhiro Suma, Yasuhiro Konishi, Koji Tanaka, Wataru Wakamiya, Yoshikazu Ohno, Kazuyasu Fujishima
1992	A	`conf`	A Testing Technique for ULSI Memory with On-Chip Voltage Down Converter. ITC Masaki Tsukude, Kazutami Arimoto, Hideto Hidaka, Yasuhiro Konishi, Masanori Hayashikoshi, Katsunori Suma, Kazuyasu Fujishima
1992	J	`jnl`	A dual-mode sensing scheme of capacitor-coupled EEPROM cell. IEEE J. Solid State Circuits Masanori Hayashikoshi, Hideto Hidaka, Kazutami Arimoto, Kazuyasu Fujishima
1992	J	`jnl`	A high-density dual-port memory cell operation and array architecture for ULSI DRAMs. IEEE J. Solid State Circuits Hideto Hidaka, Kazutami Arimoto, Kazuyasu Fujishima
1992	J	`jnl`	Cell-plate line connecting complementary bit-line (C IEEE J. Solid State Circuits Mikio Asakura, Kazutami Arimoto, Hideto Hidaka, Kazuyasu Fujishima
1991	J	`jnl`	A circuit design of intelligent cache DRAM with automatic write-back capability. IEEE J. Solid State Circuits Kazutami Arimoto, Mikio Asakura, Hideto Hidaka, Yoshio Matsuda, Kazuyasu Fujishima
1990	J	`jnl`	A speed-enhanced DRAM array architecture with embedded ECC. IEEE J. Solid State Circuits Kazutami Arimoto, Yoshio Matsuda, Kiyohiro Furutani, Masaki Tsukude, Tsukasa Ooishi, Koichiro Mashiko, Kuzuyasu Fujishima
1989	J	`jnl`	A 60-ns 3.3-V-only 16-Mbit DRAM with multipurpose register. IEEE J. Solid State Circuits Kazutami Arimoto, Kazuyasu Fujishima, Yoshio Matsuda, Masaki Tsukude, Tukasa Oishi, Wataru Wakamiya, Shin'ichi Satoh, Michihiro Yamada, Takao Nakano
1989	A	`conf`	A New Array Architecture for Parallel Testing in VLSI Memories. ITC Yoshio Matsuda, Kazutami Arimoto, Masaki Tsukude, Tsukasa Oishi, Kazuyasu Fujishima
1989	J	`jnl`	A built-in Hamming code ECC circuit for DRAMs. IEEE J. Solid State Circuits Kiyohiro Furutani, Kazutami Arimoto, Hiroshi Miyamoto, Toshifumi Kobayashi, Kenichi Yasuda, Koichiro Mashiko
1985	A	`conf`	Test Pattern Considerations for Fault Tolerant High Density DRAM. ITC Hiroshi Miyamoto, Koichiro Mashiko, Yoshikazu Morooka, Kazutami Arimoto, Michihiro Yamada, Takao Nakano