Kazushi Kawamura

65 papers A* 2A 1B 2C 5Misc 1Journal 27Unranked 27
YearRankTypeTitle / Venue / Authors
2025 J jnl
A Flip-Count-Based Dynamic Temperature Control Method for Constrained Combinatorial Optimization by Parallel Annealing Algorithms.
IEICE Trans. Inf. Syst.
Genta Inoue, Daiki Okonogi, Satoru Jimbo, Thiem Van Chu, Masato Motomura, Kazushi Kawamura
2025 J jnl
Amorphica: A Fully Connected Annealer Supporting Metamorphic Annealing and Scalable Multi Chip Integration.
IEEE Access
Daiki Okonogi, Jaehoon Yu, Satoru Jimbo, Genta Inoue, Akira Hyodo, Kota Ando, Bruno Hideki Fukushima-Kimura, Ryota Yasudo, Thiem Van Chu, Masato Motomura, Kazushi Kawamura
2025 J jnl
Annealed Mean Field Descent Is Highly Effective for Quadratic Unconstrained Binary Optimization.
CoRR
Kyo Kuroki, Thiem Van Chu, Masato Motomura, Kazushi Kawamura
2025 J jnl
Binary Quadratic Quantization: Beyond First-Order Quantization for Real-Valued Matrix Compression.
CoRR
Kyo Kuroki, Yasuyuki Okoshi, Thiem Van Chu, Kazushi Kawamura, Masato Motomura
2025 A* conf
BingoGCN: Towards Scalable and Efficient GNN Acceleration with Fine-Grained Partitioning and SLT.
ISCA
Jiale Yan, Hiroaki Ito, Yuta Nagahara, Kazushi Kawamura, Masato Motomura, Thiem Van Chu, Daichi Fujiki
2025 — conf
Boltzmann Machine Is Useful for Enhancing Search Performance of Ising Machines.
GECCO Companion
Satoru Jimbo, Kazushi Kawamura
2025 J jnl
DMSA: An Efficient Architecture for Sparse-Sparse Matrix Multiplication Based on Distribute-Merge Product Dataflow.
IEEE Trans. Very Large Scale Integr. Syst.
Yuta Nagahara, Jiale Yan, Kazushi Kawamura, Daichi Fujiki, Masato Motomura, Thiem Van Chu
2025 J jnl
Partially Frozen Random Networks Contain Compact Strong Lottery Tickets.
Trans. Mach. Learn. Res.
Hikari Otsuka, Daiki Chijiwa, Ángel López García-Arias, Yasuyuki Okoshi, Kazushi Kawamura, Thiem Van Chu, Daichi Fujiki, Susumu Takeuchi, Masato Motomura
2025 — conf
TTF-GNN: Memory-Efficient GNNs via Tensor Train Decomposition and Network Folding.
COOL CHIPS
Hiroaki Ito, Jiale Yan, Kazushi Kawamura, Masato Motomura, Thiem Van Chu, Daichi Fujiki
2025 J jnl
Uncovering Strong Lottery Tickets in Graph Transformers: A Path to Memory Efficient and Robust Graph Learning.
Trans. Mach. Learn. Res.
Hiroaki Ito, Jiale Yan, Hikari Otsuka, Kazushi Kawamura, Masato Motomura, Thiem Van Chu, Daichi Fujiki
2025 J jnl
WhiteDwarf: A Holistic Co-Design Approach to Ultra-Compact Neural Inference Acceleration.
IEEE Access
Ángel López García-Arias, Yasuyuki Okoshi, Jaehoon Yu, Junnosuke Suzuki, Hikari Otsuka, Kazushi Kawamura, Thiem Van Chu, Daichi Fujiki, Masato Motomura
2024 J jnl
A GPU-Based Ising Machine With a Multi-Spin-Flip Capability for Constrained Combinatorial Optimization.
IEEE Access
Satoru Jimbo, Tatsuhiko Shirai, Nozomu Togawa, Masato Motomura, Kazushi Kawamura
2024 — conf
A Parallel-Trial Double-Update Annealing Processor for Enabling Highly-Effective Solution Search of Constrained Combinatorial Optimization Problems.
ICFPT
Akira Hyodo, Satoru Jimbo, Daiki Okonogi, Genta Inoue, Thiem Van Chu, Masato Motomura, Kazushi Kawamura
2024 C conf
An Accurate FPGA-Based ORB Feature Extractor for SLAM with Row-Wise Keypoint Selection.
ICCE
Yuki Ichikawa, Akihiro Shioda, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
2024 A conf
Classical Thermodynamics-based Parallel Annealing Algorithm for High-speed and Robust Combinatorial Optimization.
GECCO
Kyo Kuroki, Satoru Jimbo, Thiem Van Chu, Masato Motomura, Kazushi Kawamura
2024 B conf
ETreeNet: Ensemble Model Fusing Decision Trees and Neural Networks for Small Tabular Data.
IJCNN
Tsukasa Yamakura, Kazushi Kawamura, Masato Motomura, Thiem Van Chu
2024 C conf
Efficient COO to CSR Conversion for Accelerating Sparse Matrix Processing on FPGA.
ICCE
Yuta Nagahara, Jiale Yan, Kazushi Kawamura, Masato Motomura, Thiem Van Chu
2024 J jnl
Efficient Stereo Visual Odometry on FPGA Featuring On-Chip Map Management and Pipelined Descriptor-Based Block Matching.
IEEE Access
Yuki Ichikawa, Kazushi Kawamura, Masato Motomura, Thiem Van Chu
2024 — conf
Exploiting N:M Sparsity in Quantized-Folded ResNets: Signed Multicoat Supermasks and Iterative Pruning-Quantization.
CANDAR
Akihiro Shioda, Ángel López García-Arias, Hikari Otsuka, Yuki Ichikawa, Yasuyuki Okoshi, Kazushi Kawamura, Thiem Van Chu, Daichi Fujiki, Masato Motomura
2024 C conf
Exploration of Hyperdimensional Computing Using Locality-Sensitive Hashing Mechanism on FPGA.
ICCE
Masato Watanabe, Shungo Kumazawa, Thiem Van Chu, Kazushi Kawamura, Jaehoon Yu, Masato Motomura
2024 C conf
High Throughput Datapath Design for Vision Permutator FPGA Accelerator.
ICCE
Mari Yasunaga, Junnosuke Suzuki, Masato Watanabe, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
2024 J jnl
Partial Search in a Frozen Network is Enough to Find a Strong Lottery Ticket.
CoRR
Hikari Otsuka, Daiki Chijiwa, Ángel López García-Arias, Yasuyuki Okoshi, Kazushi Kawamura, Thiem Van Chu, Daichi Fujiki, Susumu Takeuchi, Masato Motomura
2024 J jnl
Pianissimo: A Sub-mW Class DNN Accelerator With Progressively Adjustable Bit-Precision.
IEEE Access
Junnosuke Suzuki, Jaehoon Yu, Mari Yasunaga, Ángel López García-Arias, Yasuyuki Okoshi, Shungo Kumazawa, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
2024 — conf
Progressive Variable Precision DNN With Bitwise Ternary Accumulation.
AICAS
Junnosuke Suzuki, Mari Yasunaga, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
2024 J jnl
Restricted Random Pruning at Initialization for High Compression Range.
Trans. Mach. Learn. Res.
Hikari Otsuka, Yasuyuki Okoshi, Ángel López García-Arias, Kazushi Kawamura, Thiem Van Chu, Daichi Fujiki, Masato Motomura
2024 B conf
Sparse-Sparse Matrix Multiplication Accelerator on FPGA featuring Distribute-Merge Product Dataflow.
ASPDAC
Yuta Nagahara, Jiale Yan, Kazushi Kawamura, Masato Motomura, Thiem Van Chu
2024 J jnl
Toward Improving Ensemble-Based Collaborative Inference at the Edge.
IEEE Access
Shungo Kumazawa, Jaehoon Yu, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
2024 — conf
WhiteDwarf: 12.24 TFLOPS/W 40 nm Versatile Neural Inference Engine for Ultra-Compact Execution of CNNs and MLPs Through Triple Unstructured Sparsity Exploitation and Triple Model Compression.
A-SSCC
Yasuyuki Okoshi, Ángel López García-Arias, Jaehoon Yu, Junnosuke Suzuki, Hikari Otsuka, Thiem Van Chu, Kazushi Kawamura, Daichi Fujiki, Masato Motomura
2023 J jnl
A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control for Various Combinatorial Optimization Problems.
IEICE Trans. Inf. Syst.
Daiki Okonogi, Satoru Jimbo, Kota Ando, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura
2023 — conf
A Highly Accurate and Parallel Vision MLP FPGA Accelerator based on FP7/8 SIMD Operations.
MCSoC
Mari Yasunaga, Junnosuke Suzuki, Masato Watanabe, Kazushi Kawamura, Thiem Van Chu, Jaehoon Yu, Masato Motomura
2023 — conf
Amorphica: 4-Replica 512 Fully Connected Spin 336MHz Metamorphic Annealer with Programmable Optimization Strategy and Compressed-Spin-Transfer Multi-Chip Extension.
ISSCC
Kazushi Kawamura, Jaehoon Yu, Daiki Okonogi, Satoru Jimbo, Genta Inoue, Akira Hyodo, Ángel López García-Arias, Kota Ando, Bruno Hideki Fukushima-Kimura, Ryota Yasudo, Thiem Van Chu, Masato Motomura
2023 Misc conf
Decision Forest Training Accelerator Based on Binary Feature Decomposition.
FCCM
Thiem Van Chu, Yu Mizutani, Yuta Nagahara, Shungo Kumazawa, Kazushi Kawamura, Jaehoon Yu, Masato Motomura
2023 — conf
Flexibly Controllable Dynamic Cooling Methods for Solid-State Annealing Processors to Improve Combinatorial Optimization Performance.
COOL CHIPS
Genta Inoue, Daiki Okonogi, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura
2023 — conf
Multicoated and Folded Graph Neural Networks With Strong Lottery Tickets.
LoG
Jiale Yan, Hiroaki Ito, Ángel López García-Arias, Yasuyuki Okoshi, Hikari Otsuka, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
2023 J jnl
Multicoated and Folded Graph Neural Networks with Strong Lottery Tickets.
CoRR
Jiale Yan, Hiroaki Ito, Ángel López García-Arias, Yasuyuki Okoshi, Hikari Otsuka, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
2023 — conf
Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge.
VLSI Technology and Circuits
Junnosuke Suzuki, Jaehoon Yu, Mari Yasunaga, Ángel López García-Arias, Yasuyuki Okoshi, Shungo Kumazawa, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
2022 J jnl
A Hybrid Integer Encoding Method for Obtaining High-Quality Solutions of Quadratic Knapsack Problems on Solid-State Annealers.
IEICE Trans. Inf. Syst.
Satoru Jimbo, Daiki Okonogi, Kota Ando, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura
2022 — conf
APC-SCA: A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control.
IPDPS Workshops
Daiki Okonogi, Satoru Jimbo, Kota Ando, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura
2022 — conf
Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet.
ISSCC
Kazutoshi Hirose, Jaehoon Yu, Kota Ando, Yasuyuki Okoshi, Ángel López García-Arias, Junnosuke Suzuki, Thiem Van Chu, Kazushi Kawamura, Masato Motomura
2022 A* conf
Multicoated Supermasks Enhance Hidden Networks.
ICML
Yasuyuki Okoshi, Ángel López García-Arias, Kazutoshi Hirose, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu
2021 — conf
A High-Performance and Flexible FPGA Inference Accelerator for Decision Forests Based on Prior Feature Space Partitioning.
FPT
Thiem Van Chu, Ryuichi Kitajima, Kazushi Kawamura, Jaehoon Yu, Masato Motomura
2021 — conf
Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner.
HCS
Kota Ando, Jaehoon Yu, Kazutoshi Hirose, Hiroki Nakahara, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
2021 J jnl
ExtraFerns: Fully Parallel Ensemble Learning Technique with Random Projection and Non-Greedy yet Minimal Memory Access Training.
Int. J. Netw. Comput.
Shungo Kumazawa, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu
2021 J jnl
ProgressiveNN: Achieving Computational Scalability with Dynamic Bit-Precision Adjustment by MSB-first Accumulative Computation.
Int. J. Netw. Comput.
Junnosuke Suzuki, Tomohiro Kaneko, Kota Ando, Kazutoshi Hirose, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu
2021 J jnl
STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin-Spin Interactions.
IEEE J. Solid State Circuits
Kasho Yamamoto, Kazushi Kawamura, Kota Ando, Normann Mertig, Takashi Takemoto, Masanao Yamaoka, Hiroshi Teramoto, Akira Sakai, Shinya Takamaeda-Yamazaki, Masato Motomura
2021 J jnl
Solving Constrained Slot Placement Problems Using an Ising Machine and Its Evaluations.
IEICE Trans. Inf. Syst.
Sho Kanamaru, Kazushi Kawamura, Shu Tanaka, Yoshinori Tomita, Nozomu Togawa
2020 — conf
ExtraFerns: Fully Parallel Ensemble Learning Technique with Non-Greedy yet Minimal Memory Access Training.
CANDAR
Shungo Kumazawa, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu
2020 — conf
FPGA-based Heterogeneous Solver for Three-Dimensional Routing.
ASP-DAC
Kento Hasegawa, Ryota Ishikawa, Makoto Nishizawa, Kazushi Kawamura, Masashi Tawada, Nozomu Togawa
2020 — conf
ProgressiveNN: Achieving Computational Scalability without Network Alteration by MSB-first Accumulative Computation.
CANDAR
Junnosuke Suzuki, Kota Ando, Kazutoshi Hirose, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu
2019 J jnl
An FPGA Implementation Method based on Distributed-register Architectures.
IPSJ Trans. Syst. LSI Des. Methodol.
Koichi Fujiwara, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa
2019 — conf
Implementation of a ROS-Based Autonomous Vehicle on an FPGA Board.
FPT
Kento Hasegawa, Kazunari Takasaki, Makoto Nishizawa, Ryota Ishikawa, Kazushi Kawamura, Nozomu Togawa
2019 — conf
Mapping Constrained Slot-Placement Problems to Ising Models and its Evaluations by an Ising Machine.
ICCE-Berlin
Sho Kanamaru, Kazushi Kawamura, Shu Tanaka, Yoshinori Tomita, Hidetoshi Matsuoka, Kaoru Kawamura, Nozomu Togawa
2018 — conf
A loop structure optimization targeting high-level synthesis of fast number theoretic transform.
ISQED
Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa
2017 — conf
A selector-based FFT processor and its FPGA implementation.
ISOCC
Yuya Hirai, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa
2017 J jnl
Efficient Multiplexer Networks for Field-Data Extractors and Their Evaluations.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Koki Ito, Kazushi Kawamura, Yutaka Tamiya, Masao Yanagisawa, Nozomu Togawa
2016 — conf
A high-performance circuit design algorithm using data dependent approximation.
ISOCC
Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa
2016 J jnl
Bi-Partitioning Based Multiplexer Network for Field-Data Extractors.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Koki Ito, Kazushi Kawamura, Yutaka Tamiya, Masao Yanagisawa, Nozomu Togawa
2016 J jnl
Interconnection-Delay and Clock-Skew Estimate Modelings for Floorplan-Driven High-Level Synthesis Targeting FPGA Designs.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Koichi Fujiwara, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa
2016 — conf
Rotator-based multiplexer network synthesis for field-data extractors.
SoCC
Koki Ito, Kazushi Kawamura, Yutaka Tamiya, Masao Yanagisawa, Nozomu Togawa
2015 J jnl
A Floorplan-Driven High-Level Synthesis Algorithm for Multiplexer Reduction Targeting FPGA Designs.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Koichi Fujiwara, Kazushi Kawamura, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa
2015 — conf
An H∞ controller design based on the butterworth filter conversion.
ASCC
Kazushi Kawamura, Hiroki Shibasaki, Rubiyah Yusof, Yoshihisa Ishida
2015 — conf
Clock skew estimate modeling for FPGA high-level synthesis and its application.
ASICON
Koichi Fujiwara, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa
2014 — conf
A floorplan-aware high-level synthesis algorithm for multiplexer reduction targeting FPGA designs.
APCCAS
Koichi Fujiwara, Shin-ya Abe, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa
2013 J jnl
A Thermal-Aware High-Level Synthesis Algorithm for RDR Architectures through Binding and Allocation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa
2013 C conf
A partial redundant fault-secure high-level synthesis algorithm for RDR architectures.
ISCAS
Kazushi Kawamura, Sho Tanaka, Masao Yanagisawa, Nozomu Togawa