Kazuo Taki

40 papers A* 2A 1B 4Journal 13Unranked 20
YearRankTypeTitle / Venue / Authors
2007 J jnl
A Mixed Circuit and System Level Simulation Technique of Collision-Resistant RFID System.
IEICE Trans. Electron.
Yohei Fukumizu, Naoki Gochi, Makoto Nagata, Kazuo Taki
2007 J jnl
Asymmetric Slope Dual Mode Differential Logic Circuit for Compatibility of Low-Power and High-Speed Operations.
IEICE Trans. Electron.
Masao Morimoto, Makoto Nagata, Kazuo Taki
2006 — conf
A built-in power supply noise probe for digital LSIs.
ASP-DAC
Mitsuya Fukazawa, Koichiro Noguchi, Makoto Nagata, Kazuo Taki
2006 J jnl
Back-End Design of a Collision-Resistive RFID System through High-Level Modeling Approach.
IEICE Trans. Electron.
Yohei Fukumizu, Makoto Nagata, Kazuo Taki
2006 J jnl
Communication Scheme for a Highly Collision-Resistive RFID System.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yohei Fukumizu, Shuji Ohno, Makoto Nagata, Kazuo Taki
2005 J jnl
A built-in technique for probing power supply and ground noise distribution within large-scale digital integrated circuits.
IEEE J. Solid State Circuits
Makoto Nagata, Takeshi Okumoto, Kazuo Taki
2005 J jnl
High-Speed Digital Circuit Design Using Differential Logic with Asymmetric Signal Transition.
IEICE Trans. Electron.
Masao Morimoto, Makoto Nagata, Kazuo Taki
2005 J jnl
Logic Synthesis Technique for High Speed Differential Dynamic Logic with Asymmetric Slope Transition.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Masao Morimoto, Yoshinori Tanaka, Makoto Nagata, Kazuo Taki
2003 J jnl
A GUI software development system for digital AV applications.
Syst. Comput. Jpn.
Shuusuke Haruna, Norio Sanada, Hisayuki Kinoh, Kazutoshi Sumiya, Kazuo Taki
2002 — conf
An ultra low power, realtime MPEG2 MP@HL motion estimation processor core with SIMD datapath architecture optimized for gradient descent search algorithm.
CICC
Masayuki Miyama, Osamu Tooyama, N. Takamatsu, T. Kodake, K. Nakamura, A. Kato, Junichi Miyakoshi, K. Hashimoto, Shigenobu Komatsu, M. Yagi, Masao Morimoto, Kazuo Taki, Masahiko Yoshimoto
2000 — conf
A 16-bit redundant binary multiplier using low-power pass-transistor logic SPL.
ASP-DAC
Hirofumi Sakamoto, Ken'ichiro Uda, Bu-Yeol Lee, Hiroyuki Ochi, Kazuo Taki, Takao Tsuda
1999 J jnl
Test generation for stuck-on faults in pass-transistor logic SPL and implementation of DFT circuits.
Syst. Comput. Jpn.
Tsuyoshi Shinogi, Terumine Hayashi, Kazuo Taki
1998 — conf
A Survey for Pass-Transistor Logic Technologies - Recent Researches and Developments and Future Prospects (Embedded Tutorial).
ASP-DAC
Kazuo Taki
1998 — conf
Eliminating Bottlenecks on Parallel Systems using Adaptive Objects.
IEEE PACT
Masahiro Yasugi, Shegeyuki Eguchi, Kazuo Taki
1997 — conf
Super low power 8-bit CPU with pass-transistor logic.
ASP-DAC
Kazuo Taki, Bu-Yeol Lee, Hideki Tanaka, Kenzo Konishi
1997 — conf
Test Generation for Stuck-On Faults in BDD-Based Pass-Transistor Logic SPL.
Asian Test Symposium
Tsuyoshi Shinogi, Terumine Hayashi, Kazuo Taki
1994 J jnl
Parallel processing on the multi-PSI computer and its evaluation - a programming paradigm based on a small-grain highly concurrent object model.
Syst. Comput. Jpn.
Kazuo Taki, Nobuyuki Ichiyoshi
1992 — conf
Experimental Parallel Inference Software.
FGCS
Katsumi Nitta, Kazuo Taki, Nobuyuki Ichiyoshi
1992 — conf
LSI-CAD Programs on Parallel Inference Machine.
FGCS
Hiroshi Date, Yukinori Matsumoto, Kouichi Kimura, Kazuo Taki, Hiroo Kato, Masahiro Hoshi
1992 — conf
Parallel Inference Machine PIM.
FGCS
Kazuo Taki
1992 — conf
Parallel Logic Simulator based on Time Warp and its Evaluation.
FGCS
Yukinori Matsumoto, Kazuo Taki
1992 — conf
Parallel and Distributed Implementation of Concurrent Logic Programming Language KL1.
FGCS
Keiji Hirata, Reki Yamamoto, Akira Imai, Hideo Kawai, Kiyoshi Hirano, Tsuneyoshi Takagi, Kazuo Taki, Akihiko Nakase, Kazuaki Rokusawa
1992 — conf
Towards the General-Purpose Parallel Processing System, Panel Position Paper.
FGCS
Kazuo Taki
1991 B conf
Parallel Programming and Large-scale Applications in the FGCS Project.
ICLP
Kazuo Taki
1990 B conf
A Multi-Level Load Balancing Scheme for OR-Parallel Exhaustive Search Programs on the Multi-PSI.
PPoPP
Masakazu Furuichi, Kazuo Taki, Nobuyuki Ichiyoshi
1990 J jnl
A load balancing mechanism for large scale multiprocessor systems and its implementation.
New Gener. Comput.
Yasutaka Takeda, Hiroshi Nakashima, Kanae Masuda, Takashi Chikayama, Kazuo Taki
1989 — conf
The FGCS Computing Architecture.
IFIP Congress
Kazuo Taki
1988 — conf
A Load Balancing Mechanism for Large Scale Multiprocessor Systems and its Implementation.
FGCS
Yasutaka Takeda, Hiroshi Nakashima, Kanae Masuda, Takashi Chikayama, Kazuo Taki
1988 — conf
Overview of the Parallel Inference Machine Architecture (PIM).
FGCS
Atsuhiro Goto, Masatoshi Sato, Katsuto Nakajima, Kazuo Taki, Akira Matsumoto
1988 A conf
Preliminary Evaluation of the Connection Network for the Multi-PSI System.
ECAI
Kanae Masuda, Hirokazu Ishizuka, Hiroaki Iwayama, Kazuo Taki, Eiji Sugino
1988 — conf
Research and Development of the Parallel Inference System in the Intermediate Stage of the FGCS Project.
FGCS
Shunichi Uchida, Kazuo Taki, Katsuto Nakajima, Atsuhiro Goto, Takashi Chikayama
1987 B conf
A Distributed Implementation of Flat GHC on the Multi-PSI.
ICLP
M. Ichiyoshi, T. Miyazaki, Kazuo Taki
1987 A* conf
Performance and Architectural Evaluation of the PSI Machine.
ASPLOS
Kazuo Taki, Katsuto Nakajima, Hiroshi Nakashima, Morihiro Ikeda
1986 — conf
Evaluation of PSI Micro-Interpreter.
COMPCON
Katsuto Nakajima, Hiroshi Nakashima, Minoru Yokota, Kazuo Taki, Shunichi Uchida, Hiroshi Nishikawa, Akira Yamamoto, Masaki Mitsui
1984 — conf
A Microprogrammed Interpreter for the Personal Sequential Inference Machine.
FGCS
Minoru Yokota, Akira Yamamoto, Kazuo Taki, Hiroshi Nishikawa, Shunichi Uchida, Katsuto Nakajima, Masaki Mitsui
1984 — conf
Hardware Design and Implementation of the Personal Sequential Inference Machine (PSI).
FGCS
Kazuo Taki, Minoru Yokota, Akira Yamamoto, Hiroshi Nishikawa, Shunichi Uchida, Hiroshi Nakashima, Akitoshi Mitsuishi
1983 J jnl
Outline of the Personal Sequential Inference Machine: PSI.
New Gener. Comput.
Shunichi Uchida, Minoru Yokota, Akira Yamamoto, Kazuo Taki, Hiroshi Nishikawa
1983 J jnl
The Design and Implementation of a Personal Sequential Inference Machine: PSI.
New Gener. Comput.
Minoru Yokota, Akira Yamamoto, Kazuo Taki, Hiroshi Nishikawa, Shunichi Uchida
1983 B conf
The Personal Sequential Inference Machine (PSI): Its Design and Machine Architecture.
Logic Programming Workshop
Hiroshi Nishikawa, Minoru Yokota, Akira Yamamoto, Kazuo Taki, Shunichi Uchida
1979 A* conf
The Experimental LISP Machine.
IJCAI
Kazuo Taki, Yukio Kaneda, Sadao Maekawa