Kazumi Hatayama

56 papers A 13B 1C 2Misc 11Journal 11Unranked 18

Year	Rank	Type	Title / Venue / Authors
2023	—	`conf`	A Physically Unclonable Function Using Time-to-Digital Converter with Linearity Self-Calibration and its FPGA Implementation. ITC-Asia Kentaroh Katoh, Shuhei Yamamoto, Zheming Zhao, Yujie Zhao, Shogo Katayama, Anna Kuwana, Takayuki Nakatani, Kazumi Hatayama, Haruo Kobayashi, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa
2023	A	`conf`	Low Distortion Sinusoidal Signal Generator with Harmonics Cancellation Using Two Types of Digital Predistortion. ITC Keno Sato, Takayuki Nakatani, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Shogo Katayama, Daisuke Iimori, Misaki Takagi, Yujie Zhao, Shuhei Yamamoto, Anna Kuwana, Kentaroh Katoh, Kazumi Hatayama, Haruo Kobayashi
2023	J	`jnl`	Low distortion sine wave generator with simple harmonics cancellation circuit and filter for analog device testing. IEICE Electron. Express Shogo Katayama, Takayuki Nakatani, Daisuke Iimori, Misaki Takagi, Yujie Zhao, Anna Kuwana, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Kentaroh Katoh, Kazumi Hatayama, Haruo Kobayashi
2022	—	`conf`	High Precision Voltage Measurement System Utilizing Low-End ATE Resource and BOST. ATS Keno Sato, Takayuki Nakatani, Shogo Katayama, Daisuke Iimori, Gaku Ogihara, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Yujie Zhao, Kentaroh Katoh, Anna Kuwana, Kazumi Hatayama, Haruo Kobayashi
2022	Misc	`conf`	Innovative Practices Track: Innovative Analog Circuit Testing Technologies. VTS Chris Mangelsdorf, Manasa Madhvaraj, Salvador Mir, Manuel J. Barragán, Daisuke Iimori, Takayuki Nakatani, Shogo Katayama, Gaku Ogihara, Yujie Zhao, Jianglin Wei, Anna Kuwana, Kentaroh Katoh, Kazumi Hatayama, Haruo Kobayashi, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa
2022	J	`jnl`	Revisit to Histogram Method for ADC Linearity Test: Examination of Input Signal and Ratio of Input and Sampling Frequencies. J. Electron. Test. Yujie Zhao, Kentaroh Katoh, Anna Kuwana, Shogo Katayama, Jianglin Wei, Haruo Kobayashi, Takayuki Nakatani, Kazumi Hatayama, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa
2021	—	`conf`	Evaluation of High-Precision Nano-Ampere Current Measurement Method for Mass Production. ICECS Gaku Ogihara, Takayuki Nakatani, Daisuke Iimori, Shogo Katayama, Anna Kuwana, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Yujie Zhao, Jianglin Wei, Kazumi Hatayama, Haruo Kobayashi
2021	—	`conf`	High Precision Measurement of Sub-Nano Ampere Current in ATE Environment. ATS Keno Sato, Takayuki Nakatani, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Shogo Katayama, Gaku Ogihara, Daisuke Iimori, Yujie Zhao, Jianglin Wei, Anna Kuwana, Kazumi Hatayama, Haruo Kobayashi
2021	C	`conf`	Metallic Ratio Equivalent-Time Sampling: A Highly Efficient Waveform Acquisition Method. IOLTS Shuhei Yamamoto, Yuto Sasaki, Yujie Zhao, Jianglin Wei, Anna Kuwana, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Takayuki Nakatani, Minh Tri Tran, Shogo Katayama, Kazumi Hatayama, Haruo Kobayashi
2021	A	`conf`	Revisit to Accurate ADC Testing with Incoherent Sampling Using Proper Sinusoidal Signal and Sampling Frequencies. ITC Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Jianglin Wei, Takayuki Nakatani, Yujie Zhao, Shogo Katayama, Shuhei Yamamoto, Anna Kuwana, Kazumi Hatayama, Haruo Kobayashi
2021	A	`conf`	Summing Node and False Summing Node Methods: Accurate Operational Amplifier AC Characteristics Testing without Audio Analyzer. ITC Daisuke Iimori, Takayuki Nakatani, Shogo Katayama, Gaku Ogihara, Akemi Hatta, Anna Kuwana, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Jianglin Wei, Yujie Zhao, Minh Tri Tran, Kazumi Hatayama, Haruo Kobayashi
2020	—	`conf`	Accurate Testing of Precision Voltage Reference by DC-AC Conversion. ATS Keno Sato, Takayuki Nakatani, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Anna Kuwana, Kazumi Hatayama, Haruo Kobayashi
2020	Misc	`conf`	Innovative Test Practices in Asia. VTS Takeshi Iwasaki, Masao Aso, Haruji Futami, Satoshi Matsunaga, Yousuke Miyake, Takaaki Kato, Seiji Kajihara, Yukiya Miura, Smith Lai, Gavin Hung, Harry H. Chen, Haruo Kobayashi, Kazumi Hatayama
2020	—	`conf`	Summing Node Test Method: Simultaneous Multiple AC Characteristics Testing of Multiple Operational Amplifiers. ATS Gaku Ogihara, Takayuki Nakatani, Akemi Hatta, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Anna Kuwana, Riho Aoki, Shogo Katayama, Jianglin Wei, Yujie Zhao, Jianlong Wang, Kazumi Hatayama, Haruo Kobayashi
2019	—	`conf`	Accurate and Fast Testing Technique of Operational Amplifier DC Offset Voltage in µV-Order by DC-AC Conversion. ITC-Asia Yuto Sasaki, Kosuke Machida, Riho Aoki, Shogo Katayama, Takayuki Nakatani, Jianlong Wang, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Anna Kuwana, Kazumi Hatayama, Haruo Kobayashi
2019	—	`conf`	Evaluation of Null Method for Operational Amplifier Short-Time Testing. ASICON Riho Aoki, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Shogo Katayama, Yuto Sasaki, Kosuke Machida, Takayuki Nakatani, Jianlong Wang, Anna Kuwana, Kazumi Hatayama, Haruo Kobayashi
2019	—	`conf`	High-Resolution Low-Sampling-Rate Δ∑ ADC Linearity Short-Time Testing Algorithm. ASICON Jiang-Lin Wei, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Nene Kushita, Takahiro Arai, Lei Sha, Anna Kuwana, Haruo Kobayashi, Takayuki Nakatani, Kazumi Hatayama, Keno Sato
2019	Misc	`conf`	Innovative Test Practices in Japan. VTS Yusuke Asada, Takahiko Shimizu, Yuji Gendai, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Jiang-Lin Wei, Nene Kushita, Hirotaka Arai, Anna Kuwana, Takayuki Nakatani, Kazumi Hatayama, Haruo Kobayashi
2018	Misc	`conf`	Innovative practices on test in Japan. VTS Koji Asami, Yoshiro Tamura, Haruo Kobayashi, Jun Matsushima, Yoichi Maeda, Kazumi Hatayama
2017	Misc	`conf`	Innovative practices session 10B innovative practices in Asia-2: From cost perspective. VTS Kazumi Hatayama, Masahiro Ishida
2017	Misc	`conf`	Innovative practices session 9B innovative practices in Asia-1: From quality perspective. VTS Kazumi Hatayama, Masahiro Ishida
2016	J	`jnl`	Path Clustering for Test Pattern Reduction of Variation-Aware Adaptive Path Delay Testing. J. Electron. Test. Michihiro Shintani, Takumi Uezono, Kazumi Hatayama, Kazuya Masu, Takashi Sato
2014	J	`jnl`	A Variability-Aware Adaptive Test Flow for Test Quality Improvement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Michihiro Shintani, Takumi Uezono, Tomoyuki Takahashi, Kazumi Hatayama, Takashi Aikyo, Kazuya Masu, Takashi Sato
2014	A	`conf`	Memory block based scan-BIST architecture for application-dependent FPGA testing. FPGA Keita Ito, Tomokazu Yoneda, Yuta Yamato, Kazumi Hatayama, Michiko Inoue
2014	—	`conf`	Parallel Path Delay Fault Simulation for Multi/Many-Core Processors with SIMD Units. ATS Yussuf Ali, Yuta Yamato, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue
2013	Misc	`conf`	Special session 4B: Elevator talks. VTS Jennifer Dworak, Ronald Shawn Blanton, Masahiro Fujita, Kazumi Hatayama, Naghmeh Karimi, Michail Maniatakos, Antonis M. Paschalis, Adit D. Singh, Tian Xia
2012	A	`conf`	A fast and accurate per-cell dynamic IR-drop estimation method for at-speed scan test pattern validation. ITC Yuta Yamato, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue
2012	A	`conf`	DART: Dependable VLSI test architecture and its implementation. ITC Yasuo Sato, Seiji Kajihara, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue, Yukiya Miura, Satosni Untake, Takumi Hasegawa, Motoyuki Sato, Kotaro Shimamura
2011	J	`jnl`	Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing. IEICE Trans. Inf. Syst. Kohei Miyase, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara
2010	J	`jnl`	A Study of Capture-Safe Test Generation Flow for At-Speed Testing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Atsushi Takashima, Hiroshi Furukawa, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Kewal K. Saluja
2010	J	`jnl`	Foreword. IEICE Trans. Inf. Syst. Kazumi Hatayama, Tsuyoshi Shinogi
2010	Misc	`conf`	Path clustering for adaptive test. VTS Takumi Uezono, Tomoyuki Takahashi, Michihiro Shintani, Kazumi Hatayama, Kazuya Masu, Hiroyuki Ochi, Takashi Sato
2010	C	`conf`	Scan based process parameter estimation through path-delay inequalities. ISCAS Takumi Uezono, Tomoyuki Takahashi, Michihiro Shintani, Kazumi Hatayama, Kazuya Masu, Hiroyuki Ochi, Takashi Sato
2009	A	`conf`	A novel post-ATPG IR-drop reduction scheme for at-speed scan testing in broadcast-scan-based test compression environment. ICCAD Kohei Miyase, Yuta Yamato, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Xiaoqing Wen, Seiji Kajihara
2009	—	`conf`	An Adaptive Test for Parametric Faults Based on Statistical Timing Information. Asian Test Symposium Michihiro Shintani, Takumi Uezono, Tomoyuki Takahashi, Hiroyuki Ueyama, Takashi Sato, Kazumi Hatayama, Takashi Aikyo, Kazuya Masu
2009	Misc	`conf`	Small Delay Fault Model for Intra-Gate Resistive Open Defects. VTS Masayuki Arai, Akifumi Suto, Kazuhiko Iwasaki, Katsuyuki Nakano, Michihiro Shintani, Kazumi Hatayama, Takashi Aikyo
2008	B	`conf`	A Capture-Safe Test Generation Scheme for At-Speed Scan Testing. ETS Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Hiroshi Furukawa, Yuta Yamato, Atsushi Takashima, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Kewal K. Saluja
2008	A	`conf`	Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification. ICCAD Kohei Miyase, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara
2008	J	`jnl`	Estimation of Delay Test Quality and Its Application to Test Generation. Inf. Media Technol. Seiji Kajihara, Shohei Morishima, Masahiro Yamamoto, Xiaoqing Wen, Masayasu Fukunaga, Kazumi Hatayama, Takashi Aikyo
2008	J	`jnl`	Estimation of Delay Test Quality and Its Application to Test Generation. IPSJ Trans. Syst. LSI Des. Methodol. Seiji Kajihara, Shohei Morishima, Masahiro Yamamoto, Xiaoqing Wen, Masayasu Fukunaga, Kazumi Hatayama, Takashi Aikyo
2007	A	`conf`	Estimation of delay test quality and its application to test generation. ICCAD Seiji Kajihara, Shohei Morishima, Masahiro Yamamoto, Xiaoqing Wen, Masayasu Fukunaga, Kazumi Hatayama, Takashi Aikyo
2006	Misc	`conf`	Session Abstract. VTS Kazumi Hatayama
2004	—	`conf`	Opportunities with the open architecture test system. ASP-DAC Kazumi Hatayama, Rochit Rajsuman
2003	J	`jnl`	DFT Timing Design Methodology for Logic BIST. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yasuo Sato, Motoyuki Sato, Koki Tsutsumida, Kazumi Hatayama, Kazuyuki Nomoto
2003	—	`conf`	DFT timing design methodology for at-speed BIST. ASP-DAC Yasuo Sato, Motoyuki Sato, Koki Tsutsumida, Masatoshi Kawashima, Kazumi Hatayama, Kazuyuki Nomoto
2002	A	`conf`	Application of High-Quality Built-In Test to Industrial Designs. ITC Kazumi Hatayama, Michinobu Nakao, Yoshikazu Kiyoshige, Koichiro Natsume, Yasuo Sato, Takaharu Nagumo
2002	—	`conf`	At-Speed Built-in Test for Logic Circuits with Multiple Clocks. Asian Test Symposium Kazumi Hatayama, Michinobu Nakao, Yasuo Sato
2001	—	`conf`	Test Generation for Multiple-Threshold Gate-Delay Fault Model. Asian Test Symposium Michinobu Nakao, Yoshikazu Kiyoshige, Kazumi Hatayama, Yasuo Sato, Takaharu Nagumo
1999	A	`conf`	Low overhead test point insertion for scan-based BIST. ITC Michinobu Nakao, Seiji Kobayashi, Kazumi Hatayama, Kazuhiko Iijima, Seiji Terada
1997	Misc	`conf`	A practical approach to instruction-based test generation for functional modules of VLSI processors. VTS Kazumi Hatayama, Kazunori Hikone, Takeshi Miyazaki, Hiromichi Yamada
1997	—	`conf`	Accelerated Test Points Selection Method for Scan-Based BIST. Asian Test Symposium Michinobu Nakao, Kazumi Hatayama, Isao Higashi
1997	—	`conf`	Application of a Design for Delay Testability Approach to High Speed Logic LSIs. Asian Test Symposium Kazumi Hatayama, Mitsuji Ikeda, Masahiro Takakura, Satoshi Uchiyama, Yoriyuki Sakamoto
1995	—	`conf`	A parallel sequential test generation system DESCARTES based on real-valued logic simulation. Asian Test Symposium Hiroshi Date, Michinobu Nakao, Kazumi Hatayama
1993	J	`jnl`	Sequential circuit test generation by real number simulation. Syst. Comput. Jpn. Kazunori Hikone, Mitsuji Ikeda, Kazumi Hatayama, Terumine Hayashi
1992	A	`conf`	Sequential Test Generation Based on Real-Value Logic. ITC Kazumi Hatayama, Kazunori Hikone, Mitsuji Ikeda, Terumine Hayashi
1989	A	`conf`	Enhanced Delay Test Generator for High-Speed Logic LSIs. ITC Kazumi Hatayama, Mitsuji Ikeda, Terumine Hayashi, Masahiro Takakura, Kuniaki Kishida, Shun Ishiyama