Kazuki Inoue - RankMe

16 papers A 1B 3C 2Journal 6Unranked 4

Year	Rank	Type	Title / Venue / Authors
2018	—	`conf`	Understanding Fake Faces. ECCV Workshops (3) Ryota Natsume, Kazuki Inoue, Yoshihiro Fukuhara, Shintaro Yamamoto, Shigeo Morishima, Hirokatsu Kataoka
2018	J	`jnl`	Understanding Fake Faces. CoRR Ryota Natsume, Kazuki Inoue, Yoshihiro Fukuhara, Shintaro Yamamoto, Shigeo Morishima, Hirokatsu Kataoka
2017	J	`jnl`	Physical Fault Detection and Recovery Methods for System-LSI Loaded FPGA-IP Core. IEICE Trans. Inf. Syst. Motoki Amagasaki, Yuki Nishitani, Kazuki Inoue, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2013	A	`conf`	A novel FPGA design framework with VLSI post-routing performance analysis (abstract only). FPGA Qian Zhao, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2013	B	`conf`	Defect-robust FPGA architectures for intellectual property cores in system LSI. FPL Motoki Amagasaki, Kazuki Inoue, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2013	J	`jnl`	FPGA Design Framework Combined with Commercial VLSI CAD. IEICE Trans. Inf. Syst. Qian Zhao, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2012	—	`conf`	A novel physical defects recovery technique for FPGA-IP cores. ReConFig Yuki Nishitani, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2012	J	`jnl`	An Easily Testable Routing Architecture and Prototype Chip. IEICE Trans. Inf. Syst. Kazuki Inoue, Masahiro Koga, Motoki Amagasaki, Masahiro Iida, Yoshinobu Ichida, Mitsuro Saji, Jun Iida, Toshinori Sueyoshi
2012	C	`conf`	Evaluation of fault tolerant technique based on homogeneous FPGA architecture. VLSI-SoC Yuki Nishitani, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2012	B	`conf`	Fault detection and avoidance of FPGA in various granularities. FPL Kazuki Inoue, Yuki Nishitani, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi
2011	J	`jnl`	A Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells. IEICE Trans. Electron. Masahiro Iida, Masahiro Koga, Kazuki Inoue, Motoki Amagasaki, Yoshinobu Ichida, Mitsuro Saji, Jun Iida, Toshinori Sueyoshi
2011	B	`conf`	An Easily Testable Routing Architecture and Efficient Test Technique. FPL Kazuki Inoue, Hiroki Yosho, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi
2011	C	`conf`	An easily testable routing architecture of FPGA. VLSI-SoC Masahiro Iida, Kazuki Inoue, Motoki Amagasaki, Toshinori Sueyoshi
2011	—	`conf`	Evaluation of human distress by one's walking speed - toward development of early warning system for marine pilots' condition. SoSE Masahiro Toba, Yuji Hayashi, Koji Murai, Kazuki Inoue
2010	J	`jnl`	A Variable-Grain Logic Cell and Routing Architecture for a Reconfigurable IP Core. ACM Trans. Reconfigurable Technol. Syst. Kazuki Inoue, Qian Zhao, Yasuhiro Okamoto, Hiroki Yosho, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi
2009	—	`conf`	A Novel Local Interconnect Architecture for Variable Grain Logic Cell. ARC Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi