Kazuhiko Kajigaya

12 papers Journal 10Unranked 2

Year	Rank	Type	Title / Venue / Authors
2007	—	`conf`	DRAM and eRAM. ISSCC Martin Brox, Kazuhiko Kajigaya
2007	J	`jnl`	Long-Retention-Time, High-Speed DRAM Array with 12- IEICE Trans. Electron. Riichiro Takemura, Kiyoo Itoh, Tomonori Sekiguchi, Satoru Akiyama, Satoru Hanzawa, Kazuhiko Kajigaya, Takayuki Kawahara
2006	J	`jnl`	Concordant memory design: an integrated statistical design approach for multi-gigabit DRAM. IEEE J. Solid State Circuits Satoru Akiyama, Tomonori Sekiguchi, Kazuhiko Kajigaya, Satoru Hanzawa, Riichiro Takemura, Takayuki Kawahara
2005	J	`jnl`	A large-scale and low-power CAM architecture featuring a one-hot-spot block code for IP-address lookup in a network router. IEEE J. Solid State Circuits Satoru Hanzawa, Takeshi Sakata, Kazuhiko Kajigaya, Riichiro Takemura, Takayuki Kawahara
2005	—	`conf`	A ternary/quaternary CAM architecture with an NPU-side IP-address compression scheme and a dynamic re-configurable CODEC scheme for large-scale flow-table lookup. ICC Satoru Hanzawa, Takeshi Sakata, Kazuhiko Kajigaya, Riichiro Takemura, Tomonori Sekiguchi, Takayuki Kawahara
2002	J	`jnl`	A low-impedance open-bitline array for multigigabit DRAM. IEEE J. Solid State Circuits Tomonori Sekiguchi, Kiyoo Itoh, Tsugio Takahashi, Masahiro Sugaya, Hiroki Fujisawa, Masayuki Nakamura, Kazuhiko Kajigaya, Katsutaka Kimura
2001	J	`jnl`	A dual-phase-controlled dynamic latched amplifier for high-speed and low-power DRAMs. IEEE J. Solid State Circuits Hiroki Fujisawa, Tsugio Takahashi, Masayuki Nakamura, Kazuhiko Kajigaya
2001	J	`jnl`	A multigigabit DRAM technology with 6F IEEE J. Solid State Circuits Tsugio Takahashi, Tomonori Sekiguchi, Riichiro Takemura, Seiji Narui, Hiroki Fujisawa, Shinichi Miyatake, Makoto Morino, Koji Arai, Satoru Yamada, Shoji Shukuri, Masayuki Nakamura, Yoshitaka Tadaki, Kazuhiko Kajigaya, Katsutaka Kimura, Kiyoo Itoh
1997	J	`jnl`	The charge-share modified (CSM) precharge-level architecture for high-speed and low-power ferroelectric memory. IEEE J. Solid State Circuits Hiroki Fujisawa, Takeshi Sakata, Tomonori Sekiguchi, Osamu Nagashima, Katsutaka Kimura, Kazuhiko Kajigaya
1996	J	`jnl`	A 29-ns 64-Mb DRAM with hierarchical array architecture. IEEE J. Solid State Circuits Masayuki Nakamura, Tugio Takahashi, Takesada Akiba, Goro Kitsukawa, Makoto Morino, Toshihiro Sekiguchi, Isamu Asano, Katsuo Komatsuzaki, Yoshitaka Tadaki, Songsu Cho, Kazuhiko Kajigaya, Tadashi Tachibana, Katsuyuki Sato
1991	J	`jnl`	Dual-regulator dual-decoding-trimmer DRAM voltage limiter for burn-in test. IEEE J. Solid State Circuits Masashi Horiguchi, Masakazu Aoki, Jun Etoh, Gyoo Itoh, Kazuhiko Kajigaya, Atsushi Nozoe, Tetsuro Matsumoto
1990	J	`jnl`	A tunable CMOS-DRAM voltage limiter with stabilized feedback amplifier. IEEE J. Solid State Circuits Masashi Horiguchi, Masakazu Aoki, Jun Etoh, Hitoshi Tanaka, Shin'ichi Ikenaga, Kiyoo Itoh, Kazuhiko Kajigaya, Hiroaki Kotani, Kazuyoshi Ohshima, Tetsuro Matsumoto