Kazuhiko Iwasaki

65 papers A 8C 9Misc 5Journal 32Unranked 11

Year	Rank	Type	Title / Venue / Authors
2018	J	`jnl`	Layout-Aware Fast Bridge/Open Test Generation by 2-Step Pattern Reordering. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masayuki Arai, Shingo Inuyama, Kazuhiko Iwasaki
2017	A	`conf`	Layout-aware 2-step window-based pattern reordering for fast bridge/open test generation. ITC Masayuki Arai, Shingo Inuyama, Kazuhiko Iwasaki
2017	J	`jnl`	Reordering-Based Test Pattern Reduction Considering Critical Area-Aware Weighted Fault Coverage. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masayuki Arai, Kazuhiko Iwasaki
2016	—	`conf`	Critical-Area-Aware Test Pattern Generation and Reordering. ATS Shingo Inuyama, Masayuki Arai, Kazuhiko Iwasaki
2015	—	`conf`	Note on Fast Bridge Fault Test Generation Based on Critical Area. ICA3PP (3) Masayuki Arai, Shingo Inuyama, Kazuhiko Iwasaki
2013	J	`jnl`	Checkpoint Time Arrangement Rotation in Hybrid State Saving with a Limited Number of Periodical Checkpoints. IEICE Trans. Inf. Syst. Ryo Suzuki, Mamoru Ohara, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki
2013	C	`conf`	Classification of DNS Queries for Anomaly Detection. PRDC Hongbo Shi, Kazuhiko Iwasaki
2012	—	`conf`	Note on Layout-Aware Weighted Probabilistic Bridge Fault Coverage. Asian Test Symposium Masayuki Arai, Yoshihiro Shimizu, Kazuhiko Iwasaki
2011	C	`conf`	Area-Per-Yield and Defect Level of Cascaded TMR for Pipelined Processors. PRDC Masayuki Arai, Kazuhiko Iwasaki
2010	C	`conf`	A Distributed Data Replication Protocol for File Versioning with Optimal Node Assignments. PRDC Takahiko Ikeda, Mamoru Ohara, Satoshi Fukumoto, Masayuki Arai, Kazuhiko Iwasaki
2010	J	`jnl`	Reduction of Area per Good Die for SoC Memory Built-In Self-Test. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masayuki Arai, Tatsuro Endo, Kazuhiko Iwasaki, Michinobu Nakao, Iwao Suzuki
2010	J	`jnl`	Reduction of Test Data Volume and Improvement of Diagnosability Using Hybrid Compression. IEICE Trans. Inf. Syst. Anis Uzzaman, Brion L. Keller, Brian Foutz, Sandeep Bhatia, Thomas Bartenstein, Masayuki Arai, Kazuhiko Iwasaki
2009	J	`jnl`	Automatic Handling of Programmable On-Product Clock Generation (OPCG) Circuitry for Low Power Aware Delay Test. J. Low Power Electron. Anis Uzzaman, Brion L. Keller, Thomas J. Snethen, Kazuhiko Iwasaki, Masayuki Arai
2009	Misc	`conf`	Small Delay Fault Model for Intra-Gate Resistive Open Defects. VTS Masayuki Arai, Akifumi Suto, Kazuhiko Iwasaki, Katsuyuki Nakano, Michihiro Shintani, Kazumi Hatayama, Takashi Aikyo
2008	J	`jnl`	Analysis of Probabilistic Trapezoid Protocol for Data Replication. Inf. Media Technol. Tabito Suzuki, Mamoru Ohara, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki
2008	J	`jnl`	Analysis of Probabilistic Trapezoid Protocol for Data Replication. J. Inf. Process. Tabito Suzuki, Mamoru Ohara, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki
2008	A	`conf`	Hardware Overhead Reduction for Memory BIST. ITC Masayuki Arai, Kazuhiko Iwasaki, Michinobu Nakao, Iwao Suzuki
2008	J	`jnl`	Study on Expansion of Convolutional Compactors over Galois Field. IEICE Trans. Inf. Syst. Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki
2008	J	`jnl`	Study on Test Data Reduction Combining Illinois Scan and Bit Flipping. IEICE Trans. Inf. Syst. Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki
2008	J	`jnl`	Test Data Compression for Scan-Based BIST Aiming at 100x Compression Rate. IEICE Trans. Inf. Syst. Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, Tatsuru Matsuo, Takahisa Hiraide, Hideaki Konishi, Michiaki Emori, Takashi Aikyo
2008	J	`jnl`	Tester Structure Expression Language and Its Application to the Environment for VLSI Tester Program Development. J. Inf. Process. Syst. Masayuki Sato, Hiroki Wakamatsu, Masayuki Arai, Kenichi Ichino, Kazuhiko Iwasaki, Takeshi Asakawa
2006	J	`jnl`	Analytical Model on Hybrid State Saving with a Limited Number of Checkpoints and Bound Rollbacks. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Mamoru Ohara, Ryo Suzuki, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki
2006	—	`conf`	Expansion of Convolutional Compactors over Galois Field. ATS Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki
2006	J	`jnl`	Extension of coefficients for (n, k, m) convolutional-code-based packet loss recovery. Comput. Math. Appl. Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki
2006	A	`conf`	Test Data Compression of 100x for Scan-Based BIST. ITC Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, Tatsuru Matsuo, Takahisa Hiraide, Hideaki Konishi, Michiaki Emori, Takashi Aikyo
2005	A	`conf`	Analysis of Probabilistic Trapezoid Protocol for Data Replication. DSN Tabito Suzuki, Mamoru Ohara, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki
2005	A	`conf`	Analysis of error-masking and X-masking probabilities for convolutional compactors. ITC Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki
2005	J	`jnl`	Reliability Analysis of a Convolutional-Code-Based Packet Level FEC under Limited Buffer Size. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki
2004	C	`conf`	Analysis of Read and Write Availability for Generalized Hybrid Data Replication Protocol. PRDC Masayuki Arai, Tabito Suzuki, Mamoru Ohara, Satoshi Fukumoto, Kazuhiko Iwasaki, Hee Yong Youn
2004	J	`jnl`	Application of Partially Rotational Scan Technique with Tester IP for Processor Circuits. IEICE Trans. Inf. Syst. Kenichi Ichino, Ko-ichi Watanabe, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki
2004	—	`conf`	Finding a Recovery Line in Uncoordinated Checkpointing. ICDCS Workshops Mamoru Ohara, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki
2004	—	`conf`	Seed Selection Procedure for LFSR-Based BIST with Multiple Scan Chains and Phase Shifters. Asian Test Symposium Masayuki Arai, Harunobu Kurokawa, Kenichi Ichino, Satoshi Fukumoto, Kazuhiko Iwasaki
2004	J	`jnl`	Technique to Diagnose Open Defects that Takes Coupling Effects into Consideration. IEICE Trans. Inf. Syst. Yasuo Sato, Iwao Yamazaki, Hiroki Yamanaka, Toshio Ikeda, Masahiro Takakura, Kazuhiko Iwasaki
2003	—	`conf`	A seed selection procedure for LFSR-based random pattern generators. ASP-DAC Kenichi Ichino, Ko-ichi Watanabe, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki
2003	J	`jnl`	BIST-oriented test pattern generator for detection of transition faults. Syst. Comput. Jpn. Takeshi Asakawa, Kazuhiko Iwasaki, Seiji Kajihara
2003	—	`conf`	Implementation of Memory Tester Consisting of SRAM-Based Reconfigurable Cells. Asian Test Symposium Yuki Yamagata, Kenichi Ichino, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, Masayuki Satoh, Hiroyuki Itabashi, Takashi Murai, Nobuyuki Otsuka
2003	J	`jnl`	Seed Selection Procedure for LFSR-Based Random Pattern Generators. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kenichi Ichino, Ko-ichi Watanabe, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki
2002	—	`conf`	Adaptive Checkpointing for Time Warp Technique with a Limited Number of Checkpoints. ICDCS Workshops Ryo Suzuki, Satoshi Fukumoto, Kazuhiko Iwasaki
2002	C	`conf`	Evaluation of Convolutional-Code-Based FEC under Limited Recovery Time and Its Application to Real-time Transmission. PRDC Masayuki Arai, Hitoshi Kurosu, Satoshi Fukumoto, Kazuhiko Iwasaki
2002	—	`conf`	Experiment for High-Assurance Video Conference System over the Internet. HASE Masayuki Arai, Hitoshi Kurosu, Mamoru Ohara, Ryo Suzuki, Satoshi Fukumoto, Kazuhiko Iwasaki
2001	C	`conf`	Analysis of Using Convolutional Codes to Recover Packet Losses over Burst Erasure Channels. PRDC Masayuki Arai, Anna Yamamoto, Anna Yamaguchi, Satoshi Fukumoto, Kazuhiko Iwasaki
2001	—	`conf`	Hybrid BIST Using Partially Rotational Scan. Asian Test Symposium Kenichi Ichino, Takeshi Asakawa, Satoshi Fukumoto, Kazuhiko Iwasaki, Seiji Kajihara
2001	J	`jnl`	Using ATPG vectors for BIST test pattern generator. Syst. Comput. Jpn. Takeshi Asakawa, Kazuhiko Iwasaki
2000	C	`conf`	Evaluation of multicast error recovery using convolutional codes. PRDC Anna Yamaguchi, Masayuki Arai, Kazuhiko Iwasaki
2000	A	`conf`	Method to Recover Internet Packet Losses Using (n, n - 1, m) Convolutional Codes. DSN Masayuki Arai, Anna Yamaguchi, Kazuhiko Iwasaki
1999	C	`conf`	Measurement and Modeling of Burst Packet Losses in Internet End-to-End Communications. PRDC Masayuki Arai, Atsushi Chiba, Kazuhiko Iwasaki
1997	Misc	`conf`	Experimental fault analysis of 1 Mb SRAM chips. VTS Hiroyuki Goto, Shigeo Nakamura, Kazuhiko Iwasaki
1996	J	`jnl`	Aliasing Error for a Mask ROM Built-In Self-Test. IEEE Trans. Computers Kazuhiko Iwasaki, Shigeo Nakamura
1995	J	`jnl`	On the Maximum Value of Aliasing Probabilities for Single Input Signature Registers. IEEE Trans. Computers Shou-ping Feng, Toru Fujiwara, Tadao Kasami, Kazuhiko Iwasaki
1994	J	`jnl`	A Concurrent Test Architecture for Massively Parallel Computers and Its Error Detection Capability. IEEE Trans. Parallel Distributed Syst. Marius V. A. Hâncu, Kazuhiko Iwasaki, Yuji Sato, Mamoru Sugie
1994	Misc	`conf`	Aliasing error for a mask ROM built-in self-test. VTS Kazuhiko Iwasaki, Akinori Furuta, Shigeo Nakamura
1993	J	`jnl`	A Note on Aliasing Probability for Multiple Input Signature Analyzer. IEEE Trans. Computers Masakatu Morii, Kazuhiko Iwasaki
1993	J	`jnl`	A uniform network for VLSI massively parallel computers. Syst. Comput. Jpn. Kazuhiko Iwasaki, Christian Iseli, Yuji Sato
1993	Misc	`conf`	On the maximum value of aliasing probabilities for single input signature registers. VTS Shou-ping Feng, Toru Fujiwara, Tadao Kasami, Kazuhiko Iwasaki
1992	Misc	`conf`	A defect-tolerant design for mask ROMs. VTS Kazuhiko Iwasaki, Toru Fujiwara, Tadao Kasami
1992	J	`jnl`	Experimental results on the error detection capability of a concurrent test architecture for massively-parallel computers. Parallel Comput. Marius V. A. Hâncu, Kazuhiko Iwasaki, Yuji Sato, Mamoru Sugie
1991	A	`conf`	A Concurrent Test Architecture for Massively-Parallel Computers and its Error Detection Capability. ITC Marius V. A. Hâncu, Kazuhiko Iwasaki, Yuji Sato, Mamoru Sugie
1990	J	`jnl`	An analysis of the aliasing probability of multiple-input signature registers in the case of a 2 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kazuhiko Iwasaki, Fumio Arakawa
1990	J	`jnl`	Analysis of Fault Detection Probability of CMOS Combinational Circuits and Its Application to Signature Testing. Syst. Comput. Jpn. Kazuhiko Iwasaki
1990	A	`conf`	Design of signature circuits based on weight distributions of error-correcting codes. ITC Kazuhiko Iwasaki, Noboru Yamaguchi
1989	J	`jnl`	Aliasing Probabilities and Weight Distributions of Several Codes. Syst. Comput. Jpn. Kazuhiko Iwasaki, Tadahiko Nishimukai
1988	J	`jnl`	Analysis and proposal of signature circuits for LSI testing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kazuhiko Iwasaki
1988	C	`conf`	Cache-based pipeline architecture in the Hitachi H32/200 32-bit microprocessor. ICCD Tadahiko Nishimukai, Hideo Inayoshi, Kikuko Takagi, Kazuhiko Iwasaki, Ikuya Kawasaki, M. Hanawa, Takeshi Okada
1987	J	`jnl`	Decoding method for shortened fire codes and its application to VLSI processor. Syst. Comput. Jpn. Kazuhiko Iwasaki, Tsuneo Funabashi, Tatsuaki Ueno
1986	J	`jnl`	Analysis of error-detecting probability of signature circuit for lsi self-testing and proprosal of new signature circuit. Syst. Comput. Jpn. Kazuhiko Iwasaki, Noboru Yamaguchi, Yoshimune Hagiwara