Kazuei Hironaka

24 papers B 1C 1Journal 5Unranked 17
YearRankTypeTitle / Venue / Authors
2023 J jnl
A Multi-FPGA Implementation of FM-Index Based Genomic Pattern Search.
IEICE Trans. Inf. Syst.
M. M. Imdad Ullah, Akram Ben Ahmed, Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano
2023 J jnl
Power Analysis and Power Modeling of Directly-Connected FPGA Clusters.
IEICE Trans. Inf. Syst.
Kensuke Iizuka, Haruna Takagi, Aika Kamei, Kazuei Hironaka, Hideharu Amano
2022 — conf
A Message Passing Interface Library for High-Level Synthesis on Multi-FPGA Systems.
MCSoC
Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano
2022 — conf
Power Analysis of Directly-connected FPGA Clusters.
COOL CHIPS
Kensuke Iizuka, Haruna Takagi, Aika Kamei, Kazuei Hironaka, Hideharu Amano
2022 J jnl
The Implementation of a Hybrid Router and Dynamic Switching Algorithm on a Multi-FPGA System.
IEICE Trans. Inf. Syst.
Tomoki Shimizu, Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Hideharu Amano
2021 — conf
Hybrid Network of Packet Switching and STDM in a Multi-FPGA System.
COOL CHIPS
Tomoki Shimizu, Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Hideharu Amano
2021 — conf
Implementing VTA, a tensor accelerator on Flow-in-Cloud.
ACIT
Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano
2021 J jnl
Improving the Performance of Circuit-Switched Interconnection Network for a Multi-FPGA System.
IEICE Trans. Inf. Syst.
Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Yao Hu, Michihiro Koibuchi, Hideharu Amano
2021 — conf
M-KUBOS/PYNQ Cluster for multi-access edge computing.
CANDAR
Takumi Inage, Kazuei Hironaka, Kensuke Iizuka, Kohei Ito, Yasuyu Fukushima, Mitaro Namiki, Hideharu Amano
2021 J jnl
Remote Dynamic Reconfiguration of a Multi-FPGA System FiC (Flow-in-Cloud).
IEICE Trans. Inf. Syst.
Kazuei Hironaka, Kensuke Iizuka, Miho Yamakura, Akram Ben Ahmed, Hideharu Amano
2020 — conf
A Method of Partitioning Convolutional Layer to Multiple FPGAs.
ISOCC
Kensuke Iizuka, Kohei Ito, Kazuei Hironaka, Hideharu Amano
2020 — conf
Horizontal division of deep learning applications with all-to-all communication on a multi-FPGA system.
CANDAR (Workshops)
Yugo Yamauchi, Akram Ben Ahmed, Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano
2020 — conf
Implementing a Multi-ejection Switch and Making the Use of Multiple Lanes in a Circuit-switched Multi-FPGA System.
CANDAR (Workshops)
Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Yao Hu, Michihiro Koibuchi, Hideharu Amano
2019 — conf
A STDM (Static Time Division Multiplexing) Switch on a Multi-FPGA System.
MCSoC
Keita Azegami, Kazusa Musha, Kazuei Hironaka, Akram Ben Ahmed, Michihiro Koibuchi, Yao Hu, Hideharu Amano
2019 B conf
Demonstration of Flow-in-Cloud: A Multi-FPGA System.
FPL
Kazuei Hironaka, Kensuke Iizuka, Akram Ben Ahmed, M. M. Imdad Ullah, Yugo Yamauchi, Yuxi Sun, Miho Yamakura, Aoi Hiruma, Hideharu Amano
2019 C conf
Multi-FPGA Management on Flow-in-Cloud Prototype System.
SNPD
Kazuei Hironaka, Akram Ben Ahmed, Hideharu Amano
2019 — conf
The Evaluation of Partial Reconfiguration for a Multi-board FPGA System FiCSW.
HEART
Miho Yamakura, Kazuei Hironaka, Keita Azegami, Kazusa Musha, Hideharu Amano
2018 — conf
Towards an Optimized Multi FPGA Architecture with STDM Network: A Preliminary Study.
ARC
Kazuei Hironaka, Ng. Anh Vu Doan, Hideharu Amano
2012 — conf
Extension of Memory Controller Equipped with MuCCRA-3-DP: Dynamically Reconfigurable Processor Array.
NBiS
Toru Katagiri, Kazuei Hironaka, Hideharu Amano
2011 — conf
Dynamic V
ARC
Tatsuya Yamamoto, Kazuei Hironaka, Yuki Hayakawa, Masayuki Kimura, Hideharu Amano, Kimiyoshi Usami
2011 — conf
Power Centric Application Mapping for Dynamically Reconfigurable Processor Array with Dual Vdd and Dual Vth.
ReConFig
Kazuei Hironaka, Hideharu Amano
2011 — conf
Reducing power for dynamically reconfigurable processor array by reducing number of reconfigurations.
FPT
Masayuki Kimura, Kazuei Hironaka, Hideharu Amano
2011 — conf
The realtime image processing demonstration with CMA-1: An ultra low-power reconfigurable accelerator.
FPT
Kazuei Hironaka, Nobuaki Ozaki, Hideharu Amano
2010 — conf
Reducing power consumption for Dynamically Reconfigurable Processor Array with Partially Fixed Configuration Mapping.
FPT
Kazuei Hironaka, Masayuki Kimura, Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Hideharu Amano