Kavita Khare

28 papers Misc 3Journal 17Unranked 8
YearRankTypeTitle / Venue / Authors
2024 J jnl
Approximate Row-Merging-Based Multipliers for Neural Network Acceleration on FPGAs.
IEEE Embed. Syst. Lett.
Zainab Aizaz, Kavita Khare, Aizaz Tirmizi
2023 — conf
A1RL: Approximate 1-Row-LUT-Based Low-Power Signed Multipliers for DSP and Machine Learning Applications on FPGAs.
APCCAS
Zainab Aizaz, Kavita Khare, Mohd Anas Khan, Mahesh Kumar Singh, Vaithiyanathan Dhandapani
2023 J jnl
ASMPEC: Approximate-Sum-Based Mapping of Partial Products With Error Correction for Softcore Multipliers on FPGAs.
IEEE Trans. Circuits Syst. II Express Briefs
Zainab Aizaz, Kavita Khare
2023 Misc conf
FASBM: FPGA-specific Approximate Sum-based Booth multipliers for energy efficient Hardware Acceleration of Image Processing and Machine Learning Applications.
FCCM
Zainab Aizaz, Kavita Khare, Aizaz Tirmizi
2022 J jnl
Area and Power Efficient Truncated Booth Multipliers Using Approximate Carry-Based Error Compensation.
IEEE Trans. Circuits Syst. II Express Briefs
Zainab Aizaz, Kavita Khare
2022 J jnl
Energy efficient approximate booth multipliers using compact error compensation circuit for mitigation of truncation error.
Int. J. Circuit Theory Appl.
Zainab Aizaz, Kavita Khare
2021 J jnl
A Novel Approach for Optimal Design of Sample Rate Conversion Filter Using Linear Optimization Technique.
IEEE Access
Divya Gautam, Kavita Khare, Bhavana P. Shrivastava
2019 J jnl
Design and Analysis of Low-Power Adiabatic Logic Circuits by Using CNTFET Technology.
Circuits Syst. Signal Process.
Ajay Kumar Dadoria, Kavita Khare
2018 J jnl
New Leakage Reduction Techniques for FinFET Technology with Its Application.
J. Circuits Syst. Comput.
Ajay Kumar Dadoria, Kavita Khare, Tarun Kumar Gupta, R. P. Singh
2016 J jnl
Concept, Design, and Implementation of Reconfigurable CORDIC.
IEEE Trans. Very Large Scale Integr. Syst.
Supriya Aggarwal, Pramod Kumar Meher, Kavita Khare
2016 — conf
Leakage Power Reduction Technique by using FinFET Technology.
ICTCS
Ajay Kumar Dadoria, Kavita Khare, R. P. Singh
2016 — conf
Low-Power High Speed 1-bit Full Adder Circuit Design.
ICTCS
Shailesh Dwivedi, Kavita Khare, Ajay Kumar Dadoria
2013 — conf
3D CORDIC Algorithm Based Cartesian to Spherical Coordinate Converter.
VDAT
Anita Jain, Kavita Khare
2013 J jnl
CORDIC-based window implementation to minimise area and pipeline depth.
IET Signal Process.
Supriya Aggarwal, Kavita Khare
2013 Misc conf
Efficient Window-Architecture Design Using Completely Scaling-Free CORDIC Pipeline.
VLSI Design
Supriya Aggarwal, Kavita Khare
2013 J jnl
Leading One Detection Hyperbolic CORDIC with Enhanced Range of Convergence.
J. Signal Process. Syst.
Supriya Aggarwal, Kavita Khare
2013 J jnl
Lector with Footed-Diode Inverter: A Technique for Leakage Reduction in Domino Circuits.
Circuits Syst. Signal Process.
Tarun Kumar Gupta, Kavita Khare
2013 J jnl
Scale-Free Hyperbolic CORDIC Processor and Its Application to Waveform Generation.
IEEE Trans. Circuits Syst. I Regul. Pap.
Supriya Aggarwal, Pramod Kumar Meher, Kavita Khare
2012 J jnl
Area-Time Efficient Scaling-Free CORDIC Using Generalized Micro-Rotation Selection.
IEEE Trans. Very Large Scale Integr. Syst.
Supriya Aggarwal, Pramod Kumar Meher, Kavita Khare
2012 J jnl
Design Techniques Targeting Low-Area-Power-Delay Product in Hyperbolic CORDIC Algorithm.
Comput. J.
Supriya Aggarwal, Kavita Khare
2012 J jnl
FPGA Implementation of Cross Virtual Concatenation Transmitter/ Receiver for Data Transmission over Next Generation SDH Systems.
J. Signal Process. Syst.
Sunanda Manke, Kavita Khare, S. D. Sapre
2012 Misc conf
Hardware Efficient Architecture for Generating Sine/Cosine Waves.
VLSI Design
Supriya Aggarwal, Kavita Khare
2012 J jnl
Redesigned-Scale-Free CORDIC Algorithm Based FPGA Implementation of Window Functions to Minimize Area and Latency.
Int. J. Reconfigurable Comput.
Supriya Aggarwal, Kavita Khare
2011 J jnl
VCAT synchroniser - reduction of buffer size in VCAT enabled next generation SDH networks.
Eur. Trans. Telecommun.
Sunanda Manke, Kavita Khare, S. D. Sapre
2010 — conf
Standby leakage reduction in nanoscale CMOS VLSI circuits.
ICWET
J. Deshmukh, Kavita Khare
2009 — conf
Differential Delay Compensator -- A New Approach to Reduce Buffer Size in VCAT Enabled Next Generation SDH Networks.
ARTCom
Sunanda Manke, Kavita Khare, S. D. Sapre
2009 — conf
FPGA Design and Implementation Issues of Artificial Neural Network Based PID Controllers.
ARTCom
Vikas Gupta, Kavita Khare, R. P. Singh
2008 — conf
100Mbps Ethernet data transmission over SDH networks using Cross Virtual Concatenation.
ICON
Sunanda Manke, Kavita Khare, S. D. Sapre