Kaustav Banerjee

70 papers A* 13A 18C 1Misc 1Journal 16Unranked 21

Year	Rank	Type	Title / Venue / Authors
2023	—	`conf`	Exploration and Exploitation of Strain Engineering in 2D-FETs. DRC Ankit Kumar, Arnab Pal, Kamyar Parto, Wei Cao, Kaustav Banerjee
2020	J	`jnl`	Correction to "Analytical Thermal Model for Self-Heating in Advanced FinFET Devices With Implications for Design and Reliability". IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chuan Xu, Seshadri K. Kolluri, Kazuhiko Endo, Kaustav Banerjee
2013	—	`conf`	2D electronics: Graphene and beyond. ESSDERC Wei Cao, Jiahao Kang, Wei Liu, Yasin Khatami, Deblina Sarkar, Kaustav Banerjee
2013	J	`jnl`	Analytical Thermal Model for Self-Heating in Advanced FinFET Devices With Implications for Design and Reliability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chuan Xu, Seshadri K. Kolluri, Kazuhiko Endo, Kaustav Banerjee
2012	J	`jnl`	Fast High-Frequency Impedance Extraction of Horizontal Interconnects and Inductors in 3-D ICs With Multiple Substrates. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chuan Xu, Navin Srivastava, Roberto Suaya, Kaustav Banerjee
2010	J	`jnl`	A Novel Variation-Tolerant Keeper Architecture for High-Performance Low-Power Wide Fan-In Dynamic or Gates. IEEE Trans. Very Large Scale Integr. Syst. Hamed F. Dadgour, Kaustav Banerjee
2010	A	`conf`	A new paradigm in the design of energy-efficient digital circuits using laterally-actuated double-gate NEMs. ISLPED Hamed F. Dadgour, Muhammad Mustafa Hussain, Kaustav Banerjee
2010	A	`conf`	Aging-resilient design of pipelined architectures using novel detection and correction circuits. DATE Hamed F. Dadgour, Kaustav Banerjee
2010	J	`jnl`	Carbon Nanomaterials: The Ideal Interconnect Technology for Next-Generation ICs. IEEE Des. Test Comput. Hong Li, Chuan Xu, Kaustav Banerjee
2010	J	`jnl`	Corrections to "Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate" [Jul 09 1047-1060]. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Navin Srivastava, Chuan Xu, Roberto Suaya, Kaustav Banerjee
2010	A*	`conf`	Design and analysis of compact ultra energy-efficient logic gates using laterally-actuated double-electrode NEMS. DAC Hamed F. Dadgour, Muhammad Mustafa Hussain, Casey Smith, Kaustav Banerjee
2010	A	`conf`	Efficient 3D high-frequency impedance extraction for general interconnects and inductors above a layered substrate. DATE Navin Srivastava, Roberto Suaya, Kaustav Banerjee
2010	A	`conf`	Work-function variation induced fluctuation in bias-temperature-instability characteristics of emerging metal-gate devices and implications for digital design. ICCAD Seid Hadi Rasouli, Kazuhiko Endo, Kaustav Banerjee
2009	J	`jnl`	Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Navin Srivastava, Roberto Suaya, Kaustav Banerjee
2009	A	`conf`	CMOS vs Nano: comrades or rivals? FPGA Deming Chen, Russell Tessier, Kaustav Banerjee, Mojy C. Chian, André DeHon, Shinobu Fujita, James Hutchby, Steve Trimberger
2009	A	`conf`	Fast 3-D thermal analysis of complex interconnect structures using electrical modeling and simulation methodologies. ICCAD Chuan Xu, Lijun Jiang, Seshadri K. Kolluri, Barry J. Rubin, Alina Deutsch, Howard H. Smith, Kaustav Banerjee
2009	—	`conf`	Graphene based nanomaterials for VLSI interconnect and energy-storage applications. SLIP Kaustav Banerjee
2009	—	`conf`	Graphene based transistors: physics, status and future perspectives. ISPD Kaustav Banerjee, Yasin Khatami, Chaitanya Kshirsagar, Seid Hadi Rasouli
2009	—	`conf`	High-speed low-power FinFET based domino logic. ASP-DAC Seid Hadi Rasouli, Hanpei Koike, Kaustav Banerjee
2009	J	`jnl`	Hybrid NEMS-CMOS integrated circuits: A novel strategy for energy-efficient designs. IET Comput. Digit. Tech. Hamed F. Dadgour, Kaustav Banerjee
2009	A	`conf`	Variability analysis of FinFET-based devices and circuits considering electrical confinement and width quantization. ICCAD Seid Hadi Rasouli, Kazuhiko Endo, Kaustav Banerjee
2008	J	`jnl`	A Design-Specific and Thermally-Aware Methodology for Trading-Off Power and Performance in Leakage-Dominant CMOS Technologies. IEEE Trans. Very Large Scale Integr. Syst. Sheng-Chih Lin, Kaustav Banerjee
2008	A*	`conf`	Analysis and implications of parasitic and screening effects on the high-frequency/RF performance of tunneling-carbon nanotube FETs. DAC Chaitanya Kshirsagar, Mohamed N. El-Zeftawi, Kaustav Banerjee
2008	A	`conf`	High-Frequency Mutual Impedance Extraction of VLSI Interconnects In the Presence of a Multi-layer Conducting Substrate. DATE Navin Srivastava, Roberto Suaya, Kaustav Banerjee
2008	A	`conf`	Statistical modeling of metal-gate work-function variability in emerging device technologies and implications for circuit design. ICCAD Hamed F. Dadgour, Vivek De, Kaustav Banerjee
2007	J	`jnl`	3D Integration for Introspection. IEEE Micro Shashidhar Mysore, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Kaustav Banerjee, Timothy Sherwood
2007	A*	`conf`	Design and Analysis of Hybrid NEMS-CMOS Circuits for Ultra Low-Power Applications. DAC Hamed F. Dadgour, Kaustav Banerjee
2007	Misc	`conf`	Tutorial 5: SoC Communication Architectures: Technology, Current Practice, Research, and Trends. VLSI Design Nikil D. Dutt, Kaustav Banerjee, Luca Benini, Kanishka Lahiri, Sudeep Pasricha
2006	A*	`conf`	A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates. DAC Hamed F. Dadgour, Rajiv V. Joshi, Kaustav Banerjee
2006	A*	`conf`	A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy. DAC Gian Luca Loi, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Timothy Sherwood, Kaustav Banerjee
2006	A	`conf`	An electrothermally-aware full-chip substrate temperature gradient evaluation methodology for leakage dominant technologies with implications for power estimation and hot-spot management. ICCAD Sheng-Chih Lin, Kaustav Banerjee
2006	A*	`conf`	Are carbon nanotubes the future of VLSI interconnections? DAC Kaustav Banerjee, Navin Srivastava
2006	—	`conf`	Can Carbon Nanotubes Extend the Lifetime of On-Chip Electrical Interconnections? Nano-Net Kaustav Banerjee, Sungjun Im, Navin Srivastava
2006	—	`conf`	Electrothermal engineering in the nanometer era: from devices and interconnects to circuits and systems. ASP-DAC Kaustav Banerjee, Sheng-Chih Lin, Navin Srivastava
2006	A*	`conf`	Introspective 3D chips. ASPLOS Shashidhar Mysore, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Kaustav Banerjee, Timothy Sherwood
2006	—	`conf`	Tutorial 1: Emerging Technologies for VLSI Design. ISQED Rajiv V. Joshi, Kaustav Banerjee, André DeHon
2005	C	`conf`	A Thermally-Aware Methodology for Design-Specific Optimization of Supply and Threshold Voltages in Nanometer Scale ICs. ICCD Sheng-Chih Lin, Navin Srivastava, Kaustav Banerjee
2005	A	`conf`	A probabilistic framework for power-optimal repeater insertion in global interconnects under parameter variations. ISLPED Vineet Wason, Kaustav Banerjee
2005	—	`conf`	Impact of On-chip Inductance on Power Distribution Network Design for Nanometer Scale Integrated Circuits. ISQED Navin Srivastava, Xiaoning Qi, Kaustav Banerjee
2005	J	`jnl`	Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Amir H. Ajami, Kaustav Banerjee, Massoud Pedram
2005	A	`conf`	Performance analysis of carbon nanotube interconnects for VLSI applications. ICCAD Navin Srivastava, Kaustav Banerjee
2005	—	`conf`	Plenary Session 2P. ISQED Lech Józwiak, Kaustav Banerjee
2005	J	`jnl`	Supply and power optimization in leakage-dominant technologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Man Lung Mui, Kaustav Banerjee, Amit Mehrotra
2004	—	`conf`	A Comprehensive Analytical Capacitance Model of a Two Dimensional Nanodot Array. ISQED Anirban Basu, Sheng-Chih Lin, Christoph Wasshuber, Adrian M. Ionescu, Kaustav Banerjee
2004	A	`conf`	A probabilistic framework to estimate full-chips subthreshold leakage power distribution considering within-die and die-to-die P-T-V variations. ISLPED Songqing Zhang, Vineet Wason, Kaustav Banerjee
2004	J	`jnl`	Modeling techniques and verification methodologies for substrate coupling effects in mixed-signal system-on-chip designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Adil Koukab, Kaustav Banerjee, Michel J. Declercq
2004	—	`conf`	Power Supply Optimization in sub-130 nm Leakage Dominant Technologies . ISQED Man Lung Mui, Kaustav Banerjee, Amit Mehrotra
2004	A*	`conf`	Simultaneous optimization of supply and threshold voltages for low-power and high-performance circuits in the leakage dominant era. DAC Anirban Basu, Sheng-Chih Lin, Vineet Wason, Amit Mehrotra, Kaustav Banerjee
2003	A	`conf`	A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated Circuits. ICCAD Santanu Mahapatra, Kaustav Banerjee, Florent Pegeon, Adrian M. Ionescu
2003	—	`conf`	Nano, quantum, and molecular computing: are we ready for the validation and test challenges? HLDVT Sandeep K. Shukla, Ramesh Karri, Seth Copen Goldstein, Forrest Brewer, Kaustav Banerjee, Sankar Basu
2002	—	`conf`	A SET quantizer circuit aiming at digital communication system. ISCAS (5) Santanu Mahapatra, Adrian M. Ionescu, Kaustav Banerjee, Michel J. Declercq
2002	A	`conf`	Analysis and optimization of substrate noise coupling in single-chip RF transceiver design. ICCAD Adil Koukab, Kaustav Banerjee, Michel J. Declercq
2002	J	`jnl`	Analysis of on-chip inductance effects for distributed RLC interconnects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kaustav Banerjee, Amit Mehrotra
2002	A*	`conf`	Few electron devices: towards hybrid CMOS-SET integrated circuits. DAC Adrian M. Ionescu, Michel J. Declercq, Santanu Mahapatra, Kaustav Banerjee, Jacques Gautier
2002	—	`conf`	Inductance Aware Interconnect Scaling. ISQED Kaustav Banerjee, Amit Mehrotra
2002	—	`conf`	Modeling and Design of a Low-Voltage SOI Suspended-Gate MOSFET (SG-MOSFET) with a Metal-over-Gate Architecture. ISQED Adrian M. Ionescu, V. Pott, R. Fritschi, Kaustav Banerjee, Michel J. Declercq, Philippe Renaud, C. Hibert, Philippe Flückiger, G. A. Racine
2001	J	`jnl`	3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration. Proc. IEEE Kaustav Banerjee, Shukri J. Souri, Pawan Kapur, Krishna C. Saraswat
2001	—	`conf`	A fast analytical technique for estimating the bounds of on-chip clock wire inductance. CICC Yi-Chang Lu, Kaustav Banerjee, Mustafa Celik, Robert W. Dutton
2001	—	`conf`	Analysis and Design of ESD Protection Circuits for High-Frequency/RF Applications. ISQED Choshu Ito, Kaustav Banerjee, Robert W. Dutton
2001	—	`conf`	Analysis and optimization of thermal issues in high-performance VLSI. ISPD Kaustav Banerjee, Massoud Pedram, Amir H. Ajami
2001	A*	`conf`	Analysis of Non-Uniform Temperature-Dependent Interconnect Performance in High Performance ICs. DAC Amir H. Ajami, Kaustav Banerjee, Massoud Pedram, Lukas P. P. P. van Ginneken
2001	A*	`conf`	Analysis of On-Chip Inductance Effects using a Novel Performance Optimization Methodology for Distributed RLC Interconnects. DAC Kaustav Banerjee, Amit Mehrotra
2001	A	`conf`	Analysis of Substrate Thermal Gradient Effects on Optimal Buffer Insertion. ICCAD Amir H. Ajami, Kaustav Banerjee, Massoud Pedram
2001	A	`conf`	Compact Modeling and SPICE-Based Simulation for Electrothermal Analysis of Multilevel ULSI Interconnects. ICCAD TingYen Chiang, Kaustav Banerjee, Krishna Saraswat
2001	A	`conf`	Coupled Analysis of Electromigration Reliability and Performance in ULSI Signal Nets. ICCAD Kaustav Banerjee, Amit Mehrotra
2001	—	`conf`	Effects of non-uniform substrate temperature on the clock signal integrity in high performance designs. CICC Amir H. Ajami, Massoud Pedram, Kaustav Banerjee
2001	J	`jnl`	Interconnect limits on gigascale integration (GSI) in the 21st century. Proc. IEEE Jeffery A. Davis, Raguraman Venkatesan, Alan Kaloyeros, Michael Beylansky, Shukri J. Souri, Kaustav Banerjee, Krishna C. Saraswat, Arifur Rahman, Rafael Reif, James D. Meindl
2000	A*	`conf`	Multiple Si layer ICs: motivation, performance analysis, and design implications. DAC Shukri J. Souri, Kaustav Banerjee, Amit Mehrotra, Krishna Saraswat
2000	—	`conf`	Performance analysis and technology of 3-D ICs. SLIP Krishna Saraswat, Shukri J. Souri, Kaustav Banerjee, Pawan Kapur
1999	A*	`conf`	On Thermal Effects in Deep Sub-Micron VLSI Interconnects. DAC Kaustav Banerjee, Amit Mehrotra, Alberto L. Sangiovanni-Vincentelli, Chenming Hu