Kaushik Roy - RankMe

1048 papers A* 84A 171B 29C 48Misc 38Journal 500Unranked 171

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Achieving Global Flatness in Decentralized Learning with Heterogeneous Data. Trans. Mach. Learn. Res. Sakshi Choudhary, Sai Aparna Aketi, Kaushik Roy
2026	J	`jnl`	From Clutter to Clarity: Visual Recognition through Foveated Object-Centric Learning (FocL). Trans. Mach. Learn. Res. Amitangshu Mukherjee, Deepak Ravikumar, Kaushik Roy
2026	J	`jnl`	Learning to Localize Leakage of Cryptographic Sensitive Variables. Trans. Mach. Learn. Res. Jimmy Gammell, Anand Raghunathan, Abolfazl Hashemi, Kaushik Roy
2026	J	`jnl`	Loss Knows Best: Detecting Annotation Errors in Videos via Loss Trajectories. CoRR Praditha Alwis, Soumyadeep Chandra, Deepak Ravikumar, Kaushik Roy
2026	J	`jnl`	SWE-Adept: An LLM-Based Agentic Framework for Deep Codebase Analysis and Structured Issue Resolution. CoRR Kang He, Kaushik Roy
2026	J	`jnl`	TopoPrune: Robust Data Pruning via Unified Latent Space Topology. CoRR Arjun Roy, Prajna G. Malettira, Manish Nagaraj, Kaushik Roy
2026	J	`jnl`	TraceNAS: Zero-shot LLM Pruning via Gradient Trace Correlation. CoRR Prajna G. Malettira, Manish Nagaraj, Arjun Roy, Shubham Negi, Kaushik Roy
2026	J	`jnl`	WildCross: A Cross-Modal Large Scale Benchmark for Place Recognition and Metric Depth Estimation in Natural Environments. CoRR Joshua Knights, Joseph Reid, Kaushik Roy, David Hall, Mark Cox, Peyman Moghadam
2025	J	`jnl`	2D-ThermAl: Physics-Informed Framework for Thermal Analysis of Circuits using Generative AI. CoRR Soumyadeep Chandra, Sayeed Shafayet Chowdhury, Kaushik Roy
2025	J	`jnl`	ASMA: An $\underline{\text{A}}$daptive $\underline{\text{S}}$afety $\underline{\text{M}}$argin $\underline{\text{A}}$lgorithm for Vision-Language Drone Navigation via Scene-Aware Control Barrier Functions. IEEE Robotics Autom. Lett. Sourav Sanyal, Kaushik Roy
2025	C	`conf`	AlphaBlend: Hardware-Algorithm Co-design with Mixed-Alphabet Set Multipliers for DNN Workloads. ISCAS Arani Roy, Kaushik Roy
2025	J	`jnl`	Amphibian: A Meta-Learning Framework for Rehearsal-Free, Fast Online Continual Learning. Trans. Mach. Learn. Res. Gobinda Saha, Kaushik Roy
2025	C	`conf`	Building Resilient AI: Strengthening Data, Security, and Robustness in Neural Networks. IOLTS Deepak Ravikumar, Jimmy Gammell, Kaushik Roy
2025	J	`jnl`	COMET: A Framework for Modeling Compound Operation Dataflows with Explicit Collectives. CoRR Shubham Negi, Manik Singhal, Aayush Ankit, Sudeep Bhoja, Kaushik Roy
2025	J	`jnl`	CURE: Concept Unlearning via Orthogonal Representation Editing in Diffusion Models. CoRR Shristi Das Biswas, Arani Roy, Kaushik Roy
2025	J	`jnl`	Coresets from Trajectories: Selecting Data via Correlation of Loss Differences. CoRR Manish Nagaraj, Deepak Ravikumar, Kaushik Roy
2025	J	`jnl`	Coresets from Trajectories: Selecting Data via Correlation of Loss Differences. Trans. Mach. Learn. Res. Manish Nagaraj, Deepak Ravikumar, Kaushik Roy
2025	A*	`conf`	DCT-CryptoNets: Scaling Private Inference in the Frequency Domain. ICLR Arjun Roy, Kaushik Roy
2025	B	`conf`	Energy-Efficient Autonomous Aerial Navigation with Dynamic Vision Sensors: A Physics-Guided Neuromorphic Approach. IJCNN Sourav Sanyal, Amogh Joshi, Manish Nagaraj, Rohan Kumar Manna, Kaushik Roy
2025	J	`jnl`	Energy-Efficient Autonomous Aerial Navigation with Dynamic Vision Sensors: A Physics-Guided Neuromorphic Approach. CoRR Sourav Sanyal, Amogh Joshi, Manish Nagaraj, Rohan Kumar Manna, Kaushik Roy
2025	B	`conf`	Evaluating Compute in Memory Architectures for Matrix Multiplication: A Dataflow-Centric Perspective. ISPASS Tanvi Sharma, Indranil Chakraborty, Mustafa Fayez Ali, Kaushik Roy
2025	J	`jnl`	Experts are all you need: A Composable Framework for Large Language Model Inference. CoRR Shrihari Sridharan, Sourjya Roy, Anand Raghunathan, Kaushik Roy
2025	J	`jnl`	Feedback Alignment Meets Low-Rank Manifolds: A Structured Recipe for Local Learning. CoRR Arani Roy, Marco Paul E. Apolinario, Shristi Das Biswas, Kaushik Roy
2025	J	`jnl`	Finding the Muses: Identifying Coresets through Loss Trajectories. CoRR Manish Nagaraj, Deepak Ravikumar, Efstathia Soufleri, Kaushik Roy
2025	J	`jnl`	GradientSpace: Unsupervised Data Clustering for Improved Instruction Tuning. CoRR Shrihari Sridharan, Deepak Ravikumar, Anand Raghunathan, Kaushik Roy
2025	J	`jnl`	HALO: Memory-Centric Heterogeneous Accelerator with 2.5D Integration for Low-Batch LLM Inference. CoRR Shubham Negi, Kaushik Roy
2025	—	`conf`	HCiM: ADC-Less Hybrid Analog-Digital Compute in Memory Accelerator for Deep Learning Workloads. ASP-DAC Shubham Negi, Utkarsh Saxena, Deepika Sharma, Kaushik Roy
2025	J	`jnl`	Hardware-Software Co-Design for Accelerating Transformer Inference Leveraging Compute-in-Memory. CoRR Dong Eun Kim, Tanvi Sharma, Kaushik Roy
2025	—	`conf`	Improved Out-of-Distribution Detection with Additive Angular Margin Loss. CVPR Workshops Deepak Ravikumar, Efstathia Soufleri, Kaushik Roy
2025	A	`conf`	Intelligent Sensing-to-Action for Robust Autonomy at the Edge: Opportunities and Challenges. DATE Amit Ranjan Trivedi, Sina Tayebati, Hemant Kumawat, Nastaran Darabi, Divake Kumar, Adarsh Kumar Kosta, Yeshwanth Venkatesha, Dinithi Jayasuriya, Nethmi Jayasinghe, Priyadarshini Panda, Saibal Mukhopadhyay, Kaushik Roy
2025	J	`jnl`	Intelligent Sensing-to-Action for Robust Autonomy at the Edge: Opportunities and Challenges. CoRR Amit Ranjan Trivedi, Sina Tayebati, Hemant Kumawat, Nastaran Darabi, Divake Kumar, Adarsh Kumar Kosta, Yeshwanth Venkatesha, Dinithi Jayasuriya, Nethmi Jayasinghe, Priyadarshini Panda, Saibal Mukhopadhyay, Kaushik Roy
2025	J	`jnl`	KVLinC : KV Cache Quantization with Hadamard Rotation and Linear Correction. CoRR Utkarsh Saxena, Kaushik Roy
2025	J	`jnl`	LANCE: Low Rank Activation Compression for Efficient On-Device Continual Learning. CoRR Marco Paul E. Apolinario, Kaushik Roy
2025	J	`jnl`	LIMO: Low-Power In-Memory-Annealer and Matrix-Multiplication Primitive for Edge Computing. CoRR Amod Holla, Sumedh Chatterjee, Sutanu Sen, Anushka Mukherjee, Fernando García-Redondo, Dwaipayan Biswas, Francesca Iacopi, Kaushik Roy
2025	A	`conf`	LLS: Local Learning Rule for Deep Neural Networks Inspired by Neural Activity Synchronization. WACV Marco Paul E. Apolinario, Arani Roy, Kaushik Roy
2025	J	`jnl`	Learning to Localize Leakage of Cryptographic Sensitive Variables. CoRR Jimmy Gammell, Anand Raghunathan, Abolfazl Hashemi, Kaushik Roy
2025	A	`conf`	MemRaptor: Magnetoresistive Array as Matrix Vector Multiplication and Transcendental Function Operator for NLP Applications. ISLPED Dong Eun Kim, Tanvi Sharma, Anushka Mukherjee, Mainakh Mukherjee, Kaushik Roy
2025	B	`conf`	Neuro-LIFT: A Neuromorphic, LLM-based Interactive Framework for Autonomous Drone FlighT at the Edge. IJCNN Amogh Joshi, Sourav Sanyal, Kaushik Roy
2025	J	`jnl`	Neuro-LIFT: A Neuromorphic, LLM-based Interactive Framework for Autonomous Drone FlighT at the Edge. CoRR Amogh Joshi, Sourav Sanyal, Kaushik Roy
2025	J	`jnl`	Now You See It, Now You Don't - Instant Concept Erasure for Safe Text-to-Image and Video Generation. CoRR Shristi Das Biswas, Arani Roy, Kaushik Roy
2025	J	`jnl`	On Inherent Adversarial Robustness of Active Vision Systems. Trans. Mach. Learn. Res. Amitangshu Mukherjee, Timur Ibrayev, Kaushik Roy
2025	J	`jnl`	Real-Time Neuromorphic Navigation: Guiding Physical Robots with Event-Based Sensing and Task-Specific Reconfigurable Autonomy Stack. CoRR Sourav Sanyal, Amogh Joshi, Adarsh Kosta, Kaushik Roy
2025	A*	`conf`	ResQ: Mixed-Precision Quantization of Large Language Models with Low-Rank Residuals. ICML Utkarsh Saxena, Sayeh Sharify, Kaushik Roy, Xin Wang
2025	J	`jnl`	S-TLLR: STDP-inspired Temporal Local Learning Rule for Spiking Neural Networks. Trans. Mach. Learn. Res. Marco Paul E. Apolinario, Kaushik Roy
2025	A	`conf`	SADDLe: Sharpness-Aware Decentralized Deep Learning with Heterogeneous Data. WACV Sakshi Choudhary, Sai Aparna Aketi, Kaushik Roy
2025	A*	`conf`	SAP: Corrective Machine Unlearning with Scaled Activation Projection for Label Noise Robustness. AAAI Sangamesh Kodge, Deepak Ravikumar, Gobinda Saha, Kaushik Roy
2025	A*	`conf`	SHIRE: Enhancing Sample Efficiency using Human Intuition in REinforcement Learning. ICRA Amogh Joshi, Adarsh Kosta, Kaushik Roy
2025	J	`jnl`	Semantic-Syntactic Discrepancy in Images (SSDI): Learning Meaning and Order of Features from Natural Images. Trans. Mach. Learn. Res. Chun Tao, Timur Ibrayev, Kaushik Roy
2025	J	`jnl`	SlimDiff: Training-Free, Activation-Guided Hands-free Slimming of Diffusion Models. CoRR Arani Roy, Shristi Das Biswas, Kaushik Roy
2025	A*	`conf`	TAXI: Traveling Salesman Problem Accelerator with X-bar-based Ising Macros Powered by SOT-MRAMs and Hierarchical Clustering. DAC Sangmin Yoo, Amod Holla, Sourav Sanyal, Dong Eun Kim, Francesca Iacopi, Dwaipayan Biswas, James Myers, Kaushik Roy
2025	J	`jnl`	TAXI: Traveling Salesman Problem Accelerator with X-bar-based Ising Macros Powered by SOT-MRAMs and Hierarchical Clustering. CoRR Sangmin Yoo, Amod Holla, Sourav Sanyal, Dong Eun Kim, Francesca Iacopi, Dwaipayan Biswas, James Myers, Kaushik Roy
2025	B	`conf`	TESS: A Scalable Temporally and Spatially Local Learning Rule for Spiking Neural Networks. IJCNN Marco Paul E. Apolinario, Kaushik Roy, Charlotte Frenkel
2025	J	`jnl`	TESS: A Scalable Temporally and Spatially Local Learning Rule for Spiking Neural Networks. CoRR Marco Paul E. Apolinario, Kaushik Roy, Charlotte Frenkel
2025	J	`jnl`	TOFFE - Temporally-binned Object Flow from Events for High-speed and Energy-Efficient Object Detection and Tracking. CoRR Adarsh Kumar Kosta, Amogh Joshi, Arjun Roy, Rohan Kumar Manna, Manish Nagaraj, Kaushik Roy
2025	J	`jnl`	TRIM: Token-wise Attention-Derived Saliency for Data-Efficient Instruction Tuning. CoRR Manish Nagaraj, Sakshi Choudhary, Utkarsh Saxena, Deepak Ravikumar, Kaushik Roy
2025	J	`jnl`	TSkips: Efficiency Through Explicit Temporal Delay Connections in Spiking Neural Networks. Trans. Mach. Learn. Res. Prajna G. Malettira, Shubham Negi, Wachirawit Ponghiran, Kaushik Roy
2025	J	`jnl`	The Easy Path to Robustness: Coreset Selection using Sample Hardness. CoRR Pranav Ramesh, Arjun Roy, Deepak Ravikumar, Kaushik Roy, Gopalakrishnan Srinivasan
2025	A*	`conf`	Towards Memorization Estimation: Fast, Formal and Free. ICML Deepak Ravikumar, Efstathia Soufleri, Abolfazl Hashemi, Kaushik Roy
2025	J	`jnl`	Towards Scalable Modeling of Compressed Videos for Efficient Action Recognition. CoRR Shristi Das Biswas, Efstathia Soufleri, Arani Roy, Kaushik Roy
2025	A	`conf`	Tutorial: Autonomy with Neuromorphic System. ISLPED Amit Ranjan Trivedi, Priyadarshini Panda, Kaushik Roy, Saibal Mukhopadhyay
2025	J	`jnl`	ViPeR: Vision-Based Surgical Phase Recognition. IEEE Access Soumyadeep Chandra, Sayeed Shafayet Chowdhury, Courtney Yong, Ginnie Jeng, Ashorne Mahenthiran, Kostantinos E. Morris, Harrison L. Love, Chandru P. Sundaram, Kaushik Roy
2025	J	`jnl`	WAGONN: Weight Bit Agglomeration in Crossbar Arrays for Reduced Impact of Interconnect Resistance on DNN Inference Accuracy. IEEE Trans. Circuits Syst. I Regul. Pap. Jeffry Victor, Dong Eun Kim, Chunguang Wang, Kaushik Roy, Sumeet Kumar Gupta
2025	J	`jnl`	What, When, Where to Compute-in-Memory for Efficient Matrix Multiplication During Machine Learning Inference. IEEE Trans. Emerg. Top. Comput. Tanvi Sharma, Mustafa Fayez Ali, Indranil Chakraborty, Kaushik Roy
2024	J	`jnl`	A collective AI via lifelong learning and sharing at the edge. Nat. Mac. Intell. Andrea Soltoggio, Eseoghene Ben-Iwhiwhu, Vladimir Braverman, Eric Eaton, Benjamin Epstein, Yunhao Ge, Lucy Halperin, Jonathan P. How, Laurent Itti, Michael A. Jacobs, Pavan Kantharaju, Long Le, Steven Lee, Xinran Liu, Sildomar T. Monteiro, David Musliner, Saptarshi Nath, Priyadarshini Panda, Christos Peridis, Hamed Pirsiavash, Vishwa S. Parekh, Kaushik Roy, Shahaf S. Shperberg, Hava T. Siegelmann, Peter Stone, Kyle Vedder, Jingfeng Wu, Lin Yang, Guangyao Zheng, Soheil Kolouri
2024	J	`jnl`	ASMA: An Adaptive Safety Margin Algorithm for Vision-Language Drone Navigation via Scene-Aware Control Barrier Functions. CoRR Sourav Sanyal, Kaushik Roy
2024	J	`jnl`	AdaGossip: Adaptive Consensus Step-size for Decentralized Deep Learning with Communication Compression. CoRR Sai Aparna Aketi, Abolfazl Hashemi, Kaushik Roy
2024	J	`jnl`	Advancing Compressed Video Action Recognition through Progressive Knowledge Distillation. CoRR Efstathia Soufleri, Deepak Ravikumar, Kaushik Roy
2024	J	`jnl`	Algorithm Hardware Co-Design for ADC-Less Compute In-Memory Accelerator. IEEE Trans. Circuits Syst. Artif. Intell. Shubham Negi, Utkarsh Saxena, Deepika Sharma, Jeffry Victor, Imtiaz Ahmed, Sumeet Kumar Gupta, Kaushik Roy
2024	J	`jnl`	Approximate ADCs for In-Memory Computing. CoRR Arkapravo Ghosh, Hemkar Reddy Sadana, Mukut Debnath, Panthadip Maji, Shubham Negi, Sumeet Gupta, Mrigank Sharad, Kaushik Roy
2024	—	`conf`	Averaging Rate Scheduler for Decentralized Learning on Heterogeneous Data. Tiny Papers @ ICLR Sai Aparna Aketi, Sakshi Choudhary, Kaushik Roy
2024	J	`jnl`	Averaging Rate Scheduler for Decentralized Learning on Heterogeneous Data. CoRR Sai Aparna Aketi, Sakshi Choudhary, Kaushik Roy
2024	A	`conf`	Best of Both Worlds: Hybrid SNN-ANN Architecture for Event-based Optical Flow Estimation. IROS Shubham Negi, Deepika Sharma, Adarsh Kumar Kosta, Kaushik Roy
2024	J	`jnl`	Brain-Inspired Computing: A Systematic Survey and Future Trends. Proc. IEEE Guoqi Li, Lei Deng, Huajin Tang, Gang Pan, Yonghong Tian, Kaushik Roy, Wolfgang Maass
2024	J	`jnl`	CODE-CL: COnceptor-Based Gradient Projection for DEep Continual Learning. CoRR Marco Paul E. Apolinario, Kaushik Roy
2024	J	`jnl`	CoDeC: Communication-Efficient Decentralized Continual Learning. Trans. Mach. Learn. Res. Sakshi Choudhary, Sai Aparna Aketi, Gobinda Saha, Kaushik Roy
2024	J	`jnl`	Continual Learning: A Review of Techniques, Challenges, and Future Directions. IEEE Trans. Artif. Intell. Buddhi Wickramasinghe, Gobinda Saha, Kaushik Roy
2024	J	`jnl`	Corrections to "Brain-Inspired Computing: A Systematic Survey and Future Trends". Proc. IEEE Guoqi Li, Lei Deng, Huajin Tang, Gang Pan, Yonghong Tian, Kaushik Roy, Wolfgang Maass
2024	A	`conf`	Cross-feature Contrastive Loss for Decentralized Deep Learning on Heterogeneous Data. WACV Sai Aparna Aketi, Kaushik Roy
2024	A*	`conf`	Curvature Clues: Decoding Deep Learning Privacy with Input Loss Curvature. NeurIPS Deepak Ravikumar, Efstathia Soufleri, Kaushik Roy
2024	J	`jnl`	Curvature Clues: Decoding Deep Learning Privacy with Input Loss Curvature. CoRR Deepak Ravikumar, Efstathia Soufleri, Kaushik Roy
2024	J	`jnl`	DCT-CryptoNets: Scaling Private Inference in the Frequency Domain. CoRR Arjun Roy, Kaushik Roy
2024	J	`jnl`	DP-ImgSyn: Dataset Alignment for Obfuscated, Differentially Private Image Synthesis. Trans. Mach. Learn. Res. Efstathia Soufleri, Deepak Ravikumar, Kaushik Roy
2024	J	`jnl`	Deep Unlearning: Fast and Efficient Gradient-free Class Forgetting. Trans. Mach. Learn. Res. Sangamesh Kodge, Gobinda Saha, Kaushik Roy
2024	J	`jnl`	EV-Planner: Energy-Efficient Robot Navigation via Event-Based Physics-Guided Neuromorphic Planner. IEEE Robotics Autom. Lett. Sourav Sanyal, Rohan Kumar Manna, Kaushik Roy
2024	J	`jnl`	Editorial: Understanding and bridging the gap between neuromorphic computing and machine learning, volume II. Frontiers Comput. Neurosci. Lei Deng, Huajin Tang, Kaushik Roy
2024	—	`conf`	Eigen Attention: Attention in Low-Rank Space for KV Cache Compression. EMNLP (Findings) Utkarsh Saxena, Gobinda Saha, Sakshi Choudhary, Kaushik Roy
2024	J	`jnl`	Eigen Attention: Attention in Low-Rank Space for KV Cache Compression. CoRR Utkarsh Saxena, Gobinda Saha, Sakshi Choudhary, Kaushik Roy
2024	J	`jnl`	Encoding Hierarchical Information in Neural Networks Helps in Subpopulation Shift. IEEE Trans. Artif. Intell. Amitangshu Mukherjee, Isha Garg, Kaushik Roy
2024	A	`conf`	Energy Efficiency Through In-Sensor Computing: ADC-less Real-Time Sensing for Image Edge Detection. ISLPED Nirmoy Modak, Kaushik Roy
2024	A*	`conf`	Ev-Edge: Efficient Execution of Event-based Vision Algorithms on Commodity Edge Platforms. DAC Shrihari Sridharan, Surya Selvam, Kaushik Roy, Anand Raghunathan
2024	J	`jnl`	Ev-Edge: Efficient Execution of Event-based Vision Algorithms on Commodity Edge Platforms. CoRR Shrihari Sridharan, Surya Selvam, Kaushik Roy, Anand Raghunathan
2024	A	`conf`	FEDORA: A Flying Event Dataset fOr Reactive behAvior. IROS Amogh Joshi, Wachirawit Ponghiran, Adarsh Kosta, Manish Nagaraj, Kaushik Roy
2024	J	`jnl`	Guest Editorial: Special Issue on Advancing Machine Intelligence With Neuromorphic Computing. IEEE Trans. Cogn. Dev. Syst. Guoqi Li, Emre Neftci, Rong Xiao, Pablo Lanillos, Kaushik Roy
2024	A	`conf`	HALSIE: Hybrid Approach to Learning Segmentation by Simultaneously Exploiting Image and Event Modalities. WACV Shristi Das Biswas, Adarsh Kosta, Chamika M. Liyanagedera, Marco Paul E. Apolinario, Kaushik Roy
2024	J	`jnl`	HCiM: ADC-Less Hybrid Analog-Digital Compute in Memory Accelerator for Deep Learning Workloads. CoRR Shubham Negi, Utkarsh Saxena, Deepika Sharma, Kaushik Roy
2024	J	`jnl`	Hardware/Software Co-Design With ADC-Less In-Memory Computing Hardware for Spiking Neural Networks. IEEE Trans. Emerg. Top. Comput. Marco Paul E. Apolinario, Adarsh Kumar Kosta, Utkarsh Saxena, Kaushik Roy
2024	J	`jnl`	Homogenizing Non-IID Datasets via In-Distribution Knowledge Distillation for Decentralized Learning. Trans. Mach. Learn. Res. Deepak Ravikumar, Gobinda Saha, Sai Aparna Aketi, Kaushik Roy
2024	J	`jnl`	LITE-SNN: Leveraging Inherent Dynamics to Train Energy-Efficient Spiking Neural Networks for Sequential Learning. IEEE Trans. Cogn. Dev. Syst. Nitin Rathi, Kaushik Roy
2024	J	`jnl`	LLS: Local Learning Rule for Deep Neural Networks Inspired by Neural Activity Synchronization. CoRR Marco Paul E. Apolinario, Arani Roy, Kaushik Roy
2024	A*	`conf`	Memorization Through the Lens of Curvature of Loss Function Around Samples. ICML Isha Garg, Deepak Ravikumar, Kaushik Roy
2024	A*	`conf`	OPEL: Optimal Transport Guided ProcedurE Learning. NeurIPS Sayeed Shafayet Chowdhury, Soumyadeep Chandra, Kaushik Roy
2024	J	`jnl`	On Inherent Adversarial Robustness of Active Vision Systems. CoRR Amitangshu Mukherjee, Timur Ibrayev, Kaushik Roy
2024	J	`jnl`	Power side-channel leakage localization through adversarial training of deep neural networks. CoRR Jimmy Gammell, Anand Raghunathan, Kaushik Roy
2024	—	`conf`	Prompt-Based Bias Calibration for Better Zero/Few-Shot Learning of Language Models. EMNLP (Findings) Kang He, Yinghan Long, Kaushik Roy
2024	J	`jnl`	Prompt-Based Bias Calibration for Better Zero/Few-Shot Learning of Language Models. CoRR Kang He, Yinghan Long, Kaushik Roy
2024	J	`jnl`	Pruning for Improved ADC Efficiency in Crossbar-based Analog In-memory Accelerators. CoRR Timur Ibrayev, Isha Garg, Indranil Chakraborty, Kaushik Roy
2024	J	`jnl`	Real-Time Neuromorphic Navigation: Integrating Event-Based Vision and Physics-Driven Planning on a Parrot Bebop2 Quadrotor. CoRR Amogh Joshi, Sourav Sanyal, Kaushik Roy
2024	J	`jnl`	ResQ: Mixed-Precision Quantization of Large Language Models with Low-Rank Residuals. CoRR Utkarsh Saxena, Sayeh Sharify, Kaushik Roy, Xin Wang
2024	J	`jnl`	Roadmap to Neuromorphic Computing with Emerging Technologies. CoRR Adnan Mehonic, Daniele Ielmini, Kaushik Roy, Onur Mutlu, Shahar Kvatinsky, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco, Sabina Spiga, Sergey Savelev, Alexander G. Balanov, Nitin Chawla, Giuseppe Desoli, Gerardo Malavena, Christian Monzio Compagnoni, Zhongrui Wang, J. Joshua Yang, Syed Ghazi Sarwat, Abu Sebastian, Thomas Mikolajick, Beatriz Noheda, Stefan Slesazeck, Bernard Dieny, Tuo-Hung Hou, Akhil Varri, Frank Brückerhoff-Plückelmann, Wolfram H. P. Pernice, Xixiang Zhang, Sebastian Pazos, Mario Lanza, Stefan Wiefels, Regina Dittmann, Wing H. Ng, Mark Buckwell, Horatio Cox, Daniel J. Mannion, Anthony J. Kenyon, Yingming Lu, Yuchao Yang, Damien Querlioz, Louis Hutin, Elisa Vianello, Sayeed Shafayet Chowdhury, Piergiulio Mannocci, Yimao Cai, Zhong Sun, Giacomo Pedretti, John Paul Strachan, Dmitri B. Strukov, Manuel Le Gallo, Stefano Ambrogio, Ilia Valov, Rainer Waser
2024	J	`jnl`	SADDLe: Sharpness-Aware Decentralized Deep Learning with Heterogeneous Data. CoRR Sakshi Choudhary, Sai Aparna Aketi, Kaushik Roy
2024	J	`jnl`	SHIRE: Enhancing Sample Efficiency using Human Intuition in REinforcement Learning. CoRR Amogh Joshi, Adarsh Kumar Kosta, Kaushik Roy
2024	J	`jnl`	SWANN: Shuffling Weights in Crossbar Arrays for Enhanced DNN Accuracy in Deeply Scaled Technologies. CoRR Jeffry Victor, Dong Eun Kim, Chunguang Wang, Kaushik Roy, Sumeet Gupta
2024	J	`jnl`	SpiDR: A Reconfigurable Digital Compute-in-Memory Spiking Neural Network Accelerator for Event-based Perception. CoRR Deepika Sharma, Shubham Negi, Trishit Dutta, Amogh Agrawal, Kaushik Roy
2024	J	`jnl`	TOFU: Toward Obfuscated Federated Updates by Encoding Weight Updates Into Gradients From Proxy Data. IEEE Access Manish Nagaraj, Isha Garg, Kaushik Roy
2024	J	`jnl`	TSkips: Efficiency Through Explicit Temporal Delay Connections in Spiking Neural Networks. CoRR Prajna G. Malettira, Shubham Negi, Wachirawit Ponghiran, Kaushik Roy
2024	J	`jnl`	Toward Two-Stream Foveation-Based Active Vision Learning. IEEE Trans. Cogn. Dev. Syst. Timur Ibrayev, Amitangshu Mukherjee, Sai Aparna Aketi, Kaushik Roy
2024	J	`jnl`	Toward Visual Syntactical Understanding. IEEE Access Sayeed Shafayet Chowdhury, Soumyadeep Chandra, Kaushik Roy
2024	J	`jnl`	Towards Image Semantics and Syntax Sequence Learning. CoRR Chun Tao, Timur Ibrayev, Kaushik Roy
2024	J	`jnl`	Towards Two-Stream Foveation-based Active Vision Learning. CoRR Timur Ibrayev, Amitangshu Mukherjee, Sai Aparna Aketi, Kaushik Roy
2024	J	`jnl`	Towards Visual Syntactical Understanding. CoRR Sayeed Shafayet Chowdhury, Soumyadeep Chandra, Kaushik Roy
2024	A	`conf`	Unearthing the Potential of Spiking Neural Networks. DATE Sayeed Shafayet Chowdhury, Adarsh Kumar Kosta, Deepika Sharma, Marco Paul E. Apolinario, Kaushik Roy
2024	J	`jnl`	Unlocking the Potential of Spiking Neural Networks: Understanding the What, Why, and Where. IEEE Trans. Cogn. Dev. Syst. Buddhi Wickramasinghe, Sayeed Shafayet Chowdhury, Adarsh Kumar Kosta, Wachirawit Ponghiran, Kaushik Roy
2024	A*	`conf`	Unveiling Privacy, Memorization, and Input Curvature Links. ICML Deepak Ravikumar, Efstathia Soufleri, Abolfazl Hashemi, Kaushik Roy
2024	J	`jnl`	Unveiling Privacy, Memorization, and Input Curvature Links. CoRR Deepak Ravikumar, Efstathia Soufleri, Abolfazl Hashemi, Kaushik Roy
2024	J	`jnl`	Verifix: Post-Training Correction to Improve Label Noise Robustness with Verified Samples. CoRR Sangamesh Kodge, Deepak Ravikumar, Gobinda Saha, Kaushik Roy
2024	J	`jnl`	ViTALS: Vision Transformer for Action Localization in Surgical Nephrectomy. CoRR Soumyadeep Chandra, Sayeed Shafayet Chowdhury, Courtney Yong, Chandru P. Sundaram, Kaushik Roy
2023	—	`conf`	A 65 nm 1.4-6.7 TOPS/W Adaptive-SNR Sparsity-Aware CIM Core with Load Balancing Support for DL workloads. CICC Mustafa Fayez Ali, Indranil Chakraborty, Sakshi Choudhary, Muya Chang, Dong Eun Kim, Arijit Raychowdhury, Kaushik Roy
2023	A*	`conf`	Adaptive-SpikeNet: Event-based Optical Flow Estimation using Spiking Neural Networks with Learnable Neuronal Dynamics. ICRA Adarsh Kumar Kosta, Kaushik Roy
2023	J	`jnl`	Best of Both Worlds: Hybrid SNN-ANN Architecture for Event-based Optical Flow Estimation. CoRR Shubham Negi, Deepika Sharma, Adarsh Kumar Kosta, Kaushik Roy
2023	J	`jnl`	CoDeC: Communication-Efficient Decentralized Continual Learning. CoRR Sakshi Choudhary, Sai Aparna Aketi, Gobinda Saha, Kaushik Roy
2023	A*	`conf`	Continual Learning with Scaled Gradient Projection. AAAI Gobinda Saha, Kaushik Roy
2023	J	`jnl`	Continual Learning with Scaled Gradient Projection. CoRR Gobinda Saha, Kaushik Roy
2023	J	`jnl`	Cross-feature Contrastive Loss for Decentralized Deep Learning on Heterogeneous Data. CoRR Sai Aparna Aketi, Kaushik Roy
2023	J	`jnl`	DIET-SNN: A Low-Latency Spiking Neural Network With Direct Input Encoding and Leakage and Threshold Optimization. IEEE Trans. Neural Networks Learn. Syst. Nitin Rathi, Kaushik Roy
2023	A*	`conf`	DOTIE - Detecting Objects through Temporal Isolation of Events using a Spiking Architecture. ICRA Manish Nagaraj, Chamika Mihiranga Liyanagedera, Kaushik Roy
2023	J	`jnl`	Deep Unlearning: Fast and Efficient Training-free Approach to Controlled Forgetting. CoRR Sangamesh Kodge, Gobinda Saha, Kaushik Roy
2023	J	`jnl`	EV-Planner: Energy-Efficient Robot Navigation via Event-Based Physics-Guided Neuromorphic Planner. CoRR Sourav Sanyal, Rohan Kumar Manna, Kaushik Roy
2023	A*	`conf`	Event-based Temporally Dense Optical Flow Estimation with Sequential Learning. ICCV Wachirawit Ponghiran, Chamika Mihiranga Liyanagedera, Kaushik Roy
2023	—	`conf`	Exploring Foveation and Saccade for Improved Weakly-Supervised Localization. Gaze Meets ML Timur Ibrayev, Manish Nagaraj, Amitangshu Mukherjee, Kaushik Roy
2023	J	`jnl`	Exploring Neuromorphic Computing Based on Spiking Neural Networks: Algorithms to Hardware. ACM Comput. Surv. Nitin Rathi, Indranil Chakraborty, Adarsh Kosta, Abhronil Sengupta, Aayush Ankit, Priyadarshini Panda, Kaushik Roy
2023	J	`jnl`	FEDORA: Flying Event Dataset fOr Reactive behAvior. CoRR Amogh Joshi, Adarsh Kosta, Wachirawit Ponghiran, Manish Nagaraj, Kaushik Roy
2023	A*	`conf`	Global Update Tracking: A Decentralized Learning Algorithm for Heterogeneous Data. NeurIPS Sai Aparna Aketi, Abolfazl Hashemi, Kaushik Roy
2023	J	`jnl`	Global Update Tracking: A Decentralized Learning Algorithm for Heterogeneous Data. CoRR Sai Aparna Aketi, Abolfazl Hashemi, Kaushik Roy
2023	J	`jnl`	Homogenizing Non-IID datasets via In-Distribution Knowledge Distillation for Decentralized Learning. CoRR Deepak Ravikumar, Gobinda Saha, Sai Aparna Aketi, Kaushik Roy
2023	J	`jnl`	Intra-Class Mixup for Out-of-Distribution Detection. IEEE Access Deepak Ravikumar, Sangamesh Kodge, Isha Garg, Kaushik Roy
2023	A*	`conf`	Lightning Talk: A Perspective on Neuromorphic Computing. DAC Deepika Sharma, Adarsh Kumar Kosta, Kaushik Roy
2023	—	`conf`	Live Demonstration: ANN vs SNN vs Hybrid Architectures for Event-based Real-time Gesture Recognition and Optical Flow Estimation. CVPR Workshops Adarsh Kumar Kosta, Marco Paul E. Apolinario, Kaushik Roy
2023	—	`conf`	Live Demonstration: Real-time Event-based Speed Detection using Spiking Neural Networks. CVPR Workshops Arjun Roy, Manish Nagaraj, Chamika Mihiranga Liyanagedera, Kaushik Roy
2023	C	`conf`	Low-Power Real-Time Sequential Processing with Spiking Neural Networks. ISCAS Chamika Mihiranga Liyanagedera, Manish Nagaraj, Wachirawit Ponghiran, Kaushik Roy
2023	A	`conf`	McQueen: Mixed Precision Quantization of Early Exit Networks. BMVC Utkarsh Saxena, Kaushik Roy
2023	J	`jnl`	Memorization Through the Lens of Curvature of Loss Function Around Samples. CoRR Isha Garg, Kaushik Roy
2023	J	`jnl`	Neighborhood Gradient Mean: An Efficient Decentralized Learning Method for Non-IID Data. Trans. Mach. Learn. Res. Sai Aparna Aketi, Sangamesh Kodge, Kaushik Roy
2023	J	`jnl`	Online continual learning with saliency-guided experience replay using tiny episodic memory. Mach. Vis. Appl. Gobinda Saha, Kaushik Roy
2023	A	`conf`	Partial-Sum Quantization for Near ADC-Less Compute-In-Memory Accelerators. ISLPED Utkarsh Saxena, Kaushik Roy
2023	A*	`conf`	RAMP-Net: A Robust Adaptive MPC for Quadrotors via Physics-informed Neural Network. ICRA Sourav Sanyal, Kaushik Roy
2023	J	`jnl`	Roadmap for Unconventional Computing with Nanotechnology. CoRR Giovanni Finocchio, Supriyo Bandyopadhyay, Peng Lin, Gang Pan, J. Joshua Yang, Riccardo Tomasello, Christos Panagopoulos, Mario Carpentieri, Vito Puliafito, Johan Åkerman, Hiroki Takesue, Amit Ranjan Trivedi, Saibal Mukhopadhyay, Kaushik Roy, Vinod K. Sangwan, Mark C. Hersam, Anna Giordano, Huynsoo Yang, Julie Grollier, Kerem Yunus Çamsari, Peter L. McMahon, Supriyo Datta, Jean Anne C. Incorvia, Joseph S. Friedman, Sorin Cotofana, Florin Ciubotaru, Andrii V. Chumak, Azad J. Naeemi, Brajesh Kumar Kaushik, Yao Zhu, Wang Kang, Belita Koiller, Gabriel Aguilar, Guilherme P. Temporão, Kremena Makasheva, Aida Todri-Sanial, Jennifer Hasler, William Levy, Vwani Roychowdhury, Samiran Ganguly, Avik W. Ghosh, Davi Rodriquez, Satoshi Sunada, Karin Everschor-Sitte, Amit Lal, Shubham Jadhav, Massimiliano Di Ventra, Yuriy V. Pershin, Kosuke Tatsumura, Hayato Goto
2023	J	`jnl`	S-TLLR: STDP-inspired Temporal Local Learning Rule for Spiking Neural Networks. CoRR Marco Paul E. Apolinario, Kaushik Roy
2023	J	`jnl`	SAMBA: Sparsity Aware In-Memory Computing Based Machine Learning Accelerator. IEEE Trans. Computers Dong Eun Kim, Aayush Ankit, Cheng Wang, Kaushik Roy
2023	A	`conf`	Saliency Guided Experience Packing for Replay in Continual Learning. WACV Gobinda Saha, Kaushik Roy
2023	A*	`conf`	Samples with Low Loss Curvature Improve Data Efficiency. CVPR Isha Garg, Kaushik Roy
2023	—	`conf`	Segmented Recurrent Transformer: An Efficient Sequence-to-Sequence Model. EMNLP (Findings) Yinghan Long, Sayeed Shafayet Chowdhury, Kaushik Roy
2023	J	`jnl`	Segmented Recurrent Transformer: An Efficient Sequence-to-Sequence Model. CoRR Yinghan Long, Sayeed Shafayet Chowdhury, Kaushik Roy
2023	J	`jnl`	TREND: Transferability-Based Robust ENsemble Design. IEEE Trans. Artif. Intell. Deepak Ravikumar, Sangamesh Kodge, Isha Garg, Kaushik Roy
2023	J	`jnl`	WWW: What, When, Where to Compute-in-Memory. CoRR Tanvi Sharma, Mustafa Fayez Ali, Indranil Chakraborty, Kaushik Roy
2023	J	`jnl`	X-Former: In-Memory Acceleration of Transformers. CoRR Shrihari Sridharan, Jacob R. Stevens, Kaushik Roy, Anand Raghunathan
2023	J	`jnl`	X-Former: In-Memory Acceleration of Transformers. IEEE Trans. Very Large Scale Integr. Syst. Shrihari Sridharan, Jacob R. Stevens, Kaushik Roy, Anand Raghunathan
2022	J	`jnl`	A Co-design view of Compute in-Memory with Non-Volatile Elements for Neural Networks. CoRR Wilfried Haensch, Anand Raghunathan, Kaushik Roy, Bhaswar Chakrabarti, Charudatta M. Phatak, Cheng Wang, Supratik Guha
2022	A*	`conf`	A cross-layer approach to cognitive computing: invited. DAC Gobinda Saha, Cheng Wang, Anand Raghunathan, Kaushik Roy
2022	J	`jnl`	Adaptive-SpikeNet: Event-based Optical Flow Estimation using Spiking Neural Networks with Learnable Neuronal Dynamics. CoRR Adarsh Kumar Kosta, Kaushik Roy
2022	J	`jnl`	All-Electric Nonassociative Learning in Nickel Oxide. Adv. Intell. Syst. Sandip Mondal, Zhen Zhang, A. N. M. Nafiul Islam, Robert Andrawis, Sampath Gamage, Neda Alsadat Aghamiri, Qi Wang, Hua Zhou, Fanny Rodolakis, Richard Tran, Jasleen Kaur, Chi Chen, Shyue Ping Ong, Abhronil Sengupta, Yohannes Abate, Kaushik Roy, Shriram Ramanathan
2022	—	`ch.`	Approximate Computing for Machine Learning Workloads: A Circuits and Systems Perspective. Approximate Computing Sourav Sanyal, Shubham Negi, Anand Raghunathan, Kaushik Roy
2022	J	`jnl`	Compute-in-Memory Technologies and Architectures for Deep Learning Workloads. IEEE Trans. Very Large Scale Integr. Syst. Mustafa Fayez Ali, Sourjya Roy, Utkarsh Saxena, Tanvi Sharma, Anand Raghunathan, Kaushik Roy
2022	J	`jnl`	Cryogenic Neuromorphic Hardware. CoRR Md. Mazharul Islam, Shamiul Alam, Md. Shafayat Hossain, Kaushik Roy, Ahmedullah Aziz
2022	J	`jnl`	DOTIE - Detecting Objects through Temporal Isolation of Events using a Spiking Architecture. CoRR Manish Nagaraj, Chamika Mihiranga Liyanagedera, Kaushik Roy
2022	A	`conf`	Design Space and Memory Technology Co-Exploration for In-Memory Computing Based Machine Learning Accelerators. ICCAD Kang He, Indranil Chakraborty, Cheng Wang, Kaushik Roy
2022	A*	`conf`	Efficiency attacks on spiking neural networks. DAC Sarada Krithivasan, Sanchari Sen, Nitin Rathi, Kaushik Roy, Anand Raghunathan
2022	J	`jnl`	Event-based Temporally Dense Optical Flow Estimation with Sequential Neural Networks. CoRR Wachirawit Ponghiran, Chamika Mihiranga Liyanagedera, Kaushik Roy
2022	A*	`conf`	Fusion-FlowNet: Energy-Efficient Optical Flow Estimation using Sensor Fusion and Deep Fused Spiking-Analog Network Architectures. ICRA Chankyu Lee, Adarsh Kumar Kosta, Kaushik Roy
2022	J	`jnl`	HALSIE - Hybrid Approach to Learning Segmentation by Simultaneously Exploiting Image and Event Modalities. CoRR Shristi Das Biswas, Adarsh Kosta, Chamika M. Liyanagedera, Marco Paul E. Apolinario, Kaushik Roy
2022	J	`jnl`	Hardware/Software co-design with ADC-Less In-memory Computing Hardware for Spiking Neural Networks. CoRR Marco Paul E. Apolinario, Adarsh Kumar Kosta, Utkarsh Saxena, Kaushik Roy
2022	A	`conf`	HyperX: A Hybrid RRAM-SRAM partitioned system for error recovery in memristive Xbars. DATE Adarsh Kosta, Efstathia Soufleri, Indranil Chakraborty, Amogh Agrawal, Aayush Ankit, Kaushik Roy
2022	A	`conf`	Identifying Efficient Dataflows for Spiking Neural Networks. ISLPED Deepika Sharma, Aayush Ankit, Kaushik Roy
2022	—	`conf`	In-Memory Computing based Machine Learning Accelerators: Opportunities and Challenges. ACM Great Lakes Symposium on VLSI Kaushik Roy
2022	J	`jnl`	Low precision decentralized distributed training over IID and non-IID data. Neural Networks Sai Aparna Aketi, Sangamesh Kodge, Kaushik Roy
2022	A*	`conf`	NAX: neural architecture and memristive xbar based accelerator co-design. DAC Shubham Negi, Indranil Chakraborty, Aayush Ankit, Kaushik Roy
2022	J	`jnl`	Neighborhood Gradient Clustering: An Efficient Decentralized Learning Method for Non-IID Data Distributions. CoRR Sai Aparna Aketi, Sangamesh Kodge, Kaushik Roy
2022	J	`jnl`	Neuro-Ising: Accelerating Large-Scale Traveling Salesman Problems via Graph Neural Network Guided Localized Ising Solvers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sourav Sanyal, Kaushik Roy
2022	J	`jnl`	Norm-Scaling for Out-of-Distribution Detection. CoRR Deepak Ravikumar, Kaushik Roy
2022	J	`jnl`	On Noise Stability and Robustness of Adversarially Trained Networks on NVM Crossbars. IEEE Trans. Very Large Scale Integr. Syst. Chun Tao, Deboleena Roy, Indranil Chakraborty, Kaushik Roy
2022	A*	`conf`	Oscillatory Fourier Neural Network: A Compact and Efficient Architecture for Sequential Processing. AAAI Bing Han, Cheng Wang, Kaushik Roy
2022	J	`jnl`	RAMP-Net: A Robust Adaptive MPC for Quadrotors via Physics-informed Neural Network. CoRR Sourav Sanyal, Kaushik Roy
2022	A*	`conf`	RAPID-RL: A Reconfigurable Architecture with Preemptive-Exits for Efficient Deep-Reinforcement Learning. ICRA Adarsh Kumar Kosta, Malik Aqeel Anwar, Priyadarshini Panda, Arijit Raychowdhury, Kaushik Roy
2022	A*	`conf`	Spiking Neural Networks with Improved Inherent Recurrence Dynamics for Sequential Learning. AAAI Wachirawit Ponghiran, Kaushik Roy
2022	J	`jnl`	TOFU: Towards Obfuscated Federated Updates by Encoding Weight Updates into Gradients from Proxy Data. CoRR Isha Garg, Manish Nagaraj, Kaushik Roy
2022	A	`conf`	Towards ADC-Less Compute-In-Memory Accelerators for Energy Efficient Deep Learning. DATE Utkarsh Saxena, Indranil Chakraborty, Kaushik Roy
2022	—	`conf`	Towards Ultra Low Latency Spiking Neural Networks for Vision and Sequential Tasks Using Temporal Pruning. ECCV (11) Sayeed Shafayet Chowdhury, Nitin Rathi, Kaushik Roy
2021	—	`conf`	Accurate and Accelerated Neuromorphic Network Design Leveraging A Bayesian Hyperparameter Pareto Optimization Approach. ICONS Maryam Parsa, Catherine D. Schuman, Nitin Rathi, Amirkoushyar Ziabari, Derek C. Rose, J. Parker Mitchell, J. Travis Johnston, Bill Kay, Steven R. Young, Kaushik Roy
2021	J	`jnl`	BERMo: What can BERT learn from ELMo? CoRR Sangamesh Kodge, Kaushik Roy
2021	A	`conf`	Brain-Inspired Computing: Adventure from Beyond CMOS Technologies to Beyond von Neumann Architectures ICCAD Special Session Paper. ICCAD Hussam Amrouch, Jian-Jia Chen, Kaushik Roy, Yuan Xie, Indranil Chakraborty, Wenqin Huangfu, Ling Liang, Fengbin Tu, Cheng Wang, Mikail Yayla
2021	A	`conf`	Complexity-aware Adaptive Training and Inference for Edge-Cloud Distributed AI Systems. ICDCS Yinghan Long, Indranil Chakraborty, Gopalakrishnan Srinivasan, Kaushik Roy
2021	J	`jnl`	Complexity-aware Adaptive Training and Inference for Edge-Cloud Distributed AI Systems. CoRR Yinghan Long, Indranil Chakraborty, Gopalakrishnan Srinivasan, Kaushik Roy
2021	A*	`conf`	DCT-SNN: Using DCT to Distribute Spatial Information over Time for Low-Latency Spiking Neural Networks. ICCV Isha Garg, Sayeed Shafayet Chowdhury, Kaushik Roy
2021	J	`jnl`	Editorial: Understanding and Bridging the Gap Between Neuromorphic Computing and Machine Learning. Frontiers Comput. Neurosci. Lei Deng, Huajin Tang, Kaushik Roy
2021	J	`jnl`	Embracing Stochasticity to Enable Neuromorphic Computing at the Edge. IEEE Des. Test Amogh Agrawal, Deboleena Roy, Utkarsh Saxena, Kaushik Roy
2021	A	`conf`	Enabling Robust SOT-MTJ Crossbars for Machine Learning using Sparsity-Aware Device-Circuit Co-design. ISLPED Tanvi Sharma, Cheng Wang, Amogh Agrawal, Kaushik Roy
2021	J	`jnl`	Encoding Hierarchical Information in Neural Networks helps in Subpopulation Shift. CoRR Amitangshu Mukherjee, Isha Garg, Kaushik Roy
2021	A	`conf`	Exploring Spike-Based Learning for Neuromorphic Computing: Prospects and Perspectives. DATE Nitin Rathi, Amogh Agrawal, Chankyu Lee, Adarsh Kumar Kosta, Kaushik Roy
2021	J	`jnl`	Fusion-FlowNet: Energy-Efficient Optical Flow Estimation using Sensor Fusion and Deep Fused Spiking-Analog Network Architectures. CoRR Chankyu Lee, Adarsh Kumar Kosta, Kaushik Roy
2021	A*	`conf`	Gradient Projection Memory for Continual Learning. ICLR Gobinda Saha, Isha Garg, Kaushik Roy
2021	J	`jnl`	Gradient Projection Memory for Continual Learning. CoRR Gobinda Saha, Isha Garg, Kaushik Roy
2021	A	`conf`	Hybrid Analog-Spiking Long Short-Term Memory for Energy Efficient Computing on Edge Devices. DATE Wachirawit Ponghiran, Kaushik Roy
2021	J	`jnl`	IMPULSE: A 65nm Digital Compute-in-Memory Macro with Fused Weights and Membrane Potential for Spike-based Sequential Learning Tasks. CoRR Amogh Agrawal, Mustafa Fayez Ali, Minsuk Koo, Nitin Rathi, Akhilesh Jaiswal, Kaushik Roy
2021	J	`jnl`	Implicit adversarial data augmentation and robustness with Noise-based Learning. Neural Networks Priyadarshini Panda, Kaushik Roy
2021	J	`jnl`	L4-Norm Weight Adjustments for Converted Spiking Neural Networks. CoRR Jason M. Allred, Kaushik Roy
2021	J	`jnl`	Low Precision Decentralized Distributed Training with Heterogeneous Data. CoRR Sai Aparna Aketi, Sangamesh Kodge, Kaushik Roy
2021	J	`jnl`	Magnetoresistive Circuits and Systems: Embedded Non-Volatile Memory to Crossbar Arrays. IEEE Trans. Circuits Syst. I Regul. Pap. Amogh Agrawal, Cheng Wang, Tanvi Sharma, Kaushik Roy
2021	—	`conf`	Mixed Precision Quantization for ReRAM-based DNN Inference Accelerators. ASP-DAC Sitao Huang, Aayush Ankit, Plínio Silveira, Rodrigo Antunes, Sai Rahul Chalamalasetti, Izzat El Hajj, Dong Eun Kim, Glaucimar Aguiar, Pedro Bruel, Sergey Serebryakov, Cong Xu, Can Li, Paolo Faraboschi, John Paul Strachan, Deming Chen, Kaushik Roy, Wen-mei W. Hwu, Dejan S. Milojicic
2021	J	`jnl`	NAX: Co-Designing Neural Network and Hardware Architecture for Memristive Xbar based Computing Systems. CoRR Shubham Negi, Indranil Chakraborty, Aayush Ankit, Kaushik Roy
2021	J	`jnl`	Network Compression via Mixed Precision Quantization Using a Multi-Layer Perceptron for the Bit-Width Allocation. IEEE Access Efstathia Soufleri, Kaushik Roy
2021	A*	`conf`	On the Intrinsic Robustness of NVM Crossbars Against Adversarial Attacks. DAC Deboleena Roy, Indranil Chakraborty, Timur Ibrayev, Kaushik Roy
2021	J	`jnl`	On the Noise Stability and Robustness of Adversarially Trained Networks on NVM Crossbars. CoRR Deboleena Roy, Chun Tao, Indranil Chakraborty, Kaushik Roy
2021	J	`jnl`	One Timestep is All You Need: Training Spiking Neural Networks with Ultra Low Latency. CoRR Sayeed Shafayet Chowdhury, Nitin Rathi, Kaushik Roy
2021	J	`jnl`	Oscillatory Fourier Neural Network: A Compact and Efficient Architecture for Sequential Processing. CoRR Bing Han, Cheng Wang, Kaushik Roy
2021	J	`jnl`	Quantifying the Brain Predictivity of Artificial Neural Networks With Nonlinear Response Mapping. Frontiers Comput. Neurosci. Aditi Anand, Sanchari Sen, Kaushik Roy
2021	J	`jnl`	RAPID-RL: A Reconfigurable Architecture with Preemptive-Exits for Efficient Deep-Reinforcement Learning. CoRR Adarsh Kumar Kosta, Malik Aqeel Anwar, Priyadarshini Panda, Arijit Raychowdhury, Kaushik Roy
2021	J	`jnl`	RxNN: A Framework for Evaluating Deep Neural Networks on Resistive Crossbars. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shubham Jain, Abhronil Sengupta, Kaushik Roy, Anand Raghunathan
2021	J	`jnl`	SPACE: Structured Compression and Sharing of Representational Space for Continual Learning. IEEE Access Gobinda Saha, Isha Garg, Aayush Ankit, Kaushik Roy
2021	J	`jnl`	STDP Based Unsupervised Multimodal Learning With Cross-Modal Processing in Spiking Neural Networks. IEEE Trans. Emerg. Top. Comput. Intell. Nitin Rathi, Kaushik Roy
2021	J	`jnl`	Saliency Guided Experience Packing for Replay in Continual Learning. CoRR Gobinda Saha, Kaushik Roy
2021	A	`conf`	Self-Supervised Optical Flow with Spiking Neural Networks and Event Based Cameras. IROS Kenneth Chaney, Artemis Panagopoulou, Chankyu Lee, Kaushik Roy, Kostas Daniilidis
2021	B	`conf`	Spatio-Temporal Pruning and Quantization for Low-latency Spiking Neural Networks. IJCNN Sayeed Shafayet Chowdhury, Isha Garg, Kaushik Roy
2021	J	`jnl`	Spatio-Temporal Pruning and Quantization for Low-latency Spiking Neural Networks. CoRR Sayeed Shafayet Chowdhury, Isha Garg, Kaushik Roy
2021	J	`jnl`	Spiking Neural Networks with Improved Inherent Recurrence Dynamics for Sequential Learning. CoRR Wachirawit Ponghiran, Kaushik Roy
2021	J	`jnl`	Towards understanding the effect of leak in Spiking Neural Networks. Neurocomputing Sayeed Shafayet Chowdhury, Chankyu Lee, Kaushik Roy
2020	J	`jnl`	A Low Effort Approach to Structured CNN Design Using PCA. IEEE Access Isha Garg, Priyadarshini Panda, Kaushik Roy
2020	J	`jnl`	CASH-RAM: Enabling In-Memory Computations for Edge Inference Using Charge Accumulation and Sharing in Standard 8T-SRAM Arrays. IEEE J. Emerg. Sel. Topics Circuits Syst. Amogh Agrawal, Adarsh Kosta, Sangamesh Kodge, Dong Eun Kim, Kaushik Roy
2020	J	`jnl`	Circuits and Architectures for In-Memory Computing-Based Machine Learning Accelerators. IEEE Micro Aayush Ankit, Indranil Chakraborty, Amogh Agrawal, Mustafa Fayez Ali, Kaushik Roy
2020	J	`jnl`	Conditionally Deep Hybrid Neural Networks Across Edge and Cloud. CoRR Yinghan Long, Indranil Chakraborty, Kaushik Roy
2020	J	`jnl`	Constructing energy-efficient mixed-precision neural networks through principal component analysis for edge intelligence. Nat. Mach. Intell. Indranil Chakraborty, Deboleena Roy, Isha Garg, Aayush Ankit, Kaushik Roy
2020	J	`jnl`	DCT-SNN: Using DCT to Distribute Spatial Information over Time for Learning Low-Latency Spiking Neural Networks. CoRR Isha Garg, Sayeed Shafayet Chowdhury, Kaushik Roy
2020	J	`jnl`	DIET-SNN: Direct Input Encoding With Leakage and Threshold Optimization in Deep Spiking Neural Networks. CoRR Nitin Rathi, Kaushik Roy
2020	—	`conf`	Deep Spiking Neural Network: Energy Efficiency Through Time Based Coding. ECCV (10) Bing Han, Kaushik Roy
2020	J	`jnl`	Dynamic Read Current Sensing With Amplified Bit-Line Voltage for STT-MRAMs. IEEE Trans. Circuits Syst. II Express Briefs Mustafa Fayez Ali, Robert Andrawis, Kaushik Roy
2020	A*	`conf`	Enabling Deep Spiking Neural Networks with Hybrid Conversion and Spike Timing Dependent Backpropagation. ICLR Nitin Rathi, Gopalakrishnan Srinivasan, Priyadarshini Panda, Kaushik Roy
2020	J	`jnl`	Enabling Deep Spiking Neural Networks with Hybrid Conversion and Spike Timing Dependent Backpropagation. CoRR Nitin Rathi, Gopalakrishnan Srinivasan, Priyadarshini Panda, Kaushik Roy
2020	B	`conf`	Enabling Homeostasis using Temporal Decay Mechanisms in Spiking CNNs Trained with Unsupervised Spike Timing Dependent Plasticity. IJCNN Krishna Reddy Kesari, Priyadarshini Panda, Gopalakrishnan Srinivasan, Kaushik Roy
2020	—	`conf`	Energy-Efficient Target Recognition using ReRAM Crossbars for Enabling On-Device Intelligence. SiPS Sourav Sanyal, Aayush Ankit, Craig M. Vineyard, Kaushik Roy
2020	J	`jnl`	Erratum to "CASH-RAM: Enabling In-Memory Computations for Edge Inference Using Charge Accumulation and Sharing in Standard 8T-SRAM Arrays". IEEE J. Emerg. Sel. Topics Circuits Syst. Amogh Agrawal, Adarsh Kosta, Sangamesh Kodge, Dong Eun Kim, Kaushik Roy
2020	J	`jnl`	Explicitly Trained Spiking Sparsity in Spiking Neural Networks with Backpropagation. CoRR Jason M. Allred, Steven J. Spencer, Gopalakrishnan Srinivasan, Kaushik Roy
2020	J	`jnl`	Exploring Vicinal Risk Minimization for Lightweight Out-of-Distribution Detection. CoRR Deepak Ravikumar, Sangamesh Kodge, Isha Garg, Kaushik Roy
2020	J	`jnl`	Functional Read Enabling In-Memory Computations in 1Transistor - 1Resistor Memory Arrays. IEEE Trans. Circuits Syst. Akhilesh Jaiswal, Robert Andrawis, Amogh Agrawal, Kaushik Roy
2020	A*	`conf`	GENIEx: A Generalized Approach to Emulating Non-Ideality in Memristive Xbars using Neural Networks. DAC Indranil Chakraborty, Mustafa Fayez Ali, Dong Eun Kim, Aayush Ankit, Kaushik Roy
2020	J	`jnl`	GENIEx: A Generalized Approach to Emulating Non-Ideality in Memristive Xbars using Neural Networks. CoRR Indranil Chakraborty, Mustafa Fayez Ali, Dong Eun Kim, Aayush Ankit, Kaushik Roy
2020	J	`jnl`	Gradual Channel Pruning While Training Using Feature Relevance Scores for Convolutional Neural Networks. IEEE Access Sai Aparna Aketi, Sourjya Roy, Anand Raghunathan, Kaushik Roy
2020	J	`jnl`	Gradual Channel Pruning while Training using Feature Relevance Scores for Convolutional Neural Networks. CoRR Sai Aparna Aketi, Sourjya Roy, Anand Raghunathan, Kaushik Roy
2020	B	`conf`	Hyperparameter Optimization in Binary Communication Networks for Neuromorphic Deployment. IJCNN Maryam Parsa, Catherine D. Schuman, Prasanna Date, Derek C. Rose, Bill Kay, J. Parker Mitchell, Steven R. Young, Ryan Dellana, William Severa, Thomas E. Potok, Kaushik Roy
2020	J	`jnl`	Hyperparameter Optimization in Binary Communication Networks for Neuromorphic Deployment. CoRR Maryam Parsa, Catherine D. Schuman, Prasanna Date, Derek C. Rose, Bill Kay, J. Parker Mitchell, Steven R. Young, Ryan Dellana, William Severa, Thomas E. Potok, Kaushik Roy
2020	J	`jnl`	IMAC: In-Memory Multi-Bit Multiplication and ACcumulation in 6T SRAM Array. IEEE Trans. Circuits Syst. I Regul. Pap. Mustafa Fayez Ali, Akhilesh Jaiswal, Sangamesh Kodge, Amogh Agrawal, Indranil Chakraborty, Kaushik Roy
2020	J	`jnl`	IMAC: In-memory multi-bit Multiplication andACcumulation in 6T SRAM Array. CoRR Mustafa Fayez Ali, Akhilesh Jaiswal, Sangamesh Kodge, Amogh Agrawal, Indranil Chakraborty, Kaushik Roy
2020	A*	`conf`	In-Memory Computing in Emerging Memory Technologies for Machine Learning: An Overview. DAC Kaushik Roy, Indranil Chakraborty, Mustafa Fayez Ali, Aayush Ankit, Amogh Agrawal
2020	J	`jnl`	In-Memory Low-Cost Bit-Serial Addition Using Commodity DRAM Technology. IEEE Trans. Circuits Syst. I Regul. Pap. Mustafa Fayez Ali, Akhilesh Jaiswal, Kaushik Roy
2020	J	`jnl`	Incremental Learning in Deep Convolutional Neural Networks Using Partial Network Sharing. IEEE Access Syed Shakib Sarwar, Aayush Ankit, Kaushik Roy
2020	J	`jnl`	Inherent Adversarial Robustness of Deep Spiking Neural Networks: Effects of Discrete Input Encoding and Non-Linear Activations. CoRR Saima Sharmin, Nitin Rathi, Priyadarshini Panda, Kaushik Roy
2020	—	`conf`	Inherent Adversarial Robustness of Deep Spiking Neural Networks: Effects of Discrete Input Encoding and Non-linear Activations. ECCV (29) Saima Sharmin, Nitin Rathi, Priyadarshini Panda, Kaushik Roy
2020	—	`conf`	Insulator-Metal Transition Material Based Artificial Neurons: A Design Perspective. ISQED Ahmedullah Aziz, Kaushik Roy
2020	Misc	`conf`	Invited Talk: Re-Engineering Computing with Neuro-Inspired Learning: Devices, Circuits, and Systems. VLSID Priyadarshini Panda, Kaushik Roy
2020	J	`jnl`	Logic Synthesis of Approximate Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Swagath Venkataramani, Vivek Joy Kozhikkottu, Amit Sabne, Kaushik Roy, Anand Raghunathan
2020	J	`jnl`	PANTHER: A Programmable Architecture for Neural Network Training Harnessing Energy-Efficient ReRAM. IEEE Trans. Computers Aayush Ankit, Izzat El Hajj, Sai Rahul Chalamalasetti, Sapan Agarwal, Matthew J. Marinella, Martin Foltin, John Paul Strachan, Dejan S. Milojicic, Wen-Mei Hwu, Kaushik Roy
2020	A	`conf`	RAMANN: in-SRAM differentiable memory computations for memory-augmented neural networks. ISLPED Mustafa Fayez Ali, Amogh Agrawal, Kaushik Roy
2020	A*	`conf`	RMP-SNN: Residual Membrane Potential Neuron for Enabling Deeper High-Accuracy and Low-Latency Spiking Neural Network. CVPR Bing Han, Gopalakrishnan Srinivasan, Kaushik Roy
2020	J	`jnl`	RMP-SNNs: Residual Membrane Potential Neuron for Enabling Deeper High-Accuracy and Low-Latency Spiking Neural Networks. CoRR Bing Han, Gopalakrishnan Srinivasan, Kaushik Roy
2020	J	`jnl`	Relevant-features based Auxiliary Cells for Energy Efficient Detection of Natural Errors. CoRR Sai Aparna Aketi, Priyadarshini Panda, Kaushik Roy
2020	J	`jnl`	Resistive Crossbars as Approximate Hardware Building Blocks for Machine Learning: Opportunities and Challenges. Proc. IEEE Indranil Chakraborty, Mustafa Fayez Ali, Aayush Ankit, Shubham Jain, Sourjya Roy, Shrihari Sridharan, Amogh Agrawal, Anand Raghunathan, Kaushik Roy
2020	J	`jnl`	Revisiting Stochastic Computing in the Era of Nanoscale Nonvolatile Technologies. IEEE Trans. Very Large Scale Integr. Syst. Amogh Agrawal, Indranil Chakraborty, Deboleena Roy, Utkarsh Saxena, Saima Sharmin, Minsuk Koo, Yong Shim, Gopalakrishnan Srinivasan, Chamika M. Liyanagedera, Abhronil Sengupta, Kaushik Roy
2020	J	`jnl`	Robustness Hidden in Plain Sight: Can Analog Computing Defend Against Adversarial Attacks? CoRR Deboleena Roy, Indranil Chakraborty, Timur Ibrayev, Kaushik Roy
2020	—	`conf`	Spike-FlowNet: Event-Based Optical Flow Estimation with Energy-Efficient Hybrid Neural Networks. ECCV (29) Chankyu Lee, Adarsh Kosta, Alex Zihao Zhu, Kenneth Chaney, Kostas Daniilidis, Kaushik Roy
2020	J	`jnl`	Spike-FlowNet: Event-based Optical Flow Estimation with Energy-Efficient Hybrid Neural Networks. CoRR Chankyu Lee, Adarsh Kosta, Alex Zihao Zhu, Kenneth Chaney, Kostas Daniilidis, Kaushik Roy
2020	J	`jnl`	Structured Compression and Sharing of Representational Space for Continual Learning. CoRR Gobinda Saha, Isha Garg, Aayush Ankit, Kaushik Roy
2020	J	`jnl`	TREND: Transferability based Robust ENsemble Design. CoRR Deepak Ravikumar, Sangamesh Kodge, Isha Garg, Kaushik Roy
2020	J	`jnl`	Towards Understanding the Effect of Leak in Spiking Neural Networks. CoRR Sayeed Shafayet Chowdhury, Chankyu Lee, Kaushik Roy
2020	J	`jnl`	TraNNsformer: Clustered Pruning on Crossbar-Based Architectures for Energy-Efficient Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Aayush Ankit, Timur Ibrayev, Abhronil Sengupta, Kaushik Roy
2020	Misc	`conf`	Training Deep Spiking Neural Networks for Energy-Efficient Neuromorphic Computing. ICASSP Gopalakrishnan Srinivasan, Chankyu Lee, Abhronil Sengupta, Priyadarshini Panda, Syed Shakib Sarwar, Kaushik Roy
2020	J	`jnl`	Tree-CNN: A hierarchical Deep Convolutional Neural Network for incremental learning. Neural Networks Deboleena Roy, Priyadarshini Panda, Kaushik Roy
2020	J	`jnl`	i-SRAM: Interleaved Wordlines for Vector Boolean Operations Using SRAMs. IEEE Trans. Circuits Syst. Akhilesh Jaiswal, Amogh Agrawal, Mustafa Fayez Ali, Saima Sharmin, Kaushik Roy
2020	J	`jnl`	sBSNN: Stochastic-Bits Enabled Binary Spiking Neural Network With On-Chip Learning for Energy Efficient Neuromorphic Computing at the Edge. IEEE Trans. Circuits Syst. I Regul. Pap. Minsuk Koo, Gopalakrishnan Srinivasan, Yong Shim, Kaushik Roy
2020	J	`jnl`	sBSNN: Stochastic-Bits Enabled Binary Spiking Neural Network with On-Chip Learning for Energy Efficient Neuromorphic Computing at the Edge. CoRR Minsuk Koo, Gopalakrishnan Srinivasan, Yong Shim, Kaushik Roy
2019	J	`jnl`	8T SRAM Cell as a Multibit Dot-Product Engine for Beyond Von Neumann Computing. IEEE Trans. Very Large Scale Integr. Syst. Akhilesh Jaiswal, Indranil Chakraborty, Amogh Agrawal, Kaushik Roy
2019	B	`conf`	A Comprehensive Analysis on Adversarial Robustness of Spiking Neural Networks. IJCNN Saima Sharmin, Priyadarshini Panda, Syed Shakib Sarwar, Chankyu Lee, Wachirawit Ponghiran, Kaushik Roy
2019	J	`jnl`	A Comprehensive Analysis on Adversarial Robustness of Spiking Neural Networks. CoRR Saima Sharmin, Priyadarshini Panda, Syed Shakib Sarwar, Chankyu Lee, Wachirawit Ponghiran, Kaushik Roy
2019	—	`ch.`	Automatic Synthesis Techniques for Approximate Circuits. Approximate Circuits Ashish Ranjan, Swagath Venkataramani, Shubham Jain, Younghoon Kim, Shankar Ganesh Ramasubramanian, Arnab Raha, Kaushik Roy, Anand Raghunathan
2019	—	`conf`	Bayesian-based Hyperparameter Optimization for Spiking Neuromorphic Systems. IEEE BigData Maryam Parsa, J. Parker Mitchell, Catherine D. Schuman, Robert M. Patton, Thomas E. Potok, Kaushik Roy
2019	J	`jnl`	Deep Spiking Convolutional Neural Network Trained With Unsupervised Spike-Timing-Dependent Plasticity. IEEE Trans. Cogn. Dev. Syst. Chankyu Lee, Gopalakrishnan Srinivasan, Priyadarshini Panda, Kaushik Roy
2019	—	`conf`	Digital and Analog-Mixed-Signal In-Memory Processing in CMOS SRAM. ACM Great Lakes Symposium on VLSI Akhilesh Jaiswal, Amogh Agrawal, Indranil Chakraborty, Mustafa Fayez Ali, Kaushik Roy
2019	J	`jnl`	Discretization Based Solutions for Secure Machine Learning Against Adversarial Attacks. IEEE Access Priyadarshini Panda, Indranil Chakraborty, Kaushik Roy
2019	J	`jnl`	Discretization based Solutions for Secure Machine Learning against Adversarial Attacks. CoRR Priyadarshini Panda, Indranil Chakraborty, Kaushik Roy
2019	J	`jnl`	Efficient Hybrid Network Architectures for Extremely Quantized Neural Networks Enabling Intelligence at the Edge. CoRR Indranil Chakraborty, Deboleena Roy, Aayush Ankit, Kaushik Roy
2019	J	`jnl`	Enabling Spike-based Backpropagation in State-of-the-art Deep Neural Network Architectures. CoRR Chankyu Lee, Syed Shakib Sarwar, Kaushik Roy
2019	B	`conf`	Evaluating the Stability of Recurrent Neural Models during Training with Eigenvalue Spectra Analysis. IJCNN Priyadarshini Panda, Efstathia Soufleri, Kaushik Roy
2019	J	`jnl`	Evaluating the Stability of Recurrent Neural Models during Training with Eigenvalue Spectra Analysis. CoRR Priyadarshini Panda, Efstathia Soufleri, Kaushik Roy
2019	J	`jnl`	Exploiting Inherent Error Resiliency of Deep Neural Networks to Achieve Extreme Energy Efficiency Through Mixed-Signal Neurons. IEEE Trans. Very Large Scale Integr. Syst. Baibhab Chatterjee, Priyadarshini Panda, Shovan Maity, Ayan Biswas, Kaushik Roy, Shreyas Sen
2019	B	`conf`	Neural Networks at the Edge. SMARTCOMP Deboleena Roy, Gopalakrishnan Srinivasan, Priyadarshini Panda, Richard Tomsett, Nirmit Desai, Raghu K. Ganti, Kaushik Roy
2019	J	`jnl`	Neural network accelerator design with resistive crossbars: Opportunities and challenges. IBM J. Res. Dev. Shubham Jain, Aayush Ankit, Indranil Chakraborty, Tayfun Gokmen, Malte J. Rasch, Wilfried Haensch, Kaushik Roy, Anand Raghunathan
2019	B	`conf`	On Robustness of Spin-Orbit-Torque Based Stochastic Sigmoid Neurons for Spiking Neural Networks. IJCNN Akhilesh Jaiswal, Amogh Agrawal, Indranil Chakraborty, Deboleena Roy, Kaushik Roy
2019	A	`conf`	PABO: Pseudo Agent-Based Multi-Objective Bayesian Hyperparameter Optimization for Efficient Neural Accelerator Design. ICCAD Maryam Parsa, Aayush Ankit, Amirkoushyar Ziabari, Kaushik Roy
2019	J	`jnl`	PABO: Pseudo Agent-Based Multi-Objective Bayesian Hyperparameter Optimization for Efficient Neural Accelerator Design. CoRR Maryam Parsa, Aayush Ankit, Amirkoushyar Ziabari, Kaushik Roy
2019	J	`jnl`	PANTHER: A Programmable Architecture for Neural Network Training Harnessing Energy-efficient ReRAM. CoRR Aayush Ankit, Izzat El Hajj, Sai Rahul Chalamalasetti, Sapan Agarwal, Matthew J. Marinella, Martin Foltin, John Paul Strachan, Dejan S. Milojicic, Wen-mei W. Hwu, Kaushik Roy
2019	J	`jnl`	PCA-driven Hybrid network design for enabling Intelligence at the Edge. CoRR Indranil Chakraborty, Deboleena Roy, Isha Garg, Aayush Ankit, Kaushik Roy
2019	A*	`conf`	PUMA: A Programmable Ultra-efficient Memristor-based Accelerator for Machine Learning Inference. ASPLOS Aayush Ankit, Izzat El Hajj, Sai Rahul Chalamalasetti, Geoffrey Ndu, Martin Foltin, R. Stanley Williams, Paolo Faraboschi, Wen-mei W. Hwu, John Paul Strachan, Kaushik Roy, Dejan S. Milojicic
2019	J	`jnl`	PUMA: A Programmable Ultra-efficient Memristor-based Accelerator for Machine Learning Inference. CoRR Aayush Ankit, Izzat El Hajj, Sai Rahul Chalamalasetti, Geoffrey Ndu, Martin Foltin, R. Stanley Williams, Paolo Faraboschi, Wen-Mei Hwu, John Paul Strachan, Kaushik Roy, Dejan S. Milojicic
2019	J	`jnl`	Powerline Communication for Enhanced Connectivity in Neuromorphic Systems. IEEE Trans. Very Large Scale Integr. Syst. Aayush Ankit, Minsuk Koo, Shreyas Sen, Kaushik Roy
2019	J	`jnl`	ReStoCNet: Residual Stochastic Binary Convolutional Spiking Neural Network for Memory-Efficient Neuromorphic Computing. CoRR Gopalakrishnan Srinivasan, Kaushik Roy
2019	J	`jnl`	Reinforcement Learning with Low-Complexity Liquid State Machines. CoRR Wachirawit Ponghiran, Gopalakrishnan Srinivasan, Kaushik Roy
2019	J	`jnl`	SPARE: Spiking Neural Network Acceleration Using ROM-Embedded RAMs as In-Memory-Computation Primitives. IEEE Trans. Computers Amogh Agrawal, Aayush Ankit, Kaushik Roy
2019	J	`jnl`	STDP-Based Pruning of Connections and Weight Quantization in Spiking Neural Networks for Energy-Efficient Recognition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Nitin Rathi, Priyadarshini Panda, Kaushik Roy
2019	C	`conf`	Scaling Deep Spiking Neural Networks with Binary Stochastic Activations. ICCC Deboleena Roy, Indranil Chakraborty, Kaushik Roy
2019	—	`conf`	Smart cameras everywhere: AI vision on edge with emerging memories. ICECS Alex James, Georgios Ch. Sirakoulis, Kaushik Roy
2019	J	`jnl`	Stimulating STDP to Exploit Locality for Lifelong Learning without Catastrophic Forgetting. CoRR Jason M. Allred, Kaushik Roy
2019	J	`jnl`	Structured Learning for Action Recognition in Videos. IEEE J. Emerg. Sel. Topics Circuits Syst. Yinghan Long, Gopalakrishnan Srinivasan, Priyadarshini Panda, Kaushik Roy
2019	J	`jnl`	Synthesizing Images from Spatio-Temporal Representations using Spike-based Backpropagation. CoRR Deboleena Roy, Priyadarshini Panda, Kaushik Roy
2019	J	`jnl`	Towards Scalable, Efficient and Accurate Deep Spiking Neural Networks with Backward Residual Connections, Stochastic Softmax and Hybridization. CoRR Priyadarshini Panda, Sai Aparna Aketi, Kaushik Roy
2019	B	`conf`	Using Graphical Models as Explanations in Deep Neural Networks. MASS Franck Le, Mudhakar Srivatsa, Krishna Kesari Reddy, Kaushik Roy
2019	J	`jnl`	X-CHANGR: Changing Memristive Crossbar Mapping for Mitigating Line-Resistance Induced Accuracy Degradation in Deep Neural Networks. CoRR Amogh Agrawal, Chankyu Lee, Kaushik Roy
2019	J	`jnl`	Xcel-RAM: Accelerating Binary Neural Networks in High-Throughput SRAM Compute Arrays. IEEE Trans. Circuits Syst. I Regul. Pap. Amogh Agrawal, Akhilesh Jaiswal, Deboleena Roy, Bing Han, Gopalakrishnan Srinivasan, Aayush Ankit, Kaushik Roy
2018	J	`jnl`	8T SRAM Cell as a Multi-bit Dot Product Engine for Beyond von-Neumann Computing. CoRR Akhilesh Jaiswal, Indranil Chakraborty, Amogh Agrawal, Kaushik Roy
2018	J	`jnl`	A Low Effort Approach to Structured CNN Design Using PCA. CoRR Isha Garg, Priyadarshini Panda, Kaushik Roy
2018	J	`jnl`	ASP: Learning to Forget With Adaptive Synaptic Plasticity in Spiking Neural Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. Priyadarshini Panda, Jason M. Allred, Shriram Ramanathan, Kaushik Roy
2018	—	`conf`	Accelerated BTI degradation under stochastic TDDB effect. IRPS Devyani Patra, Ahmed Kamal Reza, Mehdi Katoozi, Ethan H. Cannon, Kaushik Roy, Yu Cao
2018	J	`jnl`	Adaptive accelerated aging for 28 nm HKMG technology. Microelectron. Reliab. Devyani Patra, Ahmed Kamal Reza, Mohammad Khaled Hassan, Mehdi Katoozi, Ethan H. Cannon, Kaushik Roy, Yu Cao
2018	J	`jnl`	All-Photonic Phase Change Spiking Neuron: Toward Fast Neural Computing using Light. CoRR Indranil Chakraborty, Gobinda Saha, Abhronil Sengupta, Kaushik Roy
2018	J	`jnl`	An All-Memristor Deep Spiking Neural Computing System: A Step Toward Realizing the Low-Power Stochastic Brain. IEEE Trans. Emerg. Top. Comput. Intell. Parami Wijesinghe, Aayush Ankit, Abhronil Sengupta, Kaushik Roy
2018	—	`conf`	Analysis of Bridge Defects in STT-MRAM Cells Under Process Variations and a Robust DFT Technique for Their Detection. VLSI-SoC (Selected Papers) Víctor H. Champac, Andres F. Gomez, Freddy Forero, Kaushik Roy
2018	J	`jnl`	Capacitively Driven Global Interconnect with Magnetoelectric Switching Based Receiver for Higher Energy Efficiency. CoRR Zubair Al Azim, Akhilesh Jaiswal, Indranil Chakraborty, Kaushik Roy
2018	J	`jnl`	Computing in Memory With Spin-Transfer Torque Magnetic RAM. IEEE Trans. Very Large Scale Integr. Syst. Shubham Jain, Ashish Ranjan, Kaushik Roy, Anand Raghunathan
2018	A	`conf`	Computing-in-memory with spintronics. DATE Shubham Jain, Sachin S. Sapatnekar, Jianping Wang, Kaushik Roy, Anand Raghunathan
2018	J	`jnl`	Cross-Layer Design Exploration for Energy-Quality Tradeoffs in Spiking and Non-Spiking Deep Artificial Neural Networks. IEEE Trans. Multi Scale Comput. Syst. Bing Han, Aayush Ankit, Abhronil Sengupta, Kaushik Roy
2018	J	`jnl`	DeltaFrame-BP: An Algorithm Using Frame Difference for Deep Convolutional Neural Networks Training and Inference on Video Data. IEEE Trans. Multi Scale Comput. Syst. Bing Han, Kaushik Roy
2018	J	`jnl`	Designing Energy-Efficient Intermittently Powered Systems Using Spin-Hall-Effect-Based Nonvolatile SRAM. IEEE Trans. Very Large Scale Integr. Syst. Arnab Raha, Akhilesh Jaiswal, Syed Shakib Sarwar, Hrishikesh Jayakumar, Vijay Raghunathan, Kaushik Roy
2018	J	`jnl`	Energy Efficient Neural Computing: A Study of Cross-Layer Approximations. IEEE J. Emerg. Sel. Topics Circuits Syst. Syed Shakib Sarwar, Gopalakrishnan Srinivasan, Bing Han, Parami Wijesinghe, Akhilesh Jaiswal, Priyadarshini Panda, Anand Raghunathan, Kaushik Roy
2018	J	`jnl`	Energy-Efficient Neural Computing with Approximate Multipliers. ACM J. Emerg. Technol. Comput. Syst. Syed Shakib Sarwar, Swagath Venkataramani, Aayush Ankit, Anand Raghunathan, Kaushik Roy
2018	J	`jnl`	Explainable Learning: Implicit Generative Modelling during Training for Adversarial Robustness. CoRR Priyadarshini Panda, Kaushik Roy
2018	J	`jnl`	Exploiting Inherent Error-Resiliency of Neuromorphic Computing to achieve Extreme Energy-Efficiency through Mixed-Signal Neurons. CoRR Baibhab Chatterjee, Priyadarshini Panda, Shovan Maity, Ayan Biswas, Kaushik Roy, Shreyas Sen
2018	J	`jnl`	Going Deeper in Spiking Neural Networks: VGG and Residual Architectures. CoRR Abhronil Sengupta, Yuting Ye, Robert Wang, Chiao Liu, Kaushik Roy
2018	—	`conf`	Hardware-Software Co-Design for an Analog-Digital Accelerator for Machine Learning. ICRC Joao Ambrosi, Aayush Ankit, Rodrigo Antunes, Sai Rahul Chalamalasetti, Soumitra Chatterjee, Izzat El Hajj, Guilherme Fachini, Paolo Faraboschi, Martin Foltin, Sitao Huang, Wen-Mei Hwu, Gustavo Knuppe, Sunil Vishwanathpur Lakshminarasimha, Dejan S. Milojicic, Mohan Parthasarathy, Filipe Ribeiro, Lucas Rosa, Kaushik Roy, Plínio Silveira, John Paul Strachan
2018	J	`jnl`	High-Density SOT-MRAM Based on Shared Bitline Structure. IEEE Trans. Very Large Scale Integr. Syst. Yeongkyo Seo, Kaushik Roy
2018	J	`jnl`	Image Edge Detection Based on Swarm Intelligence Using Memristive Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zoha Pajouhi, Kaushik Roy
2018	C	`conf`	M ISCAS Darya Mikhailenko, Chamika M. Liyanagedera, Alex Pappachen James, Kaushik Roy
2018	—	`conf`	Neuromorphic Computing Across the Stack: Devices, Circuits and Architectures. SiPS Aayush Ankit, Abhronil Sengupta, Kaushik Roy
2018	J	`jnl`	Photonic Spiking Neural Networks - From Devices to Systems. CoRR Indranil Chakraborty, Gobinda Saha, Kaushik Roy
2018	J	`jnl`	Proposal for a Low Voltage Analog-to-Digital Converter using Voltage Controlled Stochastic Switching of Low Barrier Nanomagnets. CoRR Indranil Chakraborty, Amogh Agrawal, Kaushik Roy
2018	—	`conf`	RECache: ROM-Embedded 8-Transistor SRAM Caches for Efficient Neural Computing. SiPS Amogh Agrawal, Kaushik Roy
2018	C	`conf`	Robust Detection of Bridge Defects in STT-MRAM Cells Under Process Variations. VLSI-SoC Andres F. Gomez, Freddy Forero, Kaushik Roy, Víctor H. Champac
2018	J	`jnl`	Rx-Caffe: Framework for evaluating and training Deep Neural Networks on Resistive Crossbars. CoRR Shubham Jain, Abhronil Sengupta, Kaushik Roy, Anand Raghunathan
2018	J	`jnl`	STDP-based Unsupervised Feature Learning using Convolution-over-time in Spiking Neural Networks for Energy-Efficient Neuromorphic Computing. ACM J. Emerg. Technol. Comput. Syst. Gopalakrishnan Srinivasan, Priyadarshini Panda, Kaushik Roy
2018	J	`jnl`	Technology Aware Training in Memristive Neuromorphic Systems for Nonideal Synaptic Crossbars. IEEE Trans. Emerg. Top. Comput. Intell. Indranil Chakraborty, Deboleena Roy, Kaushik Roy
2018	J	`jnl`	Tree-CNN: A Deep Convolutional Neural Network for Lifelong Learning. CoRR Deboleena Roy, Priyadarshini Panda, Kaushik Roy
2018	J	`jnl`	X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories. IEEE Trans. Circuits Syst. I Regul. Pap. Amogh Agrawal, Akhilesh Jaiswal, Chankyu Lee, Kaushik Roy
2018	J	`jnl`	Xcel-RAM: Accelerating Binary Neural Networks in High-Throughput SRAM Compute Arrays. CoRR Amogh Agrawal, Akhilesh Jaiswal, Bing Han, Gopalakrishnan Srinivasan, Kaushik Roy
2017	A*	`conf`	A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited. DAC Jianping Wang, Sachin S. Sapatnekar, Chris H. Kim, Paul A. Crowell, Steven J. Koester, Supriyo Datta, Kaushik Roy, Anand Raghunathan, Xiaobo Sharon Hu, Michael T. Niemier, Azad Naeemi, Chia-Ling Chien, Caroline A. Ross, Roland Kawakami
2017	J	`jnl`	ASP: Learning to Forget with Adaptive Synaptic Plasticity in Spiking Neural Networks. CoRR Priyadarshini Panda, Jason M. Allred, Shriram Ramanathan, Kaushik Roy
2017	J	`jnl`	An All-Memristor Deep Spiking Neural Network: A Step Towards Realizing the Low Power, Stochastic Brain. CoRR Parami Wijesinghe, Aayush Ankit, Abhronil Sengupta, Kaushik Roy
2017	—	`conf`	An Energy-Efficient Mixed-Signal Neuron for Inherently Error-Resilient Neuromorphic Systems. ICRC Baibhab Chatterjee, Priyadarshini Panda, Shovan Maity, Kaushik Roy, Shreyas Sen
2017	J	`jnl`	An Energy-Efficient Mixed-Signal Neuron for Inherently Error-Resilient Neuromorphic Systems. CoRR Baibhab Chatterjee, Priyadarshini Panda, Shovan Maity, Kaushik Roy, Shreyas Sen
2017	J	`jnl`	Chaos-guided Input Structuring for Improved Learning in Recurrent Neural Networks. CoRR Priyadarshini Panda, Kaushik Roy
2017	J	`jnl`	Computing in Memory with Spin-Transfer Torque Magnetic RAM. CoRR Shubham Jain, Ashish Ranjan, Kaushik Roy, Anand Raghunathan
2017	J	`jnl`	Convolutional Spike Timing Dependent Plasticity based Feature Learning in Spiking Neural Networks. CoRR Priyadarshini Panda, Gopalakrishnan Srinivasan, Kaushik Roy
2017	B	`conf`	Convolving over time via recurrent connections for sequential weight sharing in neural networks. IJCNN Jason M. Allred, Kaushik Roy
2017	J	`jnl`	Coupled Spin-Torque Nano-Oscillator-Based Computation: A Simulation Study. ACM J. Emerg. Technol. Comput. Syst. Karthik Yogendra, Chamika M. Liyanagedera, Deliang Fan, Yong Shim, Kaushik Roy
2017	J	`jnl`	Encoding Neural and Synaptic Functionalities in Electron Spin: A Pathway to Efficient Neuromorphic Computing. CoRR Abhronil Sengupta, Kaushik Roy
2017	—	`conf`	Energy efficient computation using injection locked bias-field free spin-hall nano-oscillator array with shared heavy metal. NANOARCH Karthik Yogendra, Minsuk Koo, Kaushik Roy
2017	J	`jnl`	Energy-Efficient Memories using Magneto-Electric Switching of Ferromagnets. CoRR Akhilesh Jaiswal, Indranil Chakraborty, Kaushik Roy
2017	J	`jnl`	Energy-Efficient Object Detection Using Semantic Decomposition. IEEE Trans. Very Large Scale Integr. Syst. Priyadarshini Panda, Swagath Venkataramani, Abhronil Sengupta, Anand Raghunathan, Kaushik Roy
2017	J	`jnl`	Energy-Efficient and Improved Image Recognition with Conditional Deep Learning. ACM J. Emerg. Technol. Comput. Syst. Priyadarshini Panda, Abhronil Sengupta, Kaushik Roy
2017	B	`conf`	EnsembleSNN: Distributed assistive STDP learning for energy-efficient recognition in spiking neural networks. IJCNN Priyadarshini Panda, Gopalakrishnan Srinivasan, Kaushik Roy
2017	J	`jnl`	FALCON: Feature Driven Selective Classification for Energy-Efficient Image Recognition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Priyadarshini Panda, Aayush Ankit, Parami Wijesinghe, Kaushik Roy
2017	J	`jnl`	Fast and Disturb-Free Nonvolatile Flip-Flop Using Complementary Polarizer MTJ. IEEE Trans. Very Large Scale Integr. Syst. Yeongkyo Seo, Xuanyao Fong, Kaushik Roy
2017	A	`conf`	Fast, low power evaluation of elementary functions using radial basis function networks. DATE Parami Wijesinghe, Chamika M. Liyanagedera, Kaushik Roy
2017	J	`jnl`	Gabor Filter Assisted Energy Efficient Fast Learning Convolutional Neural Networks. CoRR Syed Shakib Sarwar, Priyadarshini Panda, Kaushik Roy
2017	A	`conf`	Gabor filter assisted energy efficient fast learning Convolutional Neural Networks. ISLPED Syed Shakib Sarwar, Priyadarshini Panda, Kaushik Roy
2017	B	`conf`	Image segmentation with stochastic magnetic tunnel junctions and spiking neurons. IJCNN Chamika M. Liyanagedera, Parami Wijesinghe, Akhilesh Jaiswal, Kaushik Roy
2017	J	`jnl`	Incremental Learning in Deep Convolutional Neural Networks Using Partial Network Sharing. CoRR Syed Shakib Sarwar, Aayush Ankit, Kaushik Roy
2017	J	`jnl`	Investigation of dependence between time-zero and time-dependent variability in high-κ NMOS transistors. Microelectron. Reliab. Mohammad Khaled Hassan, Kaushik Roy
2017	J	`jnl`	Magnetic Tunnel Junction Enabled Stochastic Spiking Neural Networks: From Non-Telegraphic to Telegraphic Switching Regime. CoRR Chamika M. Liyanagedera, Abhronil Sengupta, Akhilesh Jaiswal, Kaushik Roy
2017	A	`conf`	Magnetic tunnel junction enabled all-spin stochastic spiking neural network. DATE Gopalakrishnan Srinivasan, Abhronil Sengupta, Kaushik Roy
2017	B	`conf`	Performance analysis and benchmarking of all-spin spiking neural networks (Special session paper). IJCNN Abhronil Sengupta, Aayush Ankit, Kaushik Roy
2017	J	`jnl`	Proposal for a Leaky Integrate Fire Spiking Neuron Using Voltage Driven Domain Wall Motion. CoRR Akhilesh Jaiswal, Amogh Agrawal, Kaushik Roy
2017	A*	`conf`	RESPARC: A Reconfigurable and Energy-Efficient Architecture with Memristive Crossbars for Deep Spiking Neural Networks. DAC Aayush Ankit, Abhronil Sengupta, Priyadarshini Panda, Kaushik Roy
2017	J	`jnl`	RESPARC: A Reconfigurable and Energy-Efficient Architecture with Memristive Crossbars for Deep Spiking Neural Networks. CoRR Aayush Ankit, Abhronil Sengupta, Priyadarshini Panda, Kaushik Roy
2017	J	`jnl`	SPARE: Spiking Networks Acceleration Using CMOS ROM-Embedded RAM as an In-Memory-Computation Primitive. CoRR Amogh Agrawal, Aayush Ankit, Kaushik Roy
2017	A	`conf`	STAxCache: An approximate, energy efficient STT-MRAM cache. DATE Ashish Ranjan, Swagath Venkataramani, Zoha Pajouhi, Rangharajan Venkatesan, Kaushik Roy, Anand Raghunathan
2017	J	`jnl`	STDP Based Pruning of Connections and Weight Quantization in Spiking Neural Networks for Energy Efficient Recognition. CoRR Nitin Rathi, Priyadarshini Panda, Kaushik Roy
2017	A	`conf`	Semantic driven hierarchical learning for energy-efficient image classification. DATE Priyadarshini Panda, Kaushik Roy
2017	B	`conf`	Spike timing dependent plasticity based enhanced self-learning for efficient pattern recognition in spiking neural networks. IJCNN Gopalakrishnan Srinivasan, Sourjya Roy, Vijay Raghunathan, Kaushik Roy
2017	—	`conf`	Spin-torque memristor based offset cancellation technique for sense amplifiers. SMACD Mesut Atasoyu, Mustafa Altun, Serdar Özoguz, Kaushik Roy
2017	A	`conf`	Spin-torque sensors with differential signaling for fast and energy efficient global interconnects. ISLPED Zubair Azim, Kaushik Roy
2017	—	`conf`	Staged Inference using Conditional Deep Learning for energy efficient real-time smart diagnosis. EMBC Maryam Parsa, Priyadarshini Panda, Shreyas Sen, Kaushik Roy
2017	J	`jnl`	Stochastic Spin-Orbit Torque Devices as Elements for Bayesian Inference. CoRR Yong Shim, Shuhan Chen, Abhronil Sengupta, Kaushik Roy
2017	C	`conf`	Stochastic Switching of SHE-MTJ as a Natural Annealer for Efficient Combinatorial Optimization. ICCD Yong Shim, Akhilesh Jaiswal, Kaushik Roy
2017	J	`jnl`	Technology Aware Training in Memristive Neuromorphic Systems based on non-ideal Synaptic Crossbars. CoRR Indranil Chakraborty, Deboleena Roy, Kaushik Roy
2017	J	`jnl`	TraNNsformer: Neural Network Transformation for Memristive Crossbar based Neuromorphic System Design. CoRR Aayush Ankit, Abhronil Sengupta, Kaushik Roy
2017	A	`conf`	TraNNsformer: Neural network transformation for memristive crossbar based neuromorphic system design. ICCAD Aayush Ankit, Abhronil Sengupta, Kaushik Roy
2017	J	`jnl`	X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories. CoRR Amogh Agrawal, Akhilesh Jaiswal, Kaushik Roy
2016	J	`jnl`	A Vision for All-Spin Neural Networks: A Device to System Perspective. IEEE Trans. Circuits Syst. I Regul. Pap. Abhronil Sengupta, Kaushik Roy
2016	C	`conf`	A low-voltage, low power STDP synapse implementation using domain-wall magnets for spiking neural networks. ISCAS Govind Narasimman, Subhrajit Roy, Xuanyao Fong, Kaushik Roy, Chip-Hong Chang, Arindam Basu
2016	Misc	`conf`	Approximate Computing. VLSID Swagath Venkataramani, Kaushik Roy, Anand Raghunathan
2016	J	`jnl`	Asymmetric Underlapped FinFETs for Near- and Super-Threshold Logic at Sub-10nm Technology Nodes. ACM J. Emerg. Technol. Comput. Syst. A. Arun Goud, Rangharajan Venkatesan, Anand Raghunathan, Kaushik Roy
2016	J	`jnl`	Attention Tree: Learning Hierarchies of Visual Features for Large-Scale Image Recognition. CoRR Priyadarshini Panda, Kaushik Roy
2016	J	`jnl`	Cache Design with Domain Wall Memory. IEEE Trans. Computers Rangharajan Venkatesan, Vivek Joy Kozhikkottu, Mrigank Sharad, Charles Augustine, Arijit Raychowdhury, Kaushik Roy, Anand Raghunathan
2016	J	`jnl`	Comprehensive Scaling Analysis of Current Induced Switching in Magnetic Memories Based on In-Plane and Perpendicular Anisotropies. IEEE J. Emerg. Sel. Topics Circuits Syst. Akhilesh Jaiswal, Xuanyao Fong, Kaushik Roy
2016	—	`conf`	Computing with coupled Spin Torque Nano Oscillators. ASP-DAC Karthik Yogendra, Deliang Fan, Yong Shim, Minsuk Koo, Kaushik Roy
2016	A	`conf`	Conditional Deep Learning for energy-efficient and enhanced pattern recognition. DATE Priyadarshini Panda, Abhronil Sengupta, Kaushik Roy
2016	A	`conf`	Design of power-efficient approximate multipliers for approximate artificial neural networks. ICCAD Vojtech Mrazek, Syed Shakib Sarwar, Lukás Sekanina, Zdenek Vasícek, Kaushik Roy
2016	A*	`conf`	Designing approximate circuits using clock overgating. DAC Younghoon Kim, Swagath Venkataramani, Kaushik Roy, Anand Raghunathan
2016	—	`conf`	Digital LDO with Time-Interleaved Comparators for Fast Response and Low Ripple. ISVLSI Sohail Ahasan, Saurav Maji, Kaushik Roy, Mrigank Sharad
2016	—	`conf`	Efficient embedded learning for IoT devices. ASP-DAC Swagath Venkataramani, Kaushik Roy, Anand Raghunathan
2016	J	`jnl`	Embedding Read-Only Memory in Spin-Transfer Torque MRAM-Based On-Chip Caches. IEEE Trans. Very Large Scale Integr. Syst. Xuanyao Fong, Rangharajan Venkatesan, Dongsoo Lee, Anand Raghunathan, Kaushik Roy
2016	J	`jnl`	FALCON: Feature Driven Selective Classification for Energy-Efficient Image Recognition. CoRR Priyadarshini Panda, Aayush Ankit, Parami Wijesinghe, Kaushik Roy
2016	J	`jnl`	Hierarchical Temporal Memory Based on Spin-Neurons and Resistive Memory for Energy-Efficient Brain-Inspired Computing. IEEE Trans. Neural Networks Learn. Syst. Deliang Fan, Mrigank Sharad, Abhronil Sengupta, Kaushik Roy
2016	J	`jnl`	High Performance and Energy-Efficient On-Chip Cache Using Dual Port (1R/1W) Spin-Orbit Torque MRAM. IEEE J. Emerg. Sel. Topics Circuits Syst. Yeongkyo Seo, Kon-Woo Kwon, Xuanyao Fong, Kaushik Roy
2016	J	`jnl`	Image Edge Detection based on Swarm Intelligence using Memristive Networks. CoRR Zoha Pajouhi, Kaushik Roy
2016	J	`jnl`	Integrated Systems in the More-Than-Moore Era: Designing Low-Cost Energy-Efficient Systems Using Heterogeneous Components. IEEE Des. Test Kaushik Roy, Byunghoo Jung, Dimitrios Peroulis, Anand Raghunathan
2016	A*	`conf`	Invited - Cross-layer approximations for neuromorphic computing: from devices to circuits and systems. DAC Priyadarshini Panda, Abhronil Sengupta, Syed Shakib Sarwar, Gopalakrishnan Srinivasan, Swagath Venkataramani, Anand Raghunathan, Kaushik Roy
2016	J	`jnl`	Ising spin model using Spin-Hall Effect (SHE) induced magnetization reversal in Magnetic-Tunnel-Junction. CoRR Yong Shim, Akhilesh Jaiswal, Kaushik Roy
2016	J	`jnl`	Low-Power System for Detection of Symptomatic Patterns in Audio Biological Signals. IEEE Trans. Very Large Scale Integr. Syst. Himanshu Markandeya, Kaushik Roy
2016	A*	`conf`	Low-power approximate convolution computing unit with domain-wall motion based "spin-memristor" for image processing applications. DAC Yong Shim, Abhronil Sengupta, Kaushik Roy
2016	J	`jnl`	MESL: Proposal for a Non-volatile Cascadable Magneto-Electric Spin Logic. CoRR Akhilesh Jaiswal, Kaushik Roy
2016	J	`jnl`	Multiplier-less Artificial Neurons Exploiting Error Resiliency for Energy-Efficient Neural Computing. CoRR Syed Shakib Sarwar, Swagath Venkataramani, Anand Raghunathan, Kaushik Roy
2016	A	`conf`	Multiplier-less Artificial Neurons exploiting error resiliency for energy-efficient neural computing. DATE Syed Shakib Sarwar, Swagath Venkataramani, Anand Raghunathan, Kaushik Roy
2016	Misc	`conf`	Neuromorphic Computing Enabled by Spin-Transfer Torque Devices. VLSID Abhronil Sengupta, Priyadarshini Panda, Anand Raghunathan, Kaushik Roy
2016	B	`conf`	On the energy benefits of spiking deep neural networks: A case study. IJCNN Bing Han, Abhronil Sengupta, Kaushik Roy
2016	J	`jnl`	Probabilistic Deep Spiking Neural Systems Enabled by Magnetic Tunnel Junction. CoRR Abhronil Sengupta, Maryam Parsa, Bing Han, Kaushik Roy
2016	J	`jnl`	Proposal for a Leaky-Integrate-Fire Spiking Neuron based on Magneto-Electric Switching of Ferro-magnets. CoRR Akhilesh Jaiswal, Sourjya Roy, Gopalakrishnan Srinivasan, Kaushik Roy
2016	J	`jnl`	Proposal for an All-Spin Artificial Neural Network: Emulating Neural and Synaptic Functionalities Through Domain Wall Motion in Ferromagnets. IEEE Trans. Biomed. Circuits Syst. Abhronil Sengupta, Yong Shim, Kaushik Roy
2016	—	`conf`	Prospects of efficient neural computing with arrays of magneto-metallic neurons and synapses. ASP-DAC Abhronil Sengupta, Karthik Yogendra, Deliang Fan, Kaushik Roy
2016	J	`jnl`	Significance Driven Hybrid 8T-6T SRAM for Energy-Efficient Synaptic Storage in Artificial Neural Networks. CoRR Gopalakrishnan Srinivasan, Parami Wijesinghe, Syed Shakib Sarwar, Akhilesh Jaiswal, Kaushik Roy
2016	A	`conf`	Significance driven hybrid 8T-6T SRAM for energy-efficient synaptic storage in artificial neural networks. DATE Gopalakrishnan Srinivasan, Parami Wijesinghe, Syed Shakib Sarwar, Akhilesh Jaiswal, Kaushik Roy
2016	B	`conf`	Spin torque nano-oscillator based Oscillatory Neural Network. IJCNN Chamika M. Liyanagedera, Karthik Yogendra, Kaushik Roy, Deliang Fan
2016	—	`conf`	Spin transfer torque memories for on-chip caches: Prospects and perspectives. LATS Akhilesh Jaiswal, Kaushik Roy
2016	J	`jnl`	Spin-Transfer Torque Devices for Logic and Memory: Prospects and Perspectives. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xuanyao Fong, Yusung Kim, Karthik Yogendra, Deliang Fan, Abhronil Sengupta, Anand Raghunathan, Kaushik Roy
2016	J	`jnl`	Spin-Transfer Torque Memories: Devices, Circuits, and Systems. Proc. IEEE Xuanyao Fong, Yusung Kim, Rangharajan Venkatesan, Sri Harsha Choday, Anand Raghunathan, Kaushik Roy
2016	C	`conf`	Spintronic devices for ultra-low power neuromorphic computation (Special session paper). ISCAS Abhronil Sengupta, Karthik Yogendra, Kaushik Roy
2016	—	`conf`	Toward a spintronic deep learning spiking neural processor. BioCAS Abhronil Sengupta, Bing Han, Kaushik Roy
2016	J	`jnl`	Unsupervised Regenerative Learning of Hierarchical Features in Spiking Deep Networks for Object Recognition. CoRR Priyadarshini Panda, Kaushik Roy
2016	B	`conf`	Unsupervised incremental STDP learning using forced firing of dormant or idle neurons. IJCNN Jason M. Allred, Kaushik Roy
2016	B	`conf`	Unsupervised regenerative learning of hierarchical features in Spiking Deep Networks for object recognition. IJCNN Priyadarshini Panda, Kaushik Roy
2016	J	`jnl`	Yield, Area, and Energy Optimization in STT-MRAMs Using Failure-Aware ECC. ACM J. Emerg. Technol. Comput. Syst. Zoha Pajouhi, Xuanyao Fong, Anand Raghunathan, Kaushik Roy
2015	—	`conf`	Approximate Computing: An Energy-Efficient Computing Technique for Error Resilient Applications. ISVLSI Kaushik Roy, Anand Raghunathan
2015	A*	`conf`	Approximate computing and the quest for computing efficiency. DAC Swagath Venkataramani, Srimat T. Chakradhar, Kaushik Roy, Anand Raghunathan
2015	A*	`conf`	Approximate storage for energy efficient spintronic memories. DAC Ashish Ranjan, Swagath Venkataramani, Xuanyao Fong, Kaushik Roy, Anand Raghunathan
2015	A	`conf`	Asymmetric underlapped FinFET based robust SRAM design at 7nm node. DATE A. Arun Goud, Rangharajan Venkatesan, Anand Raghunathan, Kaushik Roy
2015	A	`conf`	Computing approximately, and efficiently. DATE Swagath Venkataramani, Srimat T. Chakradhar, Kaushik Roy, Anand Raghunathan
2015	J	`jnl`	Conditional Deep Learning for Energy-Efficient and Enhanced Pattern Recognition. CoRR Priyadarshini Panda, Abhronil Sengupta, Kaushik Roy
2015	A	`conf`	Device/circuit/architecture co-design of reliable STT-MRAM. DATE Zoha Pajouhi, Xuanyao Fong, Kaushik Roy
2015	J	`jnl`	Digital LDO with Time-Interleaved Comparators for Fast Response and Low Ripple. CoRR Sohail Ahasan, Saurav Maji, Kaushik Roy, Mrigank Sharad
2015	—	`conf`	Domain wall motion-based low power hybrid spin-CMOS 5-bit Flash Analog Data Converter. ISQED Karthik Yogendra, Mei-Chin Chen, Xuanyao Fong, Kaushik Roy
2015	A	`conf`	DyReCTape: a <u>dy</u>namically <u>re</u>configurable <u>c</u>ache using domain wall memory <u>tape</u>s. DATE Ashish Ranjan, Shankar Ganesh Ramasubramanian, Rangharajan Venkatesan, Vijay S. Pai, Kaushik Roy, Anand Raghunathan
2015	J	`jnl`	Energy Efficient and High Performance Current-Mode Neural Network Circuit using Memristors and Digitally Assisted Analog CMOS Neurons. CoRR Aranya Goswamy, Sagar Kumashi, Vikash Sehwag, Siddharth Singh, Manny Jain, Kaushik Roy, Mrigank Sharad
2015	J	`jnl`	Energy-Efficient All-Spin Cache Hierarchy Using Shift-Based Writes and Multilevel Storage. ACM J. Emerg. Technol. Comput. Syst. Rangharajan Venkatesan, Mrigank Sharad, Kaushik Roy, Anand Raghunathan
2015	J	`jnl`	Exploring Spin Transfer Torque Devices for Unconventional Computing. IEEE J. Emerg. Sel. Topics Circuits Syst. Kaushik Roy, Deliang Fan, Xuanyao Fong, Yusung Kim, Mrigank Sharad, Somnath Paul, Subho Chatterjee, Swarup Bhunia, Saibal Mukhopadhyay
2015	J	`jnl`	Exploring Spin-Transfer-Torque Devices for Logic Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zoha Pajouhi, Swagath Venkataramani, Karthik Yogendra, Anand Raghunathan, Kaushik Roy
2015	J	`jnl`	Guest Editorial Computing in Emerging Technologies (Second Issue). IEEE J. Emerg. Sel. Topics Circuits Syst. Saibal Mukhopadhyay, Swarup Bhunia, Hillery C. Hunter, Kaushik Roy
2015	J	`jnl`	High Sensitivity Biosensor using Injection Locked Spin Torque Nano-Oscillators. CoRR Tathagata Srimani, Bibhas Manna, Anand Kumar Mukhopadhyay, Kaushik Roy, Mrigank Sharad
2015	J	`jnl`	Highly Reliable Spin-Transfer Torque Magnetic RAM-Based Physical Unclonable Function With Multi-Response-Bits Per Cell. IEEE Trans. Inf. Forensics Secur. Le Zhang, Xuanyao Fong, Chip-Hong Chang, Zhi-Hui Kong, Kaushik Roy
2015	J	`jnl`	Hybrid Spintronic-CMOS Spiking Neural Network With On-Chip Learning: Devices, Circuits and Systems. CoRR Abhronil Sengupta, Aparajita Banerjee, Kaushik Roy
2015	J	`jnl`	Low-Energy Two-Stage Algorithm for High Efficacy Epileptic Seizure Detection. IEEE Trans. Very Large Scale Integr. Syst. Himanshu Markandeya, Pedro P. Irazoqui, Kaushik Roy
2015	J	`jnl`	Magnetic Tunnel Junction Mimics Stochastic Cortical Spiking Neurons. CoRR Abhronil Sengupta, Priyadarshini Panda, Parami Wijesinghe, Yusung Kim, Kaushik Roy
2015	J	`jnl`	Object Detection using Semantic Decomposition for Energy-Efficient Neural Computing. CoRR Priyadarshini Panda, Abhronil Sengupta, Swagath Venkataramani, Anand Raghunathan, Kaushik Roy
2015	J	`jnl`	Optimizating Emerging Nonvolatile Memories for Dual-Mode Applications: Data Storage and Key Generator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Le Zhang, Xuanyao Fong, Chip-Hong Chang, Zhi-Hui Kong, Kaushik Roy
2015	J	`jnl`	Short-Term Plasticity and Long-Term Potentiation in Magnetic Tunnel Junctions: Towards Volatile Synapses. CoRR Abhronil Sengupta, Kaushik Roy
2015	J	`jnl`	Simulation studies of an All-Spin Artificial Neural Network: Emulating neural and synaptic functionalities through domain wall motion in ferromagnets. CoRR Abhronil Sengupta, Yong Shim, Kaushik Roy
2015	J	`jnl`	Spin-Torque Sensors for Energy Efficient High Speed Long Interconnects. CoRR Zubair Al Azim, Abhronil Sengupta, Syed Shakib Sarwar, Kaushik Roy
2015	B	`conf`	Spin-Transfer Torque Magnetic neuron for low power neuromorphic computing. IJCNN Abhronil Sengupta, Kaushik Roy
2015	A	`conf`	Spintastic: <u>spin</u>-based s<u>t</u>och<u>astic</u> logic for energy-efficient computing. DATE Rangharajan Venkatesan, Swagath Venkataramani, Xuanyao Fong, Kaushik Roy, Anand Raghunathan
2015	A	`conf`	Sub-10 nm FinFETs and Tunnel-FETs: from devices to systems. DATE Ankit Sharma, A. Arun Goud, Kaushik Roy
2015	J	`jnl`	Ultra-thin dielectric breakdown in devices and circuits: A brief review. Microelectron. Reliab. Chih-Hsiang Ho, Soo Youn Kim, Kaushik Roy
2015	J	`jnl`	Yield, Area and Energy Optimization in Stt-MRAMs using failure aware ECC. CoRR Zoha Pajouhi, Xuanyao Fong, Anand Raghunathan, Kaushik Roy
2014	—	`conf`	"All Programmable SOC FPGA for networking and computing in big data infrastructure". ASP-DAC Ivo Bolsens, Georges G. E. Gielen, Kaushik Roy, Ulf Schneider
2014	A	`conf`	ASLAN: Synthesis of approximate sequential circuits. DATE Ashish Ranjan, Arnab Raha, Swagath Venkataramani, Kaushik Roy, Anand Raghunathan
2014	J	`jnl`	AWARE (Asymmetric Write Architecture With REdundant Blocks): A High Write Speed STT-MRAM Cache Architecture. IEEE Trans. Very Large Scale Integr. Syst. Kon-Woo Kwon, Sri Harsha Choday, Yusung Kim, Kaushik Roy
2014	—	`conf`	Approximate computing for efficient information processing. ESTIMedia Swagath Venkataramani, Srimat T. Chakradhar, Kaushik Roy, Anand Raghunathan
2014	A	`conf`	AxNN: energy-efficient neuromorphic systems using approximate computing. ISLPED Swagath Venkataramani, Ashish Ranjan, Kaushik Roy, Anand Raghunathan
2014	A	`conf`	Brain-inspired computing with spin torque devices. DATE Kaushik Roy, Mrigank Sharad, Deliang Fan, Karthik Yogendra
2014	—	`conf`	Computing with Spin-Transfer-Torque Devices: Prospects and Perspectives. ISVLSI Kaushik Roy, Mrigank Sharad, Deliang Fan, Karthik Yogendra
2014	J	`jnl`	Data-Dependent Operation Speed-Up Through Automatically Inserted Signal Transition Detectors for Ultralow Voltage Logic Circuits. IEEE Trans. Very Large Scale Integr. Syst. François Botman, David Bol, Jean-Didier Legat, Kaushik Roy
2014	J	`jnl`	Design and Synthesis of Ultra Low Energy Spin-Memristor Threshold Logic. CoRR Deliang Fan, Mrigank Sharad, Kaushik Roy
2014	J	`jnl`	Failure Mitigation Techniques for 1T-1MTJ Spin-Transfer Torque MRAM Bit-cells. IEEE Trans. Very Large Scale Integr. Syst. Xuanyao Fong, Yusung Kim, Sri Harsha Choday, Kaushik Roy
2014	J	`jnl`	Guest Editorial Computing in Emerging Technologies (First Issue). IEEE J. Emerg. Sel. Topics Circuits Syst. Saibal Mukhopadhyay, Swarup Bhunia, Hillery C. Hunter, Kaushik Roy
2014	J	`jnl`	Hierarchical Temporal Memory Based on Spin-Neurons and Resistive Memory for Energy-Efficient Brain-Inspired Computing. CoRR Deliang Fan, Mrigank Sharad, Abhronil Sengupta, Kaushik Roy
2014	C	`conf`	Highly reliable memory-based Physical Unclonable Function using Spin-Transfer Torque MRAM. ISCAS Le Zhang, Xuanyao Fong, Chip-Hong Chang, Zhi-Hui Kong, Kaushik Roy
2014	J	`jnl`	Laser Induced Magnetization Reversal for Detection in Optical Interconnects. CoRR Zubair Al Azim, Xuanyao Fong, Thomas Ostler, Roy W. Chantrell, Kaushik Roy
2014	J	`jnl`	Multi-level wordline driver for robust SRAM design in nano-scale CMOS technology. Microelectron. J. Farshad Moradi, Georgios Panagopoulos, Georgios Karakonstantis, Hooman Farkhani, Dag T. Wisland, Jens Kargaard Madsen, Hamid Mahmoodi, Kaushik Roy
2014	A	`conf`	SPINDLE: SPINtronic deep learning engine for large-scale neuromorphic computing. ISLPED Shankar Ganesh Ramasubramanian, Rangharajan Venkatesan, Mrigank Sharad, Kaushik Roy, Anand Raghunathan
2014	A*	`conf`	STAG: Spintronic-Tape Architecture for GPGPU cache hierarchies. ISCA Rangharajan Venkatesan, Shankar Ganesh Ramasubramanian, Swagath Venkataramani, Kaushik Roy, Anand Raghunathan
2014	J	`jnl`	STT-SNN: A Spin-Transfer-Torque Based Soft-Limiting Non-Linear Neuron for Low-Power Artificial Neural Networks. CoRR Deliang Fan, Yong Shim, Anand Raghunathan, Kaushik Roy
2014	J	`jnl`	Scalable Effort Hardware Design. IEEE Trans. Very Large Scale Integr. Syst. Vinay Kumar Chippa, Debabrata Mohapatra, Kaushik Roy, Srimat T. Chakradhar, Anand Raghunathan
2014	J	`jnl`	Spin Orbit Torque Based Electronic Neuron. CoRR Abhronil Sengupta, Sri Harsha Choday, Yusung Kim, Kaushik Roy
2014	J	`jnl`	Spin-Orbit Torque Induced Spike-Timing Dependent Plasticity. CoRR Abhronil Sengupta, Zubair Al Azim, Xuanyao Fong, Kaushik Roy
2014	A	`conf`	StoRM: a stochastic recognition and mining processor. ISLPED Vinay K. Chippa, Swagath Venkataramani, Kaushik Roy, Anand Raghunathan
2014	A	`conf`	Workload dependent evaluation of thin-film thermoelectric devices for on-chip cooling and energy harvesting. ICCAD Sri Harsha Choday, Kon-Woo Kwon, Kaushik Roy
2013	A*	`conf`	Analysis and characterization of inherent application resilience for approximate computing. DAC Vinay K. Chippa, Srimat T. Chakradhar, Kaushik Roy, Anand Raghunathan
2013	C	`conf`	Approximate computing for energy-efficient error-resilient multimedia systems. DDECS Kaushik Roy
2013	Misc	`conf`	Approximate computing: An integrated hardware approach. ACSSC Vinay K. Chippa, Swagath Venkataramani, Srimat T. Chakradhar, Kaushik Roy, Anand Raghunathan
2013	C	`conf`	Approximate computing: Energy-efficient computing with good-enough results. IOLTS Anand Raghunathan, Kaushik Roy
2013	J	`jnl`	Area Efficient ROM-Embedded SRAM Cache. IEEE Trans. Very Large Scale Integr. Syst. Dongsoo Lee, Kaushik Roy
2013	A	`conf`	Beyond charge-based computation: Boolean and non-Boolean computing with spin torque devices. ISLPED Kaushik Roy, Mrigank Sharad, Deliang Fan, Karthik Yogendra
2013	A	`conf`	DWM-TAPESTRI - an energy efficient all-spin cache using domain wall shift based writes. DATE Rangharajan Venkatesan, Mrigank Sharad, Kaushik Roy, Anand Raghunathan
2013	—	`conf`	Design of ultra high density and low power computational blocks using nano-magnets. ISQED Mrigank Sharad, Karthik Yogendra, Kon-Woo Kwon, Kaushik Roy
2013	J	`jnl`	Device-Circuit Co-Optimization for Robust Design of FinFET-Based SRAMs. IEEE Des. Test Sumeet Kumar Gupta, Kaushik Roy
2013	J	`jnl`	Dual pillar spin-transfer torque MRAMs for low power applications. ACM J. Emerg. Technol. Comput. Syst. Niladri Narayan Mojumder, Xuanyao Fong, Charles Augustine, Sumeet Kumar Gupta, Sri Harsha Choday, Kaushik Roy
2013	—	`conf`	Energy efficient computing using coupled Dual-Pillar Spin Torque Nano Oscillators. NANOARCH Mrigank Sharad, Karthik Yogendra, Kaushik Roy
2013	—	`conf`	Energy-efficient recognition and mining processor using scalable effort design. CICC Vinay K. Chippa, Hrishikesh Jayakumar, Debabrata Mohapatra, Kaushik Roy, Anand Raghunathan
2013	J	`jnl`	Exploring Boolean and Non-Boolean Computing Applications of Spin Torque Devices. CoRR Kaushik Roy, Mrigank Sharad, Deliang Fan, Karthik Yogendra
2013	A	`conf`	Exploring Boolean and non-Boolean computing with spin torque devices. ICCAD Kaushik Roy, Mrigank Sharad, Deliang Fan, Karthik Yogendra
2013	J	`jnl`	Hardware Trojan Detection by Multiple-Parameter Side-Channel Analysis. IEEE Trans. Computers Seetharam Narasimhan, Dongdong Du, Rajat Subhra Chakraborty, Somnath Paul, Francis G. Wolff, Christos A. Papachristou, Kaushik Roy, Swarup Bhunia
2013	—	`conf`	Low power and compact mixed-mode signal processing hardware using spin-neurons. ISQED Mrigank Sharad, Deliang Fan, Kaushik Roy
2013	J	`jnl`	Low-Power Digital Signal Processing Using Approximate Adders. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Vaibhav Gupta, Debabrata Mohapatra, Anand Raghunathan, Kaushik Roy
2013	J	`jnl`	Managing the Quality vs. Efficiency Trade-off Using Dynamic Effort Scaling. ACM Trans. Embed. Comput. Syst. Vinay K. Chippa, Kaushik Roy, Srimat T. Chakradhar, Anand Raghunathan
2013	A	`conf`	Multi-level magnetic RAM using domain wall shift for energy-efficient, high-density caches. ISLPED Mrigank Sharad, Rangharajan Venkatesan, Anand Raghunathan, Kaushik Roy
2013	A*	`conf`	Quality programmable vector processors for approximate computing. MICRO Swagath Venkataramani, Vinay K. Chippa, Srimat T. Chakradhar, Kaushik Roy, Anand Raghunathan
2013	—	`conf`	Reading spin-torque memory with spin-torque sensors. NANOARCH Mrigank Sharad, Rangharajan Venkatesan, Xuanyao Fong, Anand Raghunathan, Kaushik Roy
2013	J	`jnl`	Spin Neurons: A Possible Path to Energy-Efficient Neuromorphic Computers. CoRR Mrigank Sharad, Deliang Fan, Kaushik Roy
2013	J	`jnl`	Spintronic Switches for Ultra Low Energy On-Chip and Inter-Chip Current-Mode Interconnects CoRR Mrigank Sharad, Kaushik Roy
2013	A	`conf`	Substitute-and-simplify: a unified design paradigm for approximate and quality configurable circuits. DATE Swagath Venkataramani, Kaushik Roy, Anand Raghunathan
2013	J	`jnl`	Ultra Low Power Associative Computing with Spin Neurons and Resistive Crossbar Memory CoRR Mrigank Sharad, Deliang Fan, Kaushik Roy
2013	A*	`conf`	Ultra low power associative computing with spin neurons and resistive crossbar memory. DAC Mrigank Sharad, Deliang Fan, Kaushik Roy
2013	J	`jnl`	Ultra-low Energy, High Performance and Programmable Magnetic Threshold Logic. CoRR Mrigank Sharad, Deliang Fan, Kaushik Roy
2013	J	`jnl`	Ultra-low Energy, High-Performance Dynamic Resistive Threshold Logic. CoRR Mrigank Sharad, Deliang Fan, Kaushik Roy
2012	A	`conf`	A framework for simulating hybrid MTJ/CMOS circuits: Atoms to system approach. DATE Georgios Panagopoulos, Charles Augustine, Kaushik Roy
2012	A	`conf`	A low-power "near-threshold" epileptic seizure detection processor with multiple algorithm programmability. ISLPED Himanshu Markandeya, Shriram Raghunathan, Pedro P. Irazoqui, Kaushik Roy
2012	J	`jnl`	CLIP: Circuit Level IC Protection Through Direct Injection of Process Variations. IEEE Trans. Very Large Scale Integr. Syst. W. Paul Griffin, Anand Raghunathan, Kaushik Roy
2012	A*	`conf`	Cognitive computing with spin-based neural networks. DAC Mrigank Sharad, Charles Augustine, Georgios Panagopoulos, Kaushik Roy
2012	B	`conf`	Functional analysis of circuits under timing variations. ETS Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, Anand Raghunathan
2012	A*	`conf`	Future cache design using STT MRAMs for improved energy efficiency: devices, circuits and architecture. DAC Sang Phill Park, Sumeet Kumar Gupta, Niladri Narayan Mojumder, Anand Raghunathan, Kaushik Roy
2012	Misc	`conf`	HBIST: An approach towards zero external test cost. VTS Mayur Bubna, Kaushik Roy, Ashish Goel
2012	A	`conf`	High-performance low-energy STT MRAM based on balanced write scheme. ISLPED Dongsoo Lee, Sumeet Kumar Gupta, Kaushik Roy
2012	A	`conf`	Layout-aware optimization of stt mrams. DATE Sumeet Kumar Gupta, Sang Phill Park, Niladri Narayan Mojumder, Kaushik Roy
2012	J	`jnl`	Logic and Memory Design Based on Unequal Error Protection for Voltage-scalable, Robust and Adaptive DSP Systems. J. Signal Process. Syst. Georgios Karakonstantis, Debabrata Mohapatra, Kaushik Roy
2012	Misc	`conf`	Low-Overhead Maximum Power Point Tracking for Micro-Scale Solar Energy Harvesting Systems. VLSI Design Chao Lu, Sang Phill Park, Vijay Raghunathan, Kaushik Roy
2012	J	`jnl`	Low-Power Architecture for Epileptic Seizure Detection Based on Reduced Complexity DWT. ACM J. Emerg. Technol. Comput. Syst. Mrigank Sharad, Sumeet Kumar Gupta, Shriram Raghunathan, Pedro P. Irazoqui, Kaushik Roy
2012	A	`conf`	Modeling, design and cross-layer optimization of polysilicon solar cell based micro-scale energy harvesting systems. ISLPED Elif S. Mungan, Chao Lu, Vijay Raghunathan, Kaushik Roy
2012	C	`conf`	On Modeling and Evaluation of Logic Circuits under Timing Variations. DSD Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, Anand Raghunathan
2012	—	`conf`	Poly-Si Thin Film Transistors: Opportunities for low-cost RF applications. ICICDT Soo Youn Kim, Wing-Fai Loke, Sang Phill Park, Byunghoo Jung, Kaushik Roy
2012	J	`jnl`	Proposal For Neuromorphic Hardware Using Spin Devices CoRR Mrigank Sharad, Charles Augustine, Georgios Panagopoulos, Kaushik Roy
2012	A*	`conf`	SALSA: systematic logic synthesis of approximate circuits. DAC Swagath Venkataramani, Amit Sabne, Vivek Joy Kozhikkottu, Kaushik Roy, Anand Raghunathan
2012	J	`jnl`	Self-Healing Design in Deep Scaled CMOS Technologies. J. Circuits Syst. Comput. Jangjoon Lee, Srikar Bhagavatula, Swarup Bhunia, Kaushik Roy, Byunghoo Jung
2012	J	`jnl`	Soft-Error-Resilient FPGAs Using Built-In 2-D Hamming Product Code. IEEE Trans. Very Large Scale Integr. Syst. Sang Phill Park, Dongsoo Lee, Kaushik Roy
2012	A	`conf`	Spin as state variable for computation: prospects and perspectives. ISLPED Kaushik Roy
2012	B	`conf`	Spin based neuron-synapse module for ultra low power programmable computational networks. IJCNN Mrigank Sharad, Charles Augustine, Georgios Panagopoulos, Kaushik Roy
2012	A	`conf`	TapeCache: a high density, energy efficient cache based on domain wall memory. ISLPED Rangharajan Venkatesan, Vivek Joy Kozhikkottu, Charles Augustine, Arijit Raychowdhury, Kaushik Roy, Anand Raghunathan
2012	—	`conf`	Ultra low energy analog image processing using spin based neurons. NANOARCH Mrigank Sharad, Charles Augustine, Georgios Panagopoulos, Kaushik Roy
2012	J	`jnl`	Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design. IEEE Trans. Very Large Scale Integr. Syst. Jaydeep P. Kulkarni, Kaushik Roy
2012	—	`conf`	Variation-aware and self-healing design methodology for a system-on-chip. LATW Jangjoon Lee, Srikar Bhagavatula, Kaushik Roy, Byunghoo Jung
2012	J	`jnl`	Verifying Reliability (Dagstuhl Seminar 12341). Dagstuhl Reports Görschwin Fey, Masahiro Fujita, Natasa Miskov-Zivanov, Kaushik Roy, Matteo Sonza Reorda
2012	J	`jnl`	Viterbi-Based Efficient Test Data Compression. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Dongsoo Lee, Kaushik Roy
2012	A	`conf`	Write-optimized reliable design of STT MRAM. ISLPED Yusung Kim, Sumeet Kumar Gupta, Sang Phill Park, Georgios Panagopoulos, Kaushik Roy
2011	J	`jnl`	A Priority-Based 6T/8T Hybrid SRAM Architecture for Aggressive Voltage Scaling in Video Applications. IEEE Trans. Circuits Syst. Video Technol. Ik Joon Chang, Debabrata Mohapatra, Kaushik Roy
2011	J	`jnl`	A Read-Disturb-Free, Differential Sensing 1R/1W Port, 8T Bitcell Array. IEEE Trans. Very Large Scale Integr. Syst. Jaydeep P. Kulkarni, Ashish Goel, Patrick Ndai, Kaushik Roy
2011	A	`conf`	Column-selection-enabled 8T SRAM array with ~1R/1W multi-port operation for DVFS-enabled processors. ISLPED Sang Phill Park, Soo Youn Kim, Dongsoo Lee, Jae-Joon Kim, W. Paul Griffin, Kaushik Roy
2011	J	`jnl`	Containing the Nanometer "Pandora-Box": Cross-Layer Design Techniques for Variation Aware Low Power Systems. IEEE J. Emerg. Sel. Topics Circuits Syst. Georgios Karakonstantis, Abhijit Chatterjee, Kaushik Roy
2011	A	`conf`	Design of voltage-scalable meta-functions for approximate computing. DATE Debabrata Mohapatra, Vinay K. Chippa, Anand Raghunathan, Kaushik Roy
2011	A*	`conf`	Dynamic effort scaling: managing the quality-efficiency tradeoff. DAC Vinay K. Chippa, Anand Raghunathan, Kaushik Roy, Srimat T. Chakradhar
2011	J	`jnl`	Efficient Design of Micro-Scale Energy Harvesting Systems. IEEE J. Emerg. Sel. Topics Circuits Syst. Chao Lu, Vijay Raghunathan, Kaushik Roy
2011	—	`conf`	Energy efficient many-core processor for recognition and mining using spin-based memory. NANOARCH Rangharajan Venkatesan, Vinay K. Chippa, Charles Augustine, Kaushik Roy, Anand Raghunathan
2011	J	`jnl`	Guest Editorial Advances in Design of Energy-Efficient Circuits and Systems (Second Issue). IEEE J. Emerg. Sel. Topics Circuits Syst. Enrico Macii, Vijaykrishnan Narayanan, Kaushik Roy
2011	A	`conf`	IMPACT: imprecise adders for low-power approximate computing. ISLPED Vaibhav Gupta, Debabrata Mohapatra, Sang Phill Park, Anand Raghunathan, Kaushik Roy
2011	—	`conf`	Integrated Design & Test: Conquering the Conflicting Requirements of Low-Power, Variation-Tolerance and Test Cost. Asian Test Symposium Ashish Goel, Swaroop Ghosh, Mesut Meterelliyoz, Jeff Parkhurst, Kaushik Roy
2011	—	`ch.`	Low-Power and Variation-Tolerant Application-Specific System Design. Low-Power Variation-Tolerant Design in Nanometer Silicon Georgios Karakonstantis, Kaushik Roy
2011	—	`conf`	Low-power functionality enhanced computation architecture using spin-based devices. NANOARCH Charles Augustine, Georgios Panagopoulos, Behtash Behin-Aein, Srikant Srinivasan, Angik Sarkar, Kaushik Roy
2011	A	`conf`	MACACO: Modeling and analysis of circuits for approximate computing. ICCAD Rangharajan Venkatesan, Amit Agarwal, Kaushik Roy, Anand Raghunathan
2011	Misc	`conf`	Memory-based embedded digital ATE. VTS Dongsoo Lee, Sang Phill Park, Ashish Goel, Kaushik Roy
2011	C	`conf`	Multi-level wordline driver for low power SRAMs in nano-scale CMOS technology. ICCD Farshad Moradi, Georgios Panagopoulos, Georgios Karakonstantis, Dag T. Wisland, Hamid Mahmoodi, Jens Kargaard Madsen, Kaushik Roy
2011	J	`jnl`	Novel Low Overhead Post-Silicon Self-Correction Technique for Parallel Prefix Adders Using Selective Redundancy and Adaptive Clocking. IEEE Trans. Very Large Scale Integr. Syst. Swaroop Ghosh, Kaushik Roy
2011	J	`jnl`	Robust Level Converter for Sub-Threshold/Super-Threshold Operation: 100 mV to 2.5 V. IEEE Trans. Very Large Scale Integr. Syst. Ik Joon Chang, Jae-Joon Kim, Keejong Kim, Kaushik Roy
2011	—	`conf`	Scaled LTPS TFTs for low-cost low-power applications. ISQED Soo Youn Kim, Selin Baytok, Kaushik Roy
2011	A*	`conf`	Significance driven computation on next-generation unreliable platforms. DAC Georgios Karakonstantis, Nikolaos Bellas, Christos D. Antonopoulos, Georgios Tziantzioulis, Vaibhav Gupta, Kaushik Roy
2011	A	`conf`	Stage number optimization for switched capacitor power converters in micro-scale energy harvesting. DATE Chao Lu, Sang Phill Park, Vijay Raghunathan, Kaushik Roy
2011	—	`conf`	Variation-tolerant and self-repair design methodology for low temperature polycrystalline silicon liquid crystal and organic light emitting diode displays. ASP-DAC Chih-Hsiang Ho, Chao Lu, Debabrata Mohapatra, Kaushik Roy
2011	B	`conf`	Viterbi-Based Efficient Test Data Compression. ETS Dongsoo Lee, Kaushik Roy
2011	—	`conf`	Voltage over-scaling: A cross-layer design perspective for energy efficient systems. ECCTD Georgios Karakonstantis, Kaushik Roy
2010	J	`jnl`	A Scalable Circuit-Architecture Co-Design to Improve Memory Yield for High-Performance Processors. IEEE Trans. Very Large Scale Integr. Syst. Patrick Ndai, Ashish Goel, Kaushik Roy
2010	C	`conf`	A self-consistent model to estimate NBTI degradation and a comprehensive on-line system lifetime enhancement technique. IOLTS Georgios Karakonstantis, Charles Augustine, Kaushik Roy
2010	J	`jnl`	ABRM: Adaptive Beta -Ratio Modulation for Process-Tolerant Ultradynamic Voltage Scaling. IEEE Trans. Very Large Scale Integr. Syst. Myeong-Eun Hwang, Kaushik Roy
2010	—	`conf`	Accurate characterization of random process variations using a robust low-voltage high-sensitivity sensor featuring replica-bias circuit. ISSCC Mesut Meterelliyoz, Ashish Goel, Jaydeep P. Kulkarni, Kaushik Roy
2010	A	`conf`	Analysis and design of ultra low power thermoelectric energy harvesting systems. ISLPED Chao Lu, Sang Phill Park, Vijay Raghunathan, Kaushik Roy
2010	J	`jnl`	Analysis of SRAM and eDRAM Cache Memories Under Spatial Temperature Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mesut Meterelliyoz, Jaydeep P. Kulkarni, Kaushik Roy
2010	J	`jnl`	Characterization of Random Process Variations Using Ultralow-Power, High-Sensitivity, Bias-Free Sub-Threshold Process Sensor. IEEE Trans. Circuits Syst. I Regul. Pap. Mesut Meterelliyoz, Peilin Song, Franco Stellari, Jaydeep P. Kulkarni, Kaushik Roy
2010	—	`conf`	Data-dependant sense-amplifier flip-flop for low power applications. CICC Farshad Moradi, Charles Augustine, Ashish Goel, Georgios Karakonstantis, Tuan Vu Cao, Dag T. Wisland, Hamid Mahmoodi, Kaushik Roy
2010	J	`jnl`	Design Paradigm for Robust Spin-Torque Transfer Magnetic RAM (STT MRAM) From Circuit/Architecture Perspective. IEEE Trans. Very Large Scale Integr. Syst. Jing Li, Patrick Ndai, Ashish Goel, Sayeef S. Salahuddin, Kaushik Roy
2010	J	`jnl`	Digital Computation in Subthreshold Region for Ultralow-Power Operation: A Device-Circuit-Architecture Codesign Perspective. Proc. IEEE Sumeet Kumar Gupta, Arijit Raychowdhury, Kaushik Roy
2010	J	`jnl`	Dynamic Bit-Width Adaptation in DCT: An Approach to Trade Off Image Quality and Computation Energy. IEEE Trans. Very Large Scale Integr. Syst. Jongsun Park, Jung Hwan Choi, Kaushik Roy
2010	A	`conf`	Efficient power conversion for ultra low voltage micro scale energy transducers. DATE Chao Lu, Sang Phill Park, Vijay Raghunathan, Kaushik Roy
2010	J	`jnl`	Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive Filtering. J. Signal Process. Syst. Yongtao Wang, Hamid Mahmoodi, Lih-Yih Chiou, Hunsoo Choo, Jongsun Park, Woopyo Jeong, Kaushik Roy
2010	J	`jnl`	Exploring Asynchronous Design Techniques for Process-Tolerant and Energy-Efficient Subthreshold Operation. IEEE J. Solid State Circuits Ik Joon Chang, Sang Phill Park, Kaushik Roy
2010	J	`jnl`	Fast and accurate estimation of SRAM read and hold failure probability using critical point sampling. IET Circuits Devices Syst. Ik Joon Chang, Jongsun Park, Kunhyuk Kang, Kaushik Roy
2010	A	`conf`	HERQULES: system level cross-layer design exploration for efficient energy-quality trade-offs. ISLPED Georgios Karakonstantis, Georgios Panagopoulos, Kaushik Roy
2010	—	`conf`	Improved clock-gating control scheme for transparent pipeline. ASP-DAC Jung Hwan Choi, Byung Guk Kim, Aurobindo Dasgupta, Kaushik Roy
2010	Misc	`conf`	Integrated Systems in the More-than-Moore Era: Designing Low-Cost Energy-Efficient Systems Using Heterogeneous Components. VLSI Design Kaushik Roy, Byunghoo Jung, Anand Raghunathan
2010	A	`conf`	Low-power DWT-based quasi-averaging algorithm and architecture for epileptic seizure detection. ISLPED Himanshu Markandeya, Georgios Karakonstantis, Shriram Raghunathan, Pedro P. Irazoqui, Kaushik Roy
2010	C	`conf`	Maximum power point considerations in micro-scale solar energy harvesting systems. ISCAS Chao Lu, Vijay Raghunathan, Kaushik Roy
2010	—	`conf`	Micro-scale energy harvesting: a system design perspective. ASP-DAC Chao Lu, Vijay Raghunathan, Kaushik Roy
2010	—	`conf`	Multiple-Parameter Side-Channel Analysis: A Non-invasive Hardware Trojan Detection Approach. HOST Seetharam Narasimhan, Rajat Subhra Chakraborty, Dongdong Du, Somnath Paul, Francis G. Wolff, Christos A. Papachristou, Kaushik Roy, Swarup Bhunia
2010	J	`jnl`	On-Chip Variability Sensor Using Phase-Locked Loop for Detecting and Correcting Parametric Timing Failures. IEEE Trans. Very Large Scale Integr. Syst. Kunhyuk Kang, Sang Phill Park, Keejong Kim, Kaushik Roy
2010	J	`jnl`	Parameter Variation Tolerance and Error Resiliency: New Design Paradigm for the Nanoscale Era. Proc. IEEE Swaroop Ghosh, Kaushik Roy
2010	B	`conf`	Parametric failure analysis of embedded SRAMs using fast & accurate dynamic analysis. ETS Elena I. Vatajelu, Georgios Panagopoulos, Kaushik Roy, Joan Figueras
2010	J	`jnl`	Process-Variation Resilient and Voltage-Scalable DCT Architecture for Robust Low-Power Computing. IEEE Trans. Very Large Scale Integr. Syst. Georgios Karakonstantis, Nilanjan Banerjee, Kaushik Roy
2010	A*	`conf`	Scalable effort hardware design: exploiting algorithmic resilience for energy efficiency. DAC Vinay K. Chippa, Debabrata Mohapatra, Anand Raghunathan, Kaushik Roy, Srimat T. Chakradhar
2010	J	`jnl`	Self-Repairing SRAM Using On-Chip Detection and Compensation. IEEE Trans. Very Large Scale Integr. Syst. Niladri Narayan Mojumder, Saibal Mukhopadhyay, Jae-Joon Kim, Ching-Te Chuang, Kaushik Roy
2010	J	`jnl`	Timed Input Pattern Generation for an Accurate Delay Calculation Under Multiple Input Switching. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Seung Hoon Choi, Kunhyuk Kang, Florentin Dartu, Kaushik Roy
2010	J	`jnl`	Trifecta: A Nonspeculative Scheme to Exploit Common, Data-Dependent Subcritical Paths. IEEE Trans. Very Large Scale Integr. Syst. Patrick Ndai, Nauman Rafique, Mithuna Thottethodi, Swaroop Ghosh, Swarup Bhunia, Kaushik Roy
2010	C	`conf`	VEDA: Variation-aware energy-efficient Discrete Wavelet Transform architecture. ICCD Vaibhav Gupta, Georgios Karakonstantis, Debabrata Mohapatra, Kaushik Roy
2010	J	`jnl`	Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance. IEEE Trans. Very Large Scale Integr. Syst. Yiran Chen, Hai Li, Cheng-Kok Koh, Guangyu Sun, Jing Li, Yuan Xie, Kaushik Roy
2010	J	`jnl`	Voltage Scalable High-Speed Robust Hybrid Arithmetic Units Using Adaptive Clocking. IEEE Trans. Very Large Scale Integr. Syst. Swaroop Ghosh, Debabrata Mohapatra, Georgios Karakonstantis, Kaushik Roy
2009	J	`jnl`	A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS. IEEE J. Solid State Circuits Ik Joon Chang, Jae-Joon Kim, Sang Phill Park, Kaushik Roy
2009	—	`conf`	A design methodology and device/circuit/architecture compatible simulation framework for low-power magnetic quantum cellular automata systems. ASP-DAC Charles Augustine, Behtash Behin-Aein, Xuanyao Fong, Kaushik Roy
2009	A*	`conf`	A voltage-scalable & process variation resilient hybrid SRAM architecture for MPEG-4 video processors. DAC Ik Joon Chang, Debabrata Mohapatra, Kaushik Roy
2009	—	`conf`	An alternate design paradigm for robust spin-torque transfer magnetic RAM (STT MRAM) from circuit/architecture perspective. ASP-DAC Jing Li, Patrick Ndai, Ashish Goel, Haixin Liu, Kaushik Roy
2009	Misc	`conf`	Coping with Variations through System-Level Design. VLSI Design Nilanjan Banerjee, Saumya Chandra, Swaroop Ghosh, Sujit Dey, Anand Raghunathan, Kaushik Roy
2009	J	`jnl`	Design Methodology for Low Power and Parametric Robustness Through Output-Quality Modulation: Application to Color-Interpolation Filtering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Nilanjan Banerjee, Georgios Karakonstantis, Jung Hwan Choi, Chaitali Chakrabarti, Kaushik Roy
2009	—	`conf`	Design for burn-in test: a technique for burn-in thermal stability under die-to-die parameter variations. ASP-DAC Mesut Meterelliyoz, Kaushik Roy
2009	—	`conf`	Design in the nano-scale Era: Low-power, reliability, and error resiliency. SoCC Kaushik Roy
2009	A*	`conf`	Device/circuit interactions at 22nm technology node. DAC Kaushik Roy, Jaydeep P. Kulkarni, Sumeet Kumar Gupta
2009	J	`jnl`	Gated Decap: Gate Leakage Control of On-Chip Decoupling Capacitors in Scaled Technologies. IEEE Trans. Very Large Scale Integr. Syst. Yiran Chen, Hai Li, Kaushik Roy, Cheng-Kok Koh
2009	—	`conf`	Impact of SoC power management techniques on verification and testing. ISQED Bhanu Kapoor, Shankar Hemmady, Shireesh Verma, Kaushik Roy, Manuel A. d'Abreu
2009	—	`conf`	PETE: A device/circuit analysis framework for evaluation and comparison of charge based emerging devices. ISQED Charles Augustine, Arijit Raychowdhury, Yunfei Gao, Mark S. Lundstrom, Kaushik Roy
2009	—	`conf`	REad/access-preferred (REAP) SRAM - architecture-aware bit cell design for improved yield and lower VMIN. CICC Ashish Goel, Patrick Ndai, Jaydeep P. Kulkarni, Kaushik Roy
2009	J	`jnl`	Reliability Implications of Bias-Temperature Instability in Digital ICs. IEEE Des. Test Comput. Sang Phill Park, Kunhyuk Kang, Kaushik Roy
2009	A	`conf`	Significance driven computation: a voltage-scalable, variation-aware, quality-tuning motion estimator. ISLPED Debabrata Mohapatra, Georgios Karakonstantis, Kaushik Roy
2009	J	`jnl`	Slope Interconnect Effort: Gate-Interconnect Interdependent Delay Modeling for Early CMOS Circuit Simulation. IEEE Trans. Circuits Syst. I Regul. Pap. Myeong-Eun Hwang, Seong-Ook Jung, Kaushik Roy
2009	—	`conf`	System level DSP synthesis using voltage overscaling, unequal error protection & adaptive quality tuning. SiPS Georgios Karakonstantis, Debabrata Mohapatra, Kaushik Roy
2009	J	`jnl`	Ultra Low-Power Clocking Scheme Using Energy Recovery and Clock Gating. IEEE Trans. Very Large Scale Integr. Syst. Hamid Mahmoodi, Vishy Tirumalashetty, Matthew Cooke, Kaushik Roy
2009	A	`conf`	Ultra low voltage CMOS. ISLPED Kaushik Roy
2009	J	`jnl`	Variation Estimation and Compensation Technique in Scaled LTPS TFT Circuits for Low-Power Low-Cost Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jing Li, Kunhyuk Kang, Kaushik Roy
2009	J	`jnl`	Variation-Aware Low-Power Synthesis Methodology for Fixed-Point FIR Filters. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jung Hwan Choi, Nilanjan Banerjee, Kaushik Roy
2008	—	`conf`	A 135mV 0.13μW process tolerant 6T subthreshold DTMOS SRAM in 90nm technology. CICC Myeong-Eun Hwang, Kaushik Roy
2008	—	`conf`	A 32kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS. ISSCC Ik Joon Chang, Jae-Joon Kim, Sang Phill Park, Kaushik Roy
2008	J	`jnl`	A Low Complexity Reconfigurable DCT Architecture to Trade off Image Quality for Power Consumption. J. Signal Process. Syst. Jongsun Park, Kaushik Roy
2008	J	`jnl`	A Low-Power SRAM Using Bit-Line Charge-Recycling. IEEE J. Solid State Circuits Keejong Kim, Hamid Mahmoodi, Kaushik Roy
2008	A	`conf`	A Novel Low Overhead Fault Tolerant Kogge-Stone Adder Using Adaptive Clocking. DATE Swaroop Ghosh, Patrick Ndai, Kaushik Roy
2008	—	`conf`	A high sensitivity process variation sensor utilizing sub-threshold operation. CICC Mesut Meterelliyoz, Peilin Song, Franco Stellari, Jaydeep P. Kulkarni, Kaushik Roy
2008	J	`jnl`	An On-Chip Test Structure and Digital Measurement Method for Statistical Characterization of Local Random Variability in a Process. IEEE J. Solid State Circuits Saibal Mukhopadhyay, Keunwoo Kim, Keith A. Jenkins, Ching-Te Chuang, Kaushik Roy
2008	J	`jnl`	An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs. ACM J. Emerg. Technol. Comput. Syst. Jing Li, Aditya Bansal, Swaroop Ghosh, Kaushik Roy
2008	J	`jnl`	Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique. J. Electron. Test. Swarup Bhunia, Hamid Mahmoodi, Arijit Raychowdhury, Kaushik Roy
2008	Misc	`conf`	Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry. VTS Niladri Narayan Mojumder, Saibal Mukhopadhyay, Jae-Joon Kim, Ching-Te Chuang, Kaushik Roy
2008	—	`conf`	Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching. ASP-DAC Swaroop Ghosh, Kaushik Roy
2008	—	`conf`	Fault-Tolerance with Graceful Degradation in Quality: A Design Methodology and Its Application to Digital Signal Processing Systems. DFT Nilanjan Banerjee, Charles Augustine, Kaushik Roy
2008	A	`conf`	Low power design under parameter variations. ISLPED Swarup Bhunia, Kaushik Roy
2008	—	`conf`	Low power design under parameter variations. SoCC Swarup Bhunia, Kaushik Roy
2008	A*	`conf`	Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array for yield enhancement. DAC Jing Li, Charles Augustine, Sayeef S. Salahuddin, Kaushik Roy
2008	—	`conf`	NBTI induced performance degradation in logic and memory circuits: how effectively can we approach a reliability solution? ASP-DAC Kunhyuk Kang, Saakshi Gangwal, Sang Phill Park, Kaushik Roy
2008	A	`conf`	O ISLPED Swaroop Ghosh, Jung Hwan Choi, Patrick Ndai, Kaushik Roy
2008	Misc	`conf`	Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies. VLSI Design Aditya Bansal, Jae-Joon Kim, Keunwoo Kim, Saibal Mukhopadhyay, Ching-Te Chuang, Kaushik Roy
2008	—	`conf`	Panel: SoC power management implications on validation and testing. HLDVT Bhanu Kapoor, John Goodenough, Shankar Hemmady, Shireesh Verma, Manuel A. d'Abreu, Kaushik Roy
2008	A	`conf`	Power-Aware Testing and Test Strategies for Low Power Devices. DATE Dimitris Gizopoulos, Kaushik Roy, Patrick Girard, Nicola Nicolici, Xiaoqing Wen
2008	A*	`conf`	Process variation tolerant SRAM array for ultra low voltage applications. DAC Jaydeep P. Kulkarni, Keejong Kim, Sang Phill Park, Kaushik Roy
2008	J	`jnl`	Profit Aware Circuit Design Under Process Variations Considering Speed Binning. IEEE Trans. Very Large Scale Integr. Syst. Animesh Datta, Swarup Bhunia, Jung Hwan Choi, Saibal Mukhopadhyay, Kaushik Roy
2008	J	`jnl`	Reduction of Parametric Failures in Sub-100-nm SRAM Array Using Body Bias. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Saibal Mukhopadhyay, Hamid Mahmoodi, Kaushik Roy
2008	A	`conf`	Soft Errors: System Effects, Protection Techniques and Case Studies. DATE Dimitris Gizopoulos, Kaushik Roy, Subhasish Mitra, Pia N. Sanda
2008	A	`conf`	Thermal analysis of 8-T SRAM for nano-scaled technologies. ISLPED Mesut Meterelliyoz, Jaydeep P. Kulkarni, Kaushik Roy
2008	—	`conf`	Tutorial: SoC Power Management Verification and Testing Issues. MTV Bhanu Kapoor, J. Marc Edwards, Shankar Hemmady, Shireesh Verma, Kaushik Roy
2008	—	`conf`	Variation-tolerant Spin-Torque Transfer (STT) MRAM array for yield enhancement. CICC Jing Li, Haixin Liu, Sayeef S. Salahuddin, Kaushik Roy
2008	J	`jnl`	Within-Die Variation-Aware Scheduling in Superscalar Processors for Improved Throughput. IEEE Trans. Computers Patrick Ndai, Swarup Bhunia, Amit Agarwal, Kaushik Roy
2007	J	`jnl`	A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM. IEEE J. Solid State Circuits Jaydeep P. Kulkarni, Keejong Kim, Kaushik Roy
2007	A	`conf`	A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM. ISLPED Jaydeep P. Kulkarni, Keejong Kim, Kaushik Roy
2007	—	`conf`	A 200mV to 1.2V, 4.4MHz to 6.3GHz, 48×42b 1R/1W programmable register file in 65nm CMOS. ESSCIRC Amit Agarwal, Nilanjan Banerjee, Steven K. Hsu, Ram K. Krishnamurthy, Kaushik Roy
2007	—	`conf`	A High Performance, Scalable Multiplexed Keeper Technique. ISQED Jaydeep P. Kulkarni, Kaushik Roy
2007	A	`conf`	A generic and reconfigurable test paradigm using Low-cost integrated Poly-Si TFTs. ITC Jing Li, Swaroop Ghosh, Kaushik Roy
2007	A	`conf`	A low-power SRAM using bit-line charge-recycling technique. ISLPED Keejong Kim, Hamid Mahmoodi, Kaushik Roy
2007	A	`conf`	A process variation aware low power synthesis methodology for fixed-point FIR filters. ISLPED Nilanjan Banerjee, Jung Hwan Choi, Kaushik Roy
2007	J	`jnl`	Adaptive Supply Voltage for Low-Power Ripple-Carry and Carry-Select Adders. IEICE Trans. Electron. Hiroaki Suzuki, Woopyo Jeong, Kaushik Roy
2007	Misc	`conf`	An Accurate Analytical SNM Modeling Technique for SRAMs Based on Butterworth Filter Function. VLSI Design Qikai Chen, Arjun Guha, Kaushik Roy
2007	—	`conf`	An Optimal Algorithm for Low Power Multiplierless FIR Filter Design using Chebychev Criterion. ICASSP (2) Georgios Karakonstantis, Kaushik Roy
2007	J	`jnl`	CRISTA: A New Paradigm for Low-Power, Variation-Tolerant, and Adaptive Circuit Synthesis Using Critical Path Isolation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Swaroop Ghosh, Swarup Bhunia, Kaushik Roy
2007	J	`jnl`	Carbon Nanotube Electronics: Design of High-Performance and Low-Power Digital Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. Arijit Raychowdhury, Kaushik Roy
2007	A*	`conf`	Characterization and Estimation of Circuit Reliability Degradation under NBTI using On-Line IDDQ Measurement. DAC Kunhyuk Kang, Keejong Kim, Ahmad E. Islam, Muhammad Ashraful Alam, Kaushik Roy
2007	A	`conf`	Characterization of NBTI induced temporal performance degradation in nano-scale SRAM array using IDDQ. ITC Kunhyuk Kang, Muhammad Ashraful Alam, Kaushik Roy
2007	J	`jnl`	Computation Partitioning and Reuse for Power Efficient High Performance Digital Signal Processing. J. Low Power Electron. Nilanjan Banerjee, Kaushik Roy
2007	A	`conf`	Design methodology to trade off power, output quality and error resiliency: application to color interpolation filtering. ICCAD Georgios Karakonstantis, Nilanjan Banerjee, Kaushik Roy, Chaitali Chakrabarti
2007	J	`jnl`	Design of Sigma-Delta Modulators With Arbitrary Transfer Functions. IEEE Trans. Signal Process. Yongtao Wang, Khurram Muhammad, Kaushik Roy
2007	J	`jnl`	Design of a Process Variation Tolerant Self-Repairing SRAM for Yield Enhancement in Nanoscaled CMOS. IEEE J. Solid State Circuits Saibal Mukhopadhyay, Keejong Kim, Hamid Mahmoodi, Kaushik Roy
2007	J	`jnl`	Device-Aware Yield-Centric Dual-V IEEE Trans. Very Large Scale Integr. Syst. Amit Agarwal, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy
2007	J	`jnl`	Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices. Microelectron. J. Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy
2007	A	`conf`	Estimation of statistical variation in temporal NBTI degradation and its impact on lifetime circuit performance. ICCAD Kunhyuk Kang, Sang Phill Park, Kaushik Roy, Muhammad Ashraful Alam
2007	J	`jnl`	Fast Tag Comparator Using Diode Partitioned Domino for 64-bit Microprocessors. IEEE Trans. Circuits Syst. I Regul. Pap. Hiroaki Suzuki, Chris H. Kim, Kaushik Roy
2007	—	`conf`	FinFET Based SRAM Design for Low Standby Power Applications. ISQED Tamer Cakici, Keejong Kim, Kaushik Roy
2007	—	`conf`	FinFET SRAM: Optimizing Silicon Fin Thickness and Fin Ratio to Improve Stability at iso Area. CICC Dheepa Lekshmanan, Aditya Bansal, Kaushik Roy
2007	—	`conf`	Fine-Grained Redundancy in Adders. ISQED Patrick Ndai, Shih-Lien Lu, Dinesh Somasekhar, Kaushik Roy
2007	J	`jnl`	Guest Editorial. IEEE Trans. Circuits Syst. I Regul. Pap. Clifford Lau, Alex Orailoglu, Kaushik Roy
2007	A*	`conf`	High Performance and Low Power Electronics on Flexible Substrate. DAC Jing Li, Kunhyuk Kang, Aditya Bansal, Kaushik Roy
2007	J	`jnl`	Impact of Negative-Bias Temperature Instability in Nanoscale SRAM Array: Modeling and Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kunhyuk Kang, Haldun Kufluoglu, Kaushik Roy, Muhammad Ashraful Alam
2007	A	`conf`	Interactive presentation: Process tolerant beta-ratio modulation for ultra-dynamic voltage scaling. DATE Myeong-Eun Hwang, Tamer Cakici, Kaushik Roy
2007	J	`jnl`	Low-Power and testable circuit synthesis using Shannon decomposition. ACM Trans. Design Autom. Electr. Syst. Swaroop Ghosh, Swarup Bhunia, Kaushik Roy
2007	A	`conf`	Low-overhead circuit synthesis for temperature adaptation using dynamic voltage scheduling. DATE Swaroop Ghosh, Swarup Bhunia, Kaushik Roy
2007	A	`conf`	Low-power process-variation tolerant arithmetic units using input-based elastic clocking. ISLPED Debabrata Mohapatra, Georgios Karakonstantis, Kaushik Roy
2007	C	`conf`	Memories in Scaled Technologies: A Review of Process Induced Failures, Test Methodologies, and Fault Tolerance. DDECS Saibal Mukhopadhyay, Qikai Chen, Kaushik Roy
2007	J	`jnl`	Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits CoRR Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy
2007	J	`jnl`	Modeling and Circuit Synthesis for Independently Controlled Double Gate FinFET Devices. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Animesh Datta, Ashish Goel, R. T. Cakici, Hamid Mahmoodi, Dheepa Lekshmanan, Kaushik Roy
2007	J	`jnl`	Negative Bias Temperature Instability: Estimation and Design for Improved Reliability of Nanoscale Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Bipul Chandra Paul, Kunhyuk Kang, Haldun Kufluoglu, Muhammad Ashraful Alam, Kaushik Roy
2007	A	`conf`	Power dissipation, variations and nanoscale CMOS design: Test challenges and self-calibration/self-repair solutions. ITC Swarup Bhunia, Kaushik Roy
2007	Misc	`conf`	Process Variations and Process-Tolerant Design. VLSI Design Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy
2007	A	`conf`	Process variation tolerant low power DCT architecture. DATE Nilanjan Banerjee, Georgios Karakonstantis, Kaushik Roy
2007	—	`conf`	Process-Tolerant Low-Power Adaptive Pipeline under Scaled-Vdd. CICC Swaroop Ghosh, Pooja Batra, Keejong Kim, Kaushik Roy
2007	J	`jnl`	Self-Consistent Approach to Leakage Power and Temperature Estimation to Predict Thermal Runaway in FinFET Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jung Hwan Choi, Aditya Bansal, Mesut Meterelliyoz, Jayathi Murthy, Kaushik Roy
2007	A	`conf`	Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gates. ISLPED Myeong-Eun Hwang, Seong-Ook Jung, Kaushik Roy
2007	—	`conf`	Statistical Characterization and On-Chip Measurement Methods for Local Random Variability of a Process Using Sense-Amplifier-Based Test Structure. ISSCC Saibal Mukhopadhyay, Keunwoo Kim, Keith A. Jenkins, Ching-Te Chuang, Kaushik Roy
2007	J	`jnl`	Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies CoRR Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Nilanjan Banerjee, Kaushik Roy
2007	A	`conf`	The effect of process variation on device temperature in FinFET circuits. ICCAD Jung Hwan Choi, Jayathi Murthy, Kaushik Roy
2007	C	`conf`	Tolerance to Small Delay Defects by Adaptive Clock Stretching. IOLTS Swaroop Ghosh, Patrick Ndai, Swarup Bhunia, Kaushik Roy
2007	A*	`conf`	Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop. DAC Kunhyuk Kang, Keejong Kim, Kaushik Roy
2006	—	`conf`	A CMOS Thermal Sensor and Its Applications in Temperature Adaptive Design. ISQED Qikai Chen, Mesut Meterelliyoz, Kaushik Roy
2006	J	`jnl`	A Leakage-Tolerant Low-Swing Circuit Style in Partially Depleted Silicon-on-Insulator CMOS Technologies. IEEE Trans. Very Large Scale Integr. Syst. Jae-Joon Kim, Kaushik Roy
2006	J	`jnl`	A Novel Delay Fault Testing Methodology Using Low-Overhead Built-In Delay Sensor. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy
2006	J	`jnl`	A Power Delivery and Decoupling Network Minimizing Ohmic Loss and Supply Voltage Variation in Silicon Nanoscale Technologies. IEEE Trans. Very Large Scale Integr. Syst. Mark M. Budnik, Kaushik Roy
2006	A*	`conf`	A fully physical model for leakage distribution under process variations in Nanoscale double-gate CMOS. DAC Hari Ananthan, Kaushik Roy
2006	A*	`conf`	A high density, carbon nanotube capacitor for decoupling applications. DAC Mark M. Budnik, Arijit Raychowdhury, Aditya Bansal, Kaushik Roy
2006	A	`conf`	A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolation. ICCAD Swaroop Ghosh, Swarup Bhunia, Kaushik Roy
2006	J	`jnl`	A novel high-performance and robust sense amplifier using independent gate control in sub-50-nm double-gate MOSFET. IEEE Trans. Very Large Scale Integr. Syst. Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy
2006	J	`jnl`	A process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuits. IEEE Trans. Very Large Scale Integr. Syst. Chris H. Kim, Kaushik Roy, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar
2006	J	`jnl`	An Analytical Fringe Capacitance Model for Interconnects Using Conformal Mapping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Aditya Bansal, Bipul Chandra Paul, Kaushik Roy
2006	A	`conf`	Analysis of super cut-off transistors for ultralow power digital logic circuits. ISLPED Arijit Raychowdhury, Xuanyao Fong, Qikai Chen, Kaushik Roy
2006	A	`conf`	Circuit-aware device design methodology for nanometer technologies: a case study for low power SRAM design. DATE Qikai Chen, Saibal Mukhopadhyay, Aditya Bansal, Kaushik Roy
2006	—	`conf`	Compact thermal models for estimation of temperature-dependent power/performance in FinFET technology. ASP-DAC Aditya Bansal, Mesut Meterelliyoz, Siddharth Singh, Jung Hwan Choi, Jayathi Murthy, Kaushik Roy
2006	C	`conf`	Delay Fault Localization in Test-Per-Scan BIST Using Built-In Delay Sensor. IOLTS Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy
2006	J	`jnl`	Delay Modeling and Statistical Design of Pipelined Circuit Under Process Variation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy
2006	Misc	`conf`	Double-Gate SOI Devices for Low-Power and High-Performance Applications. VLSI Design Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici
2006	A	`conf`	Dynamic bit-width adaptation in DCT: image quality versus computation energy trade-off. DATE Jongsun Park, Jung Hwan Choi, Kaushik Roy
2006	C	`conf`	Efficient Transistor-Level Sizing Technique under Temporal Performance Degradation due to NBTI. ICCD Kunhyuk Kang, Haldun Kufluoglu, Muhammad Ashraful Alam, Kaushik Roy
2006	J	`jnl`	Efficient modeling of 1/f IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jongsun Park, Khurram Muhammad, Kaushik Roy
2006	J	`jnl`	Guest Editorial. Integr. Kaushik Roy
2006	J	`jnl`	Impact of Body Bias on Delay Fault Testing of Sub-100 nm CMOS Circuits. J. Electron. Test. Bipul C. Paul, Kaushik Roy
2006	—	`conf`	Integrated MEMS Switches for Leakage Control of Battery Operated Systems. CICC Arijit Raychowdhury, Jeong-Il Kim, Dimitrios Peroulis, Kaushik Roy
2006	J	`jnl`	Layout-driven architecture synthesis for high-speed digital filters. IEEE Trans. Very Large Scale Integr. Syst. Dongku Kang, Hunsoo Choo, Khurram Muhammad, Kaushik Roy
2006	J	`jnl`	Leakage Power Analysis and Reduction for Nanoscale Circuits. IEEE Micro Amit Agarwal, Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy, Chris H. Kim
2006	A	`conf`	Leakage power dependent temperature estimation to predict thermal runaway in FinFET circuits. ICCAD Jung Hwan Choi, Aditya Bansal, Mesut Meterelliyoz, Jayathi Murthy, Kaushik Roy
2006	A	`conf`	Low power synthesis of dynamic logic circuits using fine-grained clock gating. DATE Nilanjan Banerjee, Kaushik Roy, Hamid Mahmoodi-Meimand, Swarup Bhunia
2006	—	`conf`	Low-Power and Process Variation Tolerant Memories in sub-90nm Technologies. SoCC Saibal Mukhopadhyay, Swaroop Ghosh, Keejong Kim, Kaushik Roy
2006	—	`conf`	Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability. ASP-DAC Ashish Goel, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy
2006	J	`jnl`	Low-power design techniques for scaled technologies. Integr. Bipul Chandra Paul, Amit Agarwal, Kaushik Roy
2006	—	`conf`	Minimizing Ohmic Loss in Future Processor IR Events. ISQED Mark M. Budnik, Kaushik Roy
2006	A	`conf`	Minimizing ohmic loss and supply voltage variation using a novel distributed power supply network. DATE Mark M. Budnik, Kaushik Roy
2006	J	`jnl`	Modeling and Analysis of Leakage Currents in Double-Gate Technologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang, Kaushik Roy
2006	J	`jnl`	Modeling and analysis of loading effect on leakage of nanoscaled bulk-CMOS logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy
2006	J	`jnl`	Modeling of metallic carbon-nanotube interconnects for circuit simulations and a comparison with Cu interconnects for scaled technologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Arijit Raychowdhury, Kaushik Roy
2006	J	`jnl`	Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis. IEEE Trans. Very Large Scale Integr. Syst. Nilanjan Banerjee, Arijit Raychowdhury, Kaushik Roy, Swarup Bhunia, Hamid Mahmoodi
2006	—	`conf`	Optimization of Surface Orientation for High-Performance, Low-Power and Robust FinFET SRAM. CICC Saakshi Gangwal, Saibal Mukhopadhyay, Kaushik Roy
2006	J	`jnl`	PVT-aware leakage reduction for on-die caches with improved read stability. IEEE J. Solid State Circuits Chris Hyung-Il Kim, Jae-Joon Kim, Ik-Joon Chang, Kaushik Roy
2006	—	`conf`	Process Variation: Its Impact on the Design and Test of CMOS Circuits. LATW Kaushik Roy
2006	A	`conf`	Robust level converter design for sub-threshold logic. ISLPED Ik Joon Chang, Jae-Joon Kim, Kaushik Roy
2006	—	`conf`	SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar processor design. ASP-DAC Hai Li, Yiran Chen, Kaushik Roy, Cheng-Kok Koh
2006	—	`conf`	SRAMs in Scaled Technologies under Process Variations: Failure Mechanisms, Test & Variation Tolerant Design. CICC Saibal Mukhopadhyay, Amit Agarwal, Qikai Chen, Kaushik Roy
2006	A*	`conf`	Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM. DAC Swaroop Ghosh, Saibal Mukhopadhyay, Keejong Kim, Kaushik Roy
2006	—	`conf`	Speed binning aware design methodology to improve profit under parameter variations. ASP-DAC Animesh Datta, Swarup Bhunia, Jung Hwan Choi, Saibal Mukhopadhyay, Kaushik Roy
2006	J	`jnl`	Statistical timing analysis using levelized covariance propagation considering systematic and random variations of process parameters. ACM Trans. Design Autom. Electr. Syst. Kunhyuk Kang, Bipul C. Paul, Kaushik Roy
2006	A	`conf`	Temporal performance degradation under NBTI: estimation and design for improved reliability of nanoscale circuits. DATE Bipul Chandra Paul, Kunhyuk Kang, Haldun Kufluoglu, Muhammad Ashraful Alam, Kaushik Roy
2006	J	`jnl`	Test Consideration for Nanometer-Scale CMOS Circuits. IEEE Des. Test Comput. Kaushik Roy, T. M. Mak, Kwang-Ting (Tim) Cheng
2006	A	`conf`	Ultralow power computing with sub-threshold leakage: a comparative study of bulk and SOI technologies. DATE Arijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy
2005	C	`conf`	A Feasibility Study of Subthreshold SRAM Across Technology Generations. ICCD Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy
2005	A	`conf`	A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application. DATE Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy
2005	C	`conf`	A Novel On-Chip Delay Measurement Hardware for Efficient Speed-Binning. IOLTS Arijit Raychowdhury, Swaroop Ghosh, Kaushik Roy
2005	—	`conf`	A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks. ISQED Animesh Datta, Swarup Bhunia, Nilanjan Banerjee, Kaushik Roy
2005	C	`conf`	A Soft Error Monitor Using Switching Current Detection. ICCD Patrick Ndai, Amit Agarwal, Qikai Chen, Kaushik Roy
2005	—	`conf`	A Statistical Approach to Area-Constrained Yield Enhancement for Pipelined Circuits under Parameter Variations. Asian Test Symposium Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy
2005	J	`jnl`	A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations. IEEE Trans. Very Large Scale Integr. Syst. Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy
2005	A	`conf`	A leakage control system for thermal stability during burn-in test. ITC Mesut Meterelliyoz, Hamid Mahmoodi, Kaushik Roy
2005	—	`conf`	A new reduced-complexity sphere decoder with true lattice-boundary-awareness for multi-antenna systems. ISCAS (5) Yongtao Wang, Kaushik Roy
2005	B	`conf`	A novel delay fault testing methodology using on-chip low-overhead delay measurement hardware at strategic probe points. ETS Arijit Raychowdhury, Swaroop Ghosh, Swarup Bhunia, Debjyoti Ghosh, Kaushik Roy
2005	—	`conf`	A novel low-complexity method for parallel multiplierless implementation of digital FIR filters. ISCAS (3) Yongtao Wang, Kaushik Roy
2005	A*	`conf`	A novel synthesis approach for active leakage power reduction using dynamic supply gating. DAC Swarup Bhunia, Nilanjan Banerjee, Qikai Chen, Hamid Mahmoodi-Meimand, Kaushik Roy
2005	J	`jnl`	A novel wavelet transform-based transient current analysis for fault detection and localization. IEEE Trans. Very Large Scale Integr. Syst. Swarup Bhunia, Kaushik Roy
2005	J	`jnl`	A process-tolerant cache architecture for improved yield in nanoscale technologies. IEEE Trans. Very Large Scale Integr. Syst. Amit Agarwal, Bipul Chandra Paul, Hamid Mahmoodi-Meimand, Animesh Datta, Kaushik Roy
2005	A	`conf`	Accurate estimation and modeling of total chip leakage considering inter- & intra-die process variations. ICCAD Amit Agarwal, Kunhyuk Kang, Kaushik Roy
2005	J	`jnl`	Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy
2005	A	`conf`	An 8.3GHz dual supply/threshold optimized 32b integer ALU-register file loop in 90nm CMOS. ISLPED Steven Hsu, Amit Agarwal, Kaushik Roy, Ram Krishnamurthy, Shekhar Borkar
2005	—	`conf`	Asymmetric halo CMOSFET to reduce static power dissipation with improved performance. ISCAS (1) Aditya Bansal, Kaushik Roy
2005	J	`jnl`	CSDC: a new complexity reduction technique for multiplierless implementation of digital FIR filters. IEEE Trans. Circuits Syst. I Regul. Pap. Yongtao Wang, Kaushik Roy
2005	A	`conf`	Cascaded carry-select adder (C ISLPED Yiran Chen, Hai Li, Kaushik Roy, Cheng-Kok Koh
2005	J	`jnl`	Combined circuit and architectural level variable supply-voltage scaling for low power. IEEE Trans. Very Large Scale Integr. Syst. Hai Li, Chen-Yong Cher, Kaushik Roy, T. N. Vijaykumar
2005	J	`jnl`	Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation. IEEE Trans. Very Large Scale Integr. Syst. Arijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy
2005	J	`jnl`	Current demand balancing: a technique for minimization of current surge in high performance clock-gated microprocessors. IEEE Trans. Very Large Scale Integr. Syst. Yiran Chen, Kaushik Roy, Cheng-Kok Koh
2005	J	`jnl`	Defect Oriented Testing of Analog Circuits Using Wavelet Analysis of Dynamic Supply Current. J. Electron. Test. Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy
2005	—	`conf`	Design of High Performance Sense Amplifier Using Independent Gate Control in sub-50nm Double-Gate MOSFET. ISQED Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy
2005	—	`conf`	Design of sigma-delta modulators with arbitrary transfer functions. ICASSP (5) Yongtao Wang, Khurram Muhammad, Kaushik Roy
2005	A	`conf`	Double-gate SOI devices for low-power and high-performance applications. ICCAD Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici
2005	A	`conf`	Effectiveness of low power dual-V ISLPED Amit Agarwal, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy
2005	J	`jnl`	Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations. IEEE Trans. Very Large Scale Integr. Syst. Qikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy
2005	—	`conf`	Energy recovery clocked dynamic logic. ACM Great Lakes Symposium on VLSI Matthew Cooke, Hamid Mahmoodi-Meimand, Qikai Chen, Kaushik Roy
2005	J	`jnl`	Estimation of delay variations due to random-dopant fluctuations in nanoscale CMOS circuits. IEEE J. Solid State Circuits Hamid Mahmoodi, Saibal Mukhopadhyay, Kaushik Roy
2005	—	`conf`	Fast and accurate estimation of nano-scaled SRAM read failure probability using critical point sampling. CICC Ik Joon Chang, Kunhyuk Kang, Saibal Mukhopadhyay, Chris H. Kim, Kaushik Roy
2005	J	`jnl`	Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current. J. Electron. Test. Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy
2005	J	`jnl`	GAARP: A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks. IEEE Trans. Computers Swarup Bhunia, Animesh Datta, Nilanjan Banerjee, Kaushik Roy
2005	—	`conf`	Gated Decap: gate leakage control of on-chip decoupling capacitors in scaled technologies. CICC Yiran Chen, Hai Li, Kaushik Roy, Cheng-Kok Koh
2005	J	`jnl`	High-performance low-power dual transition preferentially sized (DTPS) logic. IEEE J. Solid State Circuits Woopyo Jeong, Kaushik Roy
2005	—	`conf`	Joint control of communication subsystems for low-energy image transmission. ICASSP (3) Hunsoo Choo, Kaushik Roy
2005	—	`conf`	Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM. Asian Test Symposium Saibal Mukhopadhyay, Arijit Raychowdhury, Hamid Mahmoodi-Meimand, Kaushik Roy
2005	J	`jnl`	Low-power scan design using first-level supply gating. IEEE Trans. Very Large Scale Integr. Syst. Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Saibal Mukhopadhyay, Kaushik Roy
2005	—	`conf`	Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits. ISQED Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy
2005	A	`conf`	Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits. DATE Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy
2005	Misc	`conf`	Modeling and Testing of SRAM for New Failure Mechanisms Due to Process Variations in Nanoscale CMOS. VTS Qikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy
2005	A	`conf`	Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits. ISLPED Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang, Kaushik Roy
2005	J	`jnl`	Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy
2005	C	`conf`	Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis. ICCD Nilanjan Banerjee, Arijit Raychowdhury, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy
2005	—	`conf`	Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning. ISQED Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Kaushik Roy
2005	—	`conf`	Power Supply Noise-Aware Scheduling and Allocation for DSP Synthesis. ISQED Dongku Kang, Yiran Chen, Kaushik Roy
2005	A	`ed.`	Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005 ISLPED Kaushik Roy, Vivek Tiwari
2005	C	`conf`	Process Variation Tolerant Online Current Monitor for Robust Systems. IOLTS Qikai Chen, Saibal Mukhopadhyay, Hamid Mahmoodi, Kaushik Roy
2005	J	`jnl`	Process variation in embedded memories: failure analysis and variation aware architecture. IEEE J. Solid State Circuits Amit Agarwal, Bipul C. Paul, Saibal Mukhopadhyay, Kaushik Roy
2005	A	`conf`	Reliable and self-repairing SRAM in nano-scale technologies using leakage and delay monitoring. ITC Saibal Mukhopadhyay, Kunhyuk Kang, Hamid Mahmoodi, Kaushik Roy
2005	C	`conf`	Self Calibrating Circuit Design for Variation Tolerant VLSI Systems. IOLTS Chris H. Kim, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar, Kaushik Roy
2005	—	`conf`	Shannon Expansion Based Supply-Gated Logic for Improved Power and Testability. Asian Test Symposium Swaroop Ghosh, Swarup Bhunia, Kaushik Roy
2005	A	`conf`	Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies. DATE Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Nilanjan Banerjee, Kaushik Roy
2005	A	`conf`	Statistical Timing Analysis using Levelized Covariance Propagation. DATE Kunhyuk Kang, Bipul Chandra Paul, Kaushik Roy
2005	J	`jnl`	Synthesis of application-specific highly efficient multi-mode cores for embedded systems. ACM Trans. Embed. Comput. Syst. Lih-Yih Chiou, Swarup Bhunia, Kaushik Roy
2005	J	`jnl`	Synthesis of skewed logic circuits. ACM Trans. Design Autom. Electr. Syst. Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy
2005	—	`conf`	TFT-LCD Application Specific Low Power SRAM Using Charge-Recycling Technique. ISQED Keejong Kim, Chris H. Kim, Kaushik Roy
2005	C	`conf`	Yield Prediction of High Performance Pipelined Circuit with Respect to Delay Failures in Sub-100nm Technology. IOLTS Animesh Datta, Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy
2004	A*	`conf`	A Novel Bitstream Level Joint Channel Error Concealment Scheme for Realtime Video over Wireless Networks. INFOCOM Xiaowei Ding, Kaushik Roy
2004	C	`conf`	A Novel Fault Tolerant Cache to Improve Yield in Nanometer Technologies. IOLTS Amit Agarwal, Bipul Chandra Paul, Kaushik Roy
2004	C	`conf`	A Novel Low-Power Scan Design Technique Using Supply Gating. ICCD Swarup Bhunia, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Debjyoti Ghosh, Kaushik Roy
2004	—	`conf`	A Novel Multiple-Valued Logic Design Using Ballistic Carbon Nanotube FETs. ISMVL Arijit Raychowdhury, Kaushik Roy
2004	C	`conf`	A Technique to Reduce Power and Test Application Time in BIST. IOLTS Debjyoti Ghosh, Swarup Bhunia, Kaushik Roy
2004	A	`conf`	A circuit model for carbon nanotube interconnects: comparative study with Cu interconnects for scaled technologies. ICCAD Arijit Raychowdhury, Kaushik Roy
2004	J	`jnl`	A circuit-compatible model of ballistic carbon nanotube field-effect transistors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy
2004	—	`conf`	A leakage-tolerant low-leakage register file with conditional sleep transistor. SoCC Amit Agarwal, Kaushik Roy, Ram K. Krishnamurthy
2004	—	`conf`	A low power reconfigurable DCT architecture to trade off image quality for computational complexity. ICASSP (5) Jongsun Park, Kaushik Roy
2004	—	`conf`	Adaptive supply voltage technique for low swing interconnects. ASP-DAC Woopyo Jeong, Bipul Chandra Paul, Kaushik Roy
2004	J	`jnl`	Complexity reduction of digital filters using shift inclusive differential coefficients. IEEE Trans. Signal Process. Hunsoo Choo, Khurram Muhammad, Kaushik Roy
2004	J	`jnl`	Computation sharing programmable FIR filter for low-power and high-performance applications. IEEE J. Solid State Circuits Jongsun Park, Woopyo Jeong, Hamid Mahmoodi-Meimand, Yongtao Wang, Hunsoo Choo, Kaushik Roy
2004	J	`jnl`	DCG: deterministic clock-gating for low-power microprocessor design. IEEE Trans. Very Large Scale Integr. Syst. Hai Li, Swarup Bhunia, Yiran Chen, Kaushik Roy, T. N. Vijaykumar
2004	—	`conf`	Data-retention flip-flops for power-down applications. ISCAS (2) Hamid Mahmoodi-Meimand, Kaushik Roy
2004	A	`conf`	Device optimization for ultra-low power digital sub-threshold operation. ISLPED Bipul Chandra Paul, Arijit Raychowdhury, Kaushik Roy
2004	J	`jnl`	Diode-footed domino: a leakage-tolerant high fan-in dynamic circuit design style. IEEE Trans. Circuits Syst. I Regul. Pap. Hamid Mahmoodi-Meimand, Kaushik Roy
2004	—	`conf`	Dual-edge triggered level converting flip-flops. ISCAS (2) Hamid Mahmoodi-Meimand, Kaushik Roy
2004	—	`conf`	Effectiveness of energy recovery techniques in reducing on-chip power density in molecular nano-technologies. ISCAS (3) Myeong-Eun Hwang, Arijit Raychowdhury, Kaushik Roy
2004	—	`conf`	Efficient Communication Channel Utilization for Mapping FFT onto Mesh Array. Communications in Computing Cheng-Yi Chen, Soonkeon Kwon, Kaushik Roy
2004	J	`jnl`	Enhancing Yield at the End of the Technology Roadmap. IEEE Des. Test Comput. Naran Sirisantana, Bipul Chandra Paul, Kaushik Roy
2004	—	`conf`	Estimation of delay variations due to random-dopant fluctuations in nano-scaled CMOS circuits. CICC Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Kaushik Roy
2004	—	`conf`	FinFET SRAM - Device and Circuit Design Considerations. ISQED Hari Ananthan, Aditya Bansal, Kaushik Roy
2004	—	`conf`	First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique. DFT Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy
2004	C	`conf`	Floorplan-Aware Low-Complexity Digital Filter Synthesis for Low-Power & High-Speed. ICCD Dongku Kang, Hunsoo Choo, Kaushik Roy
2004	—	`conf`	Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current. ISQED Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy
2004	—	`conf`	Hardware architecture and VLSI implementation of a low-power high-performance polyphase channelizer with applications to subband adaptive filtering. ICASSP (5) Yongtao Wang, Hamid Mahmoodi, Lih-Yih Chiou, Hunsoo Choo, Jongsun Park, Woopyo Jeong, Kaushik Roy
2004	A	`conf`	Impact of Body Bias on Delay Fault Testing of Nanoscale CMOS Circuits. ITC Bipul Chandra Paul, Cassondra Neau, Kaushik Roy
2004	A	`conf`	Larger-than-vdd forward body bias in sub-0.5V nanoscale CMOS. ISLPED Hari Ananthan, Chris H. Kim, Kaushik Roy
2004	A*	`conf`	Leakage in nano-scale technologies: mechanisms, impact and design considerations. DAC Amit Agarwal, Chris H. Kim, Saibal Mukhopadhyay, Kaushik Roy
2004	J	`jnl`	Low-Power Design Using Multiple Channel Lengths and Oxide Thicknesses. IEEE Des. Test Comput. Naran Sirisantana, Kaushik Roy
2004	—	`conf`	Low-Power Design. ISQED Kaushik Roy
2004	A	`conf`	Low-power carry-select adder using adaptive supply voltage based on input vector patterns. ISLPED Hiroaki Suzuki, Woopyo Jeong, Kaushik Roy
2004	Misc	`conf`	Modeling and Estimation of Leakage in Sub-90nm Devices. VLSI Design Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy
2004	A*	`conf`	Novel sizing algorithm for yield improvement under process variation in nanometer technology. DAC Seung Hoon Choi, Bipul Chandra Paul, Kaushik Roy
2004	—	`conf`	Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor. ASP-DAC Yiran Chen, Kaushik Roy, Cheng-Kok Koh
2004	A	`ed.`	Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004 ISLPED Rajiv V. Joshi, Kiyoung Choi, Vivek Tiwari, Kaushik Roy
2004	—	`conf`	Process variation in nano-scale memories: failure analysis and process tolerant architecture. CICC Amit Agarwal, Bipul C. Paul, Kaushik Roy
2004	—	`conf`	Simultaneous Multiple-Vdd Scheduling and Allocation for Partitioned Floorplan. ISQED Dongku Kang, Mark C. Johnson, Kaushik Roy
2004	A	`conf`	Statistical design and optimization of SRAM cell for yield enhancement. ICCAD Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy
2004	A	`conf`	Trim Bit Setting of Analog Filters Using Wavelet-Based Supply Current Analysis. DATE Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy
2003	A	`conf`	A New Crosstalk Noise Model for DOMINO Logic Circuits. DATE Seung Hoon Choi, Kaushik Roy
2003	A	`conf`	A forward body-biased low-leakage SRAM cache: device and architecture considerations. ISLPED Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy
2003	—	`conf`	A logic-aware layout methodology to enhance the noise immunity of domino circuits. ISCAS (5) Yonghee Im, Kaushik Roy
2003	—	`conf`	A metric for analyzing effective on-chip inductive coupling. ASP-DAC Guoan Zhong, Cheng-Kok Koh, Kaushik Roy
2003	A	`conf`	A noise tolerant cache design to reduce gate and sub-threshold leakage in the nanometer regime. ISLPED Amit Agarwal, Kaushik Roy
2003	J	`jnl`	A single-V IEEE J. Solid State Circuits Amit Agarwal, Hai Li, Kaushik Roy
2003	—	`conf`	A time borrowing selectively clocked skewed logic for high-performance circuits in scaled technologies. ESSCIRC Naran Sirisantana, Kaushik Roy
2003	A*	`conf`	Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling. DAC Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy
2003	A*	`conf`	An adaptive window-based susceptance extraction and its efficient implementation. DAC Guoan Zhong, Cheng-Kok Koh, Venkataramanan Balakrishnan, Kaushik Roy
2003	Misc	`conf`	Design of Deep Sub-Micron CMOS Circuits. VLSI Design Rajiv V. Joshi, Kaushik Roy
2003	A*	`conf`	Deterministic Clock Gating for Microprocessor Power Reduction. HPCA Hai Li, Swarup Bhunia, Yiran Chen, T. N. Vijaykumar, Kaushik Roy
2003	—	`conf`	Efficient generation of 1/f CICC Jongsun Park, Khurram Muhammad, Kaushik Roy
2003	Misc	`conf`	Embedded Tutorial: Test Consideration for Nanometer Scale CMOS Circuits. VTS Kaushik Roy, T. M. Mak, Kwang-Ting Cheng
2003	A	`conf`	Energy recovery clocking scheme and flip-flops for ultra low-energy applications. ISLPED Matthew Cooke, Hamid Mahmoodi-Meimand, Kaushik Roy
2003	—	`ch.`	Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology. Embedded Software for SoC Amit Agarwal, Kaushik Roy, T. N. Vijaykumar
2003	A	`conf`	Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology. DATE Amit Agarwal, Kaushik Roy, T. N. Vijaykumar
2003	J	`jnl`	Gate leakage reduction for scaled devices using transistor stacking. IEEE Trans. Very Large Scale Integr. Syst. Saibal Mukhopadhyay, Cassondra Neau, R. T. Cakici, Amit Agarwal, Chris H. Kim, Kaushik Roy
2003	J	`jnl`	High-performance FIR filter design based on sharing multiplication. IEEE Trans. Very Large Scale Integr. Syst. Jongsun Park, Khurram Muhammad, Kaushik Roy
2003	—	`conf`	Integer linear programming-based synthesis of skewed logic circuits. ASP-DAC Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy
2003	A	`conf`	Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors. ISLPED Yiran Chen, Kaushik Roy, Cheng-Kok Koh
2003	—	`conf`	LALM: A Logic-Aware Layout Methodology to Enhance the Noise Immunity of Domino Circuits. ISVLSI Yonghee Im, Kaushik Roy
2003	C	`conf`	Low Power Adder with Adaptive Supply Voltage. ICCD Hiroaki Suzuki, Woopyo Jeong, Kaushik Roy
2003	A	`conf`	MRPF: An Architectural Transformation for Synthesis of High-Performance and Low-Power Digital Filters. DATE Hunsoo Choo, Khurram Muhammad, Kaushik Roy
2003	A	`conf`	Modeling and estimation of total leakage current in nano-scaled CMOS devices considering the effect of parameter variation. ISLPED Saibal Mukhopadhyay, Kaushik Roy
2003	A	`conf`	Modeling of Ballistic Carbon Nanotube Field Effect Transistors for Efficient Circuit Simulation. ICCAD Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy
2003	—	`conf`	Multiple Scan Chain Design Technique for Power Reduction during Test Application in BIST. DFT Debjyoti Ghosh, Swarup Bhunia, Kaushik Roy
2003	C	`conf`	Multiple-Vdd Scheduling/Allocation for Partitioned Floorplan. ICCD Dongku Kang, Mark C. Johnson, Kaushik Roy
2003	J	`jnl`	Multiple-parameter CMOS IC testing with increased sensitivity for I IEEE Trans. Very Large Scale Integr. Syst. Ali Keshavarzi, Kaushik Roy, Charles F. Hawkins, Vivek De
2003	J	`jnl`	On-chip interconnect modeling by wire duplication. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Guoan Zhong, Cheng-Kok Koh, Kaushik Roy
2003	A	`conf`	Optimal body bias selection for leakage improvement and process compensation over different technology generations. ISLPED Cassondra Neau, Kaushik Roy
2003	—	`conf`	Robust high-performance low-power carry select adder. ASP-DAC Woopyo Jeong, Kaushik Roy
2003	A	`conf`	Selectively Clocked CMOS Logic Style for Low-Power Noise-Immune Operations in Scaled Technologies. DATE Naran Sirisantana, Kaushik Roy
2003	A	`conf`	Synthesis of Application-Specific Highly-Efficient Multi-Mode Systems for Low-Power Applications. DATE Lih-Yih Chiou, Swarup Bhunia, Kaushik Roy
2003	J	`jnl`	Two's complement computation sharing multiplier and its applications to high performance DFE. IEEE Trans. Signal Process. Hunsoo Choo, Khurram Muhammad, Kaushik Roy
2003	J	`jnl`	Ultra-low-power DLMS adaptive filter for hearing aid applications. IEEE Trans. Very Large Scale Integr. Syst. Chris Hyung-Il Kim, Hendrawan Soeleman, Kaushik Roy
2003	A*	`conf`	VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power. MICRO Hai Li, Chen-Yong Cher, T. N. Vijaykumar, Kaushik Roy
2002	—	`conf`	A High Performance IDDQ Testable Cache for Scaled CMOS Technologies. Asian Test Symposium Swarup Bhunia, Hai Li, Kaushik Roy
2002	J	`jnl`	A graph theoretic approach for synthesizing very low-complexityhigh-speed digital filters. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Khurram Muhammad, Kaushik Roy
2002	A*	`conf`	A novel wavelet transform based transient current analysis for fault detection and localization. DAC Swarup Bhunia, Kaushik Roy, Jaume Segura
2002	A*	`conf`	DRG-cache: a data retention gated-ground cache for low power. DAC Amit Agarwal, Hai Li, Kaushik Roy
2002	J	`jnl`	Decoupling capacitance allocation and its application topower-supply noise-aware floorplanning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh
2002	—	`conf`	Dynamic Noise Analysis with Capacitive and Inductive Coupling. ASP-DAC/VLSI Design Seung Hoon Choi, Bipul Chandra Paul, Kaushik Roy
2002	Misc	`conf`	Dynamic Supply Current Testing of Analog Circuits Using Wavelet Transform. VTS Swarup Bhunia, Kaushik Roy
2002	A	`conf`	Dynamic VTH Scaling Scheme for Active Leakage Power Reduction. DATE Chris H. Kim, Kaushik Roy
2002	A	`conf`	Dynamic Vt SRAM: a leakage tolerant cache memory for low voltage microprocessors. ISLPED Chris H. Kim, Kaushik Roy
2002	A	`conf`	Fault Detection and Diagnosis Using Wavelet Based Transient Current Analysis. DATE Swarup Bhunia, Kaushik Roy
2002	A	`conf`	High performance and low power FIR filter design based on sharing multiplication. ISLPED Jongsun Park, Woopyo Jeong, Hunsoo Choo, Hamid Mahmoodi-Meimand, Yongtao Wang, Kaushik Roy
2002	—	`conf`	IDDQ Testing for Deep Submicron ICs: Challenges and Solutions. LATW Zhanping Chen, Liqiong Wei, Ali Keshavarzi, Kaushik Roy
2002	J	`jnl`	IDDQ Testing for Deep-Submicron ICs: Challenges and Solutions. IEEE Des. Test Comput. Zhanping Chen, Liqiong Wei, Ali Keshavarzi, Kaushik Roy
2002	J	`jnl`	Leakage Current in Deep-Submicron CMOS Circuits. J. Circuits Syst. Comput. Kaushik Roy, Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand
2002	J	`jnl`	Leakage and Process Variation Effects in Current Testing on Future CMOS Circuits. IEEE Des. Test Comput. Ali Keshavarzi, James W. Tschanz, Siva G. Narendra, Vivek De, W. Robert Daasch, Kaushik Roy, Manoj Sachdev, Charles F. Hawkins
2002	J	`jnl`	Leakage control with efficient use of transistor stacks in single threshold CMOS. IEEE Trans. Very Large Scale Integr. Syst. Mark C. Johnson, Dinesh Somasekhar, Lih-Yih Chiou, Kaushik Roy
2002	Misc	`conf`	Low power reconfigurable DCT design based on sharing multiplication. ICASSP Jongsun Park, Soonkeon Kwon, Kaushik Roy
2002	A	`conf`	Model Reduction in the Time-Domain Using Laguerre Polynomials and Krylov Methods. DATE Yiran Chen, Venkataramanan Balakrishnan, Cheng-Kok Koh, Kaushik Roy
2002	—	`conf`	Noise Analysis under Capacitive and Inductive Coupling for High Speed Circuits. DELTA Seung Hoon Choi, Kaushik Roy
2002	J	`jnl`	O IEEE Trans. Very Large Scale Integr. Syst. Yonghee Im, Kaushik Roy
2002	A	`conf`	On-chip interconnect modeling by wire duplication. ICCAD Guoan Zhong, Cheng-Kok Koh, Kaushik Roy
2002	—	`conf`	Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement. ASP-DAC/VLSI Design Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh
2002	J	`jnl`	Reduced computational redundancy implementation of DSP algorithms using computation sharing vector scaling. IEEE Trans. Very Large Scale Integr. Syst. Khurram Muhammad, Kaushik Roy
2002	J	`jnl`	Skewed CMOS: noise-tolerant high-performance low-power static circuit family. IEEE Trans. Very Large Scale Integr. Syst. Alexandre Solomatnikov, Dinesh Somasekhar, Naran Sirisantana, Kaushik Roy
2002	—	`conf`	Synthesis of Selectively Clocked Skewed Logic Circuits. ISQED Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy
2002	A	`conf`	Testing CrossTalk Induced Delay Faults in Static CMOS Circuits Through Dynamic Timing Analysis. ITC Bipul Chandra Paul, Kaushik Roy
2002	A*	`conf`	Timed pattern generation for noise-on-delay calculation. DAC Seung Hoon Choi, Kaushik Roy, Florentin Dartu
2002	J	`jnl`	Vertically integrated SOI circuits for low-power and high-performance applications. IEEE Trans. Very Large Scale Integr. Syst. Liqiong Wei, Rongtian Zhang, Kaushik Roy, Zhanping Chen, David B. Janes
2001	J	`jnl`	A novel approach to high-level switching activity modeling with applications to low-power DSP system synthesis. IEEE Trans. Signal Process. Magnus Lundberg, Khurram Muhammad, Kaushik Roy, Sarah Kate Wilson
2001	A*	`conf`	An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches. HPCA Se-Hyun Yang, Michael D. Powell, Babak Falsafi, Kaushik Roy, T. N. Vijaykumar
2001	A	`conf`	CASh: A Novel "Clock as Shield" Design Methodology for Noise Immune Precharge-Evaluate Logic. ICCAD Yonghee Im, Kaushik Roy
2001	Misc	`conf`	DSP data path synthesis for low-power applications. ICASSP Lih-Yih Chiou, Khurram Muhammad, Kaushik Roy
2001	Misc	`conf`	Decision feedback equalizer with two's complement computation sharing multiplication. ICASSP Hunsoo Choo, Khurram Muhammad, Kaushik Roy
2001	—	`conf`	Decoupling capacitance allocation for power supply noise suppression. ISPD Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh
2001	—	`conf`	Design Verification and Robust Design Technique for Cross-Talk Faults. Asian Test Symposium Bipul Chandra Paul, Seung Hoon Choi, Yonghee Im, Kaushik Roy
2001	—	`conf`	Design and Test of Low Voltage CMOS Circuits. ISQED Kaushik Roy, Ali Keshavarzi
2001	A	`conf`	Double-gate fully-depleted SOI transistors for low-power high-performance nano-scale circuit design. ISLPED Rongtian Zhang, Kaushik Roy, David B. Janes
2001	A*	`conf`	Exploring SOI Device Structures and Interconnect Architectures for 3-Dimensional Integration. DAC Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes
2001	J	`jnl`	Fault Detection and Location Using IDD Waveform Analysis. IEEE Des. Test Comput. Khurram Muhammad, Kaushik Roy
2001	A	`conf`	Low complexity FIR filters using factorization of perturbed coefficients. DATE Cassondra Neau, Khurram Muhammad, Kaushik Roy
2001	J	`jnl`	On effective I IEEE Trans. Very Large Scale Integr. Syst. Zhanping Chen, Liqiong Wei, Kaushik Roy
2001	—	`conf`	Power Constrained Test Scheduling with Low Power Weighted Random Testing. IOLTW Xiaodong Zhang, Kaushik Roy
2001	—	`conf`	Power Trends and Performance Characterization of 3-Dimensional Integration for Future Technology Generations. ISQED Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes
2001	—	`conf`	Power trends and performance characterization of 3-dimensional integration. ISCAS (4) Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes
2001	—	`ed.`	Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, West Lafayette, Indiana, USA, 2001 ACM Great Lakes Symposium on VLSI Kaushik Roy, Sung-Mo Kang, Cheng-Kok Koh
2001	J	`jnl`	QSERL: quasi-static energy recovery logic. IEEE J. Solid State Circuits Yibin Ye, Kaushik Roy
2001	J	`jnl`	Reducing leakage in a high-performance deep-submicron instruction cache. IEEE Trans. Very Large Scale Integr. Syst. Michael D. Powell, Se-Hyun Yang, Babak Falsafi, Kaushik Roy, T. N. Vijaykumar
2001	A*	`conf`	Reducing set-associative cache energy via way-prediction and selective direct-mapping. MICRO Michael D. Powell, Amit Agarwal, T. N. Vijaykumar, Babak Falsafi, Kaushik Roy
2001	J	`jnl`	Robust subthreshold logic for ultra-low power operation. IEEE Trans. Very Large Scale Integr. Syst. Hendrawan Soeleman, Kaushik Roy, Bipul Chandra Paul
2001	A	`conf`	Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications. ISLPED Naran Sirisantana, Aiqun Cao, Shawn Davidson, Cheng-Kok Koh, Kaushik Roy
2001	—	`conf`	Short-circuit power analysis of an inverter driving an RLC load. ISCAS (4) Rui Wang, Kaushik Roy, Cheng-Kok Koh
2001	J	`jnl`	Signal Strength Based Switching Activity Modeling and Estimation for DSP Applications. VLSI Design Lih-Yih Chiou, Khurram Muhammad, Kaushik Roy
2001	Misc	`conf`	Sub-Domino Logic: Ultra-Low Power Dynamic Sub-Threshold Digital Logic. VLSI Design Hendrawan Soeleman, Kaushik Roy, Bipul Chandra Paul
2001	A	`conf`	Ultra-low power DLMS adaptive filter for hearing aid applications. ISLPED Chris Hyung-Il Kim, Kaushik Roy
2000	A	`conf`	A Twisted Bundle Layout Structure for Minimizing Inductive Coupling Noise. ICCAD Guoan Zhong, Cheng-Kok Koh, Kaushik Roy
2000	—	`conf`	A novel high-performance predictable circuit architecture for the deep sub-micron era. CICC Yonghee Im, Kaushik Roy
2000	—	`conf`	Digital CMOS logic operation in the sub-threshold region. ACM Great Lakes Symposium on VLSI Hendrawan Soeleman, Kaushik Roy
2000	A*	`conf`	Dynamic noise analysis in precharge-evaluate circuits. DAC Dinesh Somasekhar, Seung Hoon Choi, Kaushik Roy, Yibin Ye, Vivek De
2000	J	`jnl`	Estimating Circuit Activity in Combinational CMOS Digital Circuits. IEEE Des. Test Comput. Hendrawan Soeleman, Kaushik Roy, Tan-Li Chou
2000	C	`conf`	Estimation of Inductive and Resistive Switching Noise on Power Supply Network in Deep Sub-Micron CMOS Circuits. ICCD Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh
2000	Misc	`conf`	Estimation of Switching Noise on Power Supply Lines in Deep Sub-micron CMOS Circuits. VLSI Design Shiyou Zhao, Kaushik Roy
2000	J	`jnl`	Estimation of power dissipation using a novel power macromodelingtechnique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zhanping Chen, Kaushik Roy, Edwin K. P. Chong
2000	A	`conf`	Frequency Domain Analysis of Switching Noise on Power Supply Network. ICCAD Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh
2000	A	`conf`	Gated-V ISLPED Michael D. Powell, Se-Hyun Yang, Babak Falsafi, Kaushik Roy, T. N. Vijaykumar
2000	C	`conf`	High-Performance Low-Power CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness. ICCD Naran Sirisantana, Liqiong Wei, Kaushik Roy
2000	J	`jnl`	Intrinsic leakage in deep submicron CMOS ICs-measurement-based test solutions. IEEE Trans. Very Large Scale Integr. Syst. Ali Keshavarzi, Kaushik Roy, Charles F. Hawkins
2000	Misc	`conf`	Low Power VLSI Signal Processing. VLSI Design Kaushik Roy, Khurram Muhammad
2000	Misc	`conf`	Low Voltage Low Power CMOS Design Techniques for Deep Submicron ICs. VLSI Design Liqiong Wei, Kaushik Roy, Vivek De
2000	—	`book`	Low-Power CMOS VLSI Circuit Design. Kaushik Roy, Sharat Prasad
2000	J	`jnl`	Low-power weighted random pattern testing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xiaodong Zhang, Wenlei Shan, Kaushik Roy
2000	Misc	`conf`	Minimally redundant parallel implementation of digital filters and vector scaling. ICASSP Khurram Muhammad, Kaushik Roy
2000	A	`conf`	Multiple-parameter CMOS IC testing with increased sensitivity for I_DDQ. ITC Ali Keshavarzi, Kaushik Roy, Charles F. Hawkins, Manoj Sachdev, Krishnamurthy Soumyanath, Vivek De
2000	Misc	`conf`	Non-adaptive and adaptive filter implementation based on sharing multiplication. ICASSP Jongsun Park, Hunsoo Choo, Khurram Muhammad, Seung Hoon Choi, Yonghee Im, Kaushik Roy
2000	—	`conf`	On Effective IDDQ Testing of Low Voltage CMOS Circuits Using Leakage Control Techniques. ISQED Zhanping Chen, Liqiong Wei, Kaushik Roy
2000	—	`conf`	Peak Power Reduction in Low Power BIST. ISQED Xiaodong Zhang, Kaushik Roy
2000	—	`conf`	Power Reduction in Test-Per-Scan BIST. IOLTW Xiaodong Zhang, Kaushik Roy
2000	—	`conf`	Power minimization by simultaneous dual-V CICC Liqiong Wei, Kaushik Roy, Cheng-Kok Koh
2000	—	`ed.`	Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, Chicago, Illinois, USA, March 2-4, 2000 ACM Great Lakes Symposium on VLSI Majid Sarrafzadeh, Prithviraj Banerjee, Kaushik Roy
2000	A	`conf`	Robust ultra-low power sub-threshold DTMOS logic. ISLPED Hendrawan Soeleman, Kaushik Roy, Bipul Chandra Paul
2000	C	`conf`	Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family. ICCD Alexandre Solomatnikov, Kaushik Roy, Cheng-Kok Koh, Dinesh Somasekhar
2000	A	`conf`	Stochastic Wire-Length and Delay Distribution of 3-Dimensional Circuits. ICCAD Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes
2000	A*	`conf`	Test challenges for deep sub-micron technologies. DAC Kwang-Ting Cheng, Sujit Dey, Mike Rodgers, Kaushik Roy
1999	—	`conf`	A Graph Theoretic Approach for Design and Synthesis of Multiplierless FIR Filters. ISSS Khurram Muhammad, Kaushik Roy
1999	A	`conf`	A novel design methodology for high performance and low power digital filters. ICCAD Khurram Muhammad, Kaushik Roy
1999	—	`conf`	Design and Synthesis of Low Power Weighted Random Pattern Generator Considering Peak Power Reduction. DFT Xiaodong Zhang, Kaushik Roy
1999	J	`jnl`	Design and optimization of dual-threshold circuits for low-voltage low-power applications. IEEE Trans. Very Large Scale Integr. Syst. Liqiong Wei, Zhanping Chen, Kaushik Roy, Mark C. Johnson, Yibin Ye, Vivek De
1999	Misc	`conf`	High-level modeling of switching activity with application to low-power DSP system synthesis. ICASSP Magnus Lundberg, Khurram Muhammad, Kaushik Roy, Sarah Kate Wilson
1999	A*	`conf`	Leakage Control with Efficient Use of Transistor Stacks in Single Threshold CMOS. DAC Mark C. Johnson, Dinesh Somasekhar, Kaushik Roy
1999	Misc	`conf`	Low Power Design Methodologies for Systems-on-Chips. VLSI Design Kaushik Roy, Anand Raghunathan, Sujit Dey
1999	A*	`conf`	Mixed- DAC Liqiong Wei, Zhanping Chen, Kaushik Roy, Yibin Ye, Vivek De
1999	J	`jnl`	Models and algorithms for bounds on leakage in CMOS circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mark C. Johnson, Dinesh Somasekhar, Kaushik Roy
1999	—	`conf`	Multiple-Vdd multiple-Vth CMOS (MVCMOS) for low power applications. ISCAS (1) Kaushik Roy, Liqiong Wei, Zhanping Chen
1999	Misc	`conf`	POWERTEST: A Tool for Energy Conscious Weighted Random Pattern Testing. VLSI Design Xiaodong Zhang, Kaushik Roy, Sudipta Bhawmik
1999	—	`conf`	Power Consumption in XOR-Based Circuits. ASP-DAC Yibin Ye, Kaushik Roy, Rolf Drechsler
1999	C	`conf`	Switching Characteristics of Generalized Array Multiplier Architectures and their Applications to Low Power Design. ICCD Khurram Muhammad, Dinesh Somasekhar, Kaushik Roy
1999	A	`conf`	Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's. ISLPED Ali Keshavarzi, Siva G. Narendra, Shekhar Borkar, Charles F. Hawkins, Kaushik Roy, Vivek De
1999	A	`conf`	Ultra-low power digital subthreshold logic circuits. ISLPED Hendrawan Soeleman, Kaushik Roy
1999	Misc	`conf`	VLSI Signal Processing in FPGAs. VLSI Design Sudip Nag, H. K. Verma, Kaushik Roy
1998	A	`conf`	A Coarse-Grained FPGA Architecture for High-Performance FIR Filtering. FPGA James R. Anderson, Siddharth Sheth, Kaushik Roy
1998	A*	`conf`	A Power Macromodeling Technique Based on Power Sensitivity. DAC Zhanping Chen, Kaushik Roy
1998	A*	`conf`	Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits. DAC Liqiong Wei, Zhanping Chen, Mark Johnson, Kaushik Roy, Vivek De
1998	J	`jnl`	Efficient statistical approach to estimate power considering uncertain properties of primary inputs. IEEE Trans. Very Large Scale Integr. Syst. Zhanping Chen, Kaushik Roy, Tan-Li Chou
1998	—	`conf`	Estimation of average switching power under accurate modeling of signal correlations. CICC Zhanping Chen, Kaushik Roy, Yibin Ye
1998	A	`conf`	Estimation of power sensitivity in sequential circuits with power macromodeling application. ICCAD Zhanping Chen, Kaushik Roy, Edwin K. P. Chong
1998	A	`conf`	Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks. ISLPED Zhanping Chen, Mark Johnson, Liqiong Wei, Kaushik Roy
1998	—	`conf`	IDD Waveforms Analysis for Testing of Domino and Low Voltage Static CMOS Circuits. Great Lakes Symposium on VLSI Hendrawan Soeleman, Dinesh Somasekhar, Kaushik Roy
1998	J	`jnl`	LVDCSL: a high fan-in, high-performance, low-voltage differential current switch logic family. IEEE Trans. Very Large Scale Integr. Syst. Dinesh Somasekhar, Kaushik Roy
1998	—	`conf`	Leakage power reduction in low-voltage CMOS designs. ICECS Kaushik Roy
1998	J	`jnl`	Maximum power estimation for CMOS circuits using deterministic and statistical approaches. IEEE Trans. Very Large Scale Integr. Syst. Chuan-Yu Wang, Kaushik Roy
1998	J	`jnl`	Performance and Wirability Driven Layout for Row-Based FPGAs. VLSI Design Sudip Nag, Kaushik Roy
1998	J	`jnl`	Power Estimation Under Uncertain Delays. Integr. Comput. Aided Eng. Tan-Li Chou, Kaushik Roy
1997	A*	`conf`	A Graph-Based Synthesis Algorithm for AND/XOR Networks. DAC Yibin Ye, Kaushik Roy
1997	Misc	`conf`	Algorithms for Low Power FIR Filter Realization Using Differential Coefficients. VLSI Design Naushik Sankarayya, Kaushik Roy, Debashis Bhattacharya
1997	A	`conf`	COSMOS: a continuous optimization approach for maximum power estimation of CMOS circuits. ICCAD Chuan-Yu Wang, Kaushik Roy
1997	J	`jnl`	Datapath scheduling with multiple supply voltages and level converters. ACM Trans. Design Autom. Electr. Syst. Mark C. Johnson, Kaushik Roy
1997	—	`conf`	Efficient synthesis of AND/XOR networks. ASP-DAC Yibin Ye, Kaushik Roy
1997	C	`conf`	Estimation of Maximum Power for Sequential Circuits Considering Spurious Transitions. ICCD Chuan-Yu Wang, Kaushik Roy
1997	A	`conf`	Intrinsic Leakage in Low-Power Deep Submicron CMOS ICs. ITC Ali Keshavarzi, Kaushik Roy, Charles F. Hawkins
1997	A	`conf`	LVDCSL: low voltage differential current switch logic, a robust low power DCSL family. ISLPED Dinesh Somasekhar, Kaushik Roy
1997	Misc	`conf`	Low-Power Driven Logic Synthesis Using Accurate Power Estimation Technique. VLSI Design Priya Patil, Tan-Li Chou, Kaushik Roy, Rabindra Roy
1997	—	`conf`	Network-based simulation laboratories for microelectronics systems design and education. MSE Nirav H. Kapadia, Mark S. Lundstrom, José A. B. Fortes, Kaushik Roy
1997	C	`conf`	On Complexity Reduction of FIR Digital Filters Using Constrained Least Squares Solution. ICCD Khurram Muhammad, Kaushik Roy
1997	A	`conf`	Optimizing computations in a transposed direct form realization of floating-point LTI-FIR systems. ICCAD Naushik Sankarayya, Kaushik Roy, Debashis Bhattacharya
1997	A	`conf`	Power sensitivity - a new method to estimate power dissipation considering uncertain specifications of primary inputs. ICCAD Zhanping Chen, Kaushik Roy, Tan-Li Chou
1997	A	`conf`	Quasi-static energy recovery logic and supply-clock generation circuits. ISLPED Yibin Ye, Kaushik Roy, Georgios I. Stamoulis
1996	J	`jnl`	Accurate power estimation of CMOS sequential circuits. IEEE Trans. Very Large Scale Integr. Syst. Tan-Li Chou, Kaushik Roy
1996	J	`jnl`	Differential current switch logic: a low power DCVS logic family. IEEE J. Solid State Circuits Dinesh Somasekhar, Kaushik Roy
1996	J	`jnl`	Estimation of activity for static and domino CMOS circuits considering signal correlations and simultaneous switching. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tan-Li Chou, Kaushik Roy
1996	Misc	`conf`	Maximum power estimation for CMOS circuits using deterministic and statistic approaches. VLSI Design Chuan-Yu Wang, Kaushik Roy
1996	C	`conf`	Optimal Selection of Supply Voltages and Level Conversions During Data Path Scheduling Under Resource Constraints. ICCD Mark C. Johnson, Kaushik Roy
1996	J	`jnl`	Transistor reordering for power minimization under delay constraint. ACM Trans. Design Autom. Electr. Syst. S. C. Prasad, Kaushik Roy
1995	Misc	`conf`	Circuit optimization for minimisation of power consumption under delay constraint. VLSI Design S. C. Prasad, Kaushik Roy
1995	C	`conf`	Control unit synthesis targeting low-power processors. ICCD Chuan-Yu Wang, Kaushik Roy
1995	C	`conf`	Estimation of sequential circuit activity considering spatial and temporal correlations. ICCD Tan-Li Chou, Kaushik Roy
1995	A	`conf`	Integrated Test Solutions and Test Economics for MCMs. ITC Kevin T. Kornegay, Kaushik Roy
1995	J	`jnl`	On Routability for FPGAs under Faulty Conditions. IEEE Trans. Computers Kaushik Roy, Sudip Nag
1995	A	`conf`	Statistical estimation of sequential circuit activity. ICCAD Tan-Li Chou, Kaushik Roy
1994	C	`conf`	ASAP: A Transistor Sizing Tool for Speed Area and Power Optimization of Static CMOS Circuits. ISCAS Santanu Dutta, Sudip Nag, Kaushik Roy
1994	J	`jnl`	Automatic synthesis of FPGA channel architecture for routability and performance. IEEE Trans. Very Large Scale Integr. Syst. Kaushik Roy, Sudip Nag
1994	J	`jnl`	BiCMOS logic testing. IEEE Trans. Very Large Scale Integr. Syst. Marc E. Levitt, Kaushik Roy, Jacob A. Abraham
1994	A	`conf`	Estimation of circuit activity considering signal correlations and simultaneous switching. ICCAD Tan-Li Chou, Kaushik Roy, Sharat Prasad
1994	J	`jnl`	Guest Editors' Introduction: Low-Power VLSI Design. IEEE Des. Test Comput. Kaushik Roy, Abhijit Chatterjee
1994	—	`conf`	Logic synthesis for reliability - an early start to controlling electromigration and hot carrier effects. EURO-DAC Kaushik Roy, Sharat Prasad
1994	B	`conf`	On Channel Architecture and Routability for FPGAs Under Faulty Conditions. FPL Kaushik Roy, Sudip Nag
1994	B	`conf`	Power Dissipation Driven FPGA Place and Route Under Delay Constraints. FPL Kaushik Roy, Sharat Prasad
1993	J	`jnl`	A bounded search algorithm for segmented channel routing for FPGA's and associated channel architecture issues. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kaushik Roy
1993	C	`conf`	Channel Architecture Optimization for Performance and Routability of Row-Based FPGAs. ICCD Kaushik Roy, Sudip Nag, Santanu Dutta
1993	J	`jnl`	Circuit activity based logic synthesis for low power reliable operations. IEEE Trans. Very Large Scale Integr. Syst. Kaushik Roy, S. C. Prasad
1993	Misc	`conf`	Estimating Area Efficiency of Antifuse Based Channelled FPGA Architectures. VLSI Design Mahesh Mehendale, Kaushik Roy
1993	A*	`conf`	Iterative Wirability and Performance Improvement for FPGAs. DAC Sudip Nag, Kaushik Roy
1993	C	`conf`	On Fault Modeling and Fault Tolerance of Antifuse Based FPGAs. ISCAS Kaushik Roy
1992	C	`conf`	SYCLOP: Synthesis of CMOS Logic for Low Power Applications. ICCD Kaushik Roy, Sharat Prasad
1991	J	`jnl`	The use of RTL descriptions in accurate timing verification and test generation (VLSI). IEEE J. Solid State Circuits Kaushik Roy, Jacob A. Abraham
1990	J	`jnl`	Algorithm-Based Fault Tolerance on a Hypercube Multiprocessor. IEEE Trans. Computers Prithviraj Banerjee, Joseph T. Rahmeh, Craig B. Stunkel, V. S. S. Nair, Kaushik Roy, Vijay Balasubramanian, Jacob A. Abraham
1990	C	`conf`	BiCMOS fault models: is stuck-at adequate? ICCD Marc E. Levitt, Kaushik Roy, Jacob A. Abraham
1990	—	`conf`	High level test generation using data flow descriptions. EURO-DAC Kaushik Roy, Jacob A. Abraham
1989	A*	`conf`	A Novel Approach to Accurate Timing Verification Using RTL Descriptions. DAC Kaushik Roy, Jacob A. Abraham
1989	A	`conf`	Synthesis of delay fault testable combinational logic. ICCAD Kaushik Roy, Jacob A. Abraham, Kaushik De, Stephen L. Lusky
1988	—	`conf`	An evaluation of system-level fault tolerance on the Intel hypercube multiprocessor. FTCS Prithviraj Banerjee, Joseph T. Rahmeh, Craig B. Stunkel, V. S. S. Nair, Kaushik Roy, Jacob A. Abraham