Katsuro Sasaki

16 papers A 1Journal 15

Year	Rank	Type	Title / Venue / Authors
1997	J	`jnl`	Instruction buffering to reduce power in processors for signal processing. IEEE Trans. Very Large Scale Integr. Syst. Raminder Singh Bajwa, Mitsuru Hiraki, Hirotsugu Kojima, Douglas J. Gorny, Ken-ichi Nitta, Avadhani Shridhar, Koichi Seki, Katsuro Sasaki
1996	A	`conf`	Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer. ISLPED Mitsuru Hiraki, Raminder Singh Bajwa, Hirotsugu Kojima, Douglas J. Gorny, Ken-ichi Nitta, Avadhani Shridhar, Katsuro Sasaki, Koichi Seki
1995	J	`jnl`	A 2.6-ns wave-pipelined CMOS SRAM with dual-sensing-latch circuits. IEEE J. Solid State Circuits Suguru Tachibana, Hisayuki Higuchi, Koichi Takasugi, Katsuro Sasaki, Toshiaki Yamanaka, Yoshinobu Nakagome
1995	J	`jnl`	A 4.4 ns CMOS 54⨉54-b multiplier using pass-transistor multiplexer. IEEE J. Solid State Circuits Norio Ohkubo, Makoto Suzuki, Toshinobu Shinbo, Toshiaki Yamanaka, Akihiro Shimizu, Katsuro Sasaki, Yoshinobu Nakagome
1995	J	`jnl`	Half-swing clocking scheme for 75% power saving in clocking circuitry. IEEE J. Solid State Circuits Hirotsugu Kojima, Satoshi Tanaka, Katsuro Sasaki
1995	J	`jnl`	Trends in low-power RAM circuit technologies. Proc. IEEE Kiyoo Itoh, Katsuro Sasaki, Yoshinobu Nakagome
1994	J	`jnl`	A 12.5-ns 16-Mb CMOS SRAM with common-centroid-geometry-layout sense amplifiers. IEEE J. Solid State Circuits Koichiro Ishibashi, Kunihiro Komiyaji, Sadayuki Morita, Toshiro Aoto, Shuji Ikeda, Kyoichiro Asayama, Atsuyosi Koike, Toshiaki Yamanaka, Naotaka Hashimoto, Haruhito Iida, Fumio Kojima, Koichi Motohashi, Katsuro Sasaki
1993	J	`jnl`	A 1.5-ns 32-b CMOS ALU in double pass-transistor logic. IEEE J. Solid State Circuits Makoto Suzuki, Norio Ohkubo, Toshinobu Shinbo, Toshiaki Yamanaka, Akihiro Shimizu, Katsuro Sasaki, Yoshinobu Nakagome
1993	J	`jnl`	A 16-Mb CMOS SRAM with a 2.3- mu m IEEE J. Solid State Circuits Katsuro Sasaki, Kiyotsugu Ueda, Koichi Takasugi, Hiroshi Toyoshima, Koichiro Ishibashi, Toshiaki Yamanaka, Naotaka Hashimoto, Nagatoshi Ohki
1992	J	`jnl`	A 1-V TFT-load SRAM using a two-step word-voltage method. IEEE J. Solid State Circuits Koichiro Ishibashi, Koichi Takasugi, Toshiaki Yamanaka, Takashi Hashimoto, Katsuro Sasaki
1992	J	`jnl`	A 1.5-V full-swing BiCMOS logic circuit. IEEE J. Solid State Circuits Mitsuru Hiraki, Kazuo Yano, Masataka Minami, Kazushige Sato, Nozomu Matsuzaki, Atsuo Watanabe, Takashi Nishida, Katsuro Sasaki, Koichi Seki
1992	J	`jnl`	A 1.7-V adjustable I/O interface for low-voltage fast SRAMs. IEEE J. Solid State Circuits Koichiro Ishibashi, Katsuro Sasaki, Toshiaki Yamanaka, Hiroshi Toyoshima, Fumio Kojima
1992	J	`jnl`	A 7-ns 140-mW 1-Mb CMOS SRAM with current sense amplifier. IEEE J. Solid State Circuits Katsuro Sasaki, Koichiro Ishibashi, Kiyotsugu Ueda, Kunihiro Komiyaji, Toshiaki Yamanaka, Naotaka Hashimoto, Hiroshi Toyoshima, Fumio Kojima, Akihiro Shimizu
1992	J	`jnl`	A voltage down converter with submicroampere standby current for low-power static RAMs. IEEE J. Solid State Circuits Koichiro Ishibashi, Katsuro Sasaki, Hiroshi Toyoshima
1990	J	`jnl`	A 23-ns 4-Mb CMOS SRAM with 0.2- mu A standby current. IEEE J. Solid State Circuits Katsuro Sasaki, Koichiro Ishibashi, Katsuhiro Shimohigashi, Toshiaki Yamanaka, Nobuyuki Moriwake, Shigeru Honjo, Shuji Ikeda, Atsuyoshi Koike, Satoshi Meguro, Osamu Minato
1989	J	`jnl`	A 9-ns 1-Mbit CMOS SRAM. IEEE J. Solid State Circuits Katsuro Sasaki, Koichiro Ishibashi, Toshiaki Yamanaka, Naotaka Hashimoto, Takashi Nishida, Katsuhiro Shimohigashi, Shoji Hanamura, Shigeru Honjo