Katsumasa Watanabe

16 papers A 1Misc 2Journal 6Unranked 7
YearRankTypeTitle / Venue / Authors
2007 J jnl
Robust Quantum Algorithms Computing OR with epsilon-Biased Oracles.
IEICE Trans. Inf. Syst.
Tomoya Suzuki, Shigeru Yamashita, Masaki Nakanishi, Katsumasa Watanabe
2006 Misc conf
A New Approach to Online FPGA Placement.
CISS
Mitsuru Tomono, Masaki Nakanishi, Shigeru Yamashita, Kazuo Nakajima, Katsumasa Watanabe
2006 J jnl
An Efficient and Effective Algorithm for Online Task Placement with I/O Communications in Partially Reconfigurable FPGAs.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Mitsuru Tomono, Masaki Nakanishi, Shigeru Yamashita, Kazuo Nakajima, Katsumasa Watanabe
2006 Misc conf
Robust Quantum Algorithms with
COCOON
Tomoya Suzuki, Shigeru Yamashita, Masaki Nakanishi, Katsumasa Watanabe
2005 — conf
Event-oriented computing with reconfigurable platform.
ASP-DAC
Mitsuru Tomono, Masaki Nakanishi, Katsumasa Watanabe, Shigeru Yamashita
2005 — conf
Reconfigurable 1-Bit Processor Array with Reduced Wirng Area.
ERSA
Nobuo Nakai, Masaki Nakanishi, Shigeru Yamashita, Katsumasa Watanabe
2003 J jnl
Bit Length Optimization of Fractional Part on Floating to Fixed Point Conversion for High-Level Synthesis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Nobuhiro Doi, Takashi Horiyama, Masaki Nakanishi, Shinji Kimura, Katsumasa Watanabe
2002 J jnl
Look Up Table Compaction Based on Folding of Logic Functions.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Shinji Kimura, Atsushi Ishii, Takashi Horiyama, Masaki Nakanishi, Hirotsugu Kajihara, Katsumasa Watanabe
2001 — conf
A real-time 64-monosyllable recognition LSI with learning mechanism.
ASP-DAC
Kazuhiro Nakamura, Qiang Zhu, Shinji Maruoka, Takashi Horiyama, Shinji Kimura, Katsumasa Watanabe
2001 — conf
Speech recognition chip for monosyllables.
ASP-DAC
Kazuhiro Nakamura, Qiang Zhu, Shinji Maruoka, Takashi Horiyama, Shinji Kimura, Katsumasa Watanabe
2000 — conf
An application specific Java processor with reconfigurabilities.
ASP-DAC
Shinji Kimura, Hiroyuki Kida, Kazuyoshi Takagi, Tatsumori Abematsu, Katsumasa Watanabe
2000 — conf
Multi-clock path analysis using propositional satisfiability.
ASP-DAC
Kazuhiro Nakamura, Shinji Maruoka, Shinji Kimura, Katsumasa Watanabe
1998 A conf
Waiting false path analysis of sequential logic circuits for performance optimization.
ICCAD
Kazuhiro Nakamura, Kazuyoshi Takagi, Shinji Kimura, Katsumasa Watanabe
1997 — conf
A Hardware/Software Codesign Method for a General Purpose Reconfigurable Co-Processor.
CODES
Shinji Kimura, Yasufumi Itou, Makoto Hirao, Katsumasa Watanabe, Mitsuteru Yukishita, Akira Nagoya
1988 J jnl
Structured FORTRAN Preprocessors Generating Optimized Output.
Softw. Pract. Exp.
Tatsuo Tsuji, Katsumasa Watanabe, Athushi Ikehata
1987 J jnl
A method of constructing large-scale program processor for 8-bit system utilizing memory mapping feature.
Syst. Comput. Jpn.
Tatsuo Tsuji, Kazuto Kontani, Katsumasa Watanabe, Mitsuaki Sumiya