Katsuhiko Degawa

16 papers A 2C 1Misc 1Journal 5Unranked 7
YearRankTypeTitle / Venue / Authors
2015 A conf
A new method for measuring alias-free aperture jitter in an ADC output.
ITC
Takahiro J. Yamaguchi, Katsuhiko Degawa, Masayuki Kawabata, Masahiro Ishida, Koichiro Uekusa, Mani Soma
2011 C conf
An equivalent-time and clocked approach for continuous-time quantization.
ISCAS
Takahiro J. Yamaguchi, Mohamed Abbas, Mani Soma, Takafumi Aoki, Yasuo Furukawa, Katsuhiko Degawa, Satoshi Komatsu, Kunihiro Asada
2011 A conf
Application of a continuous-time level crossing quantization method for timing noise measurements.
ITC
Takahiro J. Yamaguchi, Mani Soma, Takafumi Aoki, Yasuo Furukawa, Katsuhiko Degawa, Kunihiro Asada, Mohamed Abbas, Satoshi Komatsu
2009 Misc conf
Phase-based alignment of two signals having partially overlapped spectra.
ICASSP
Albert Tumewu, Kazuyuki Miyazawa, Takafumi Aoki, Takahiro J. Yamaguchi, Katsuhiko Degawa, Takayuki Akita
2009 J jnl
Systematic Approach to Designing Multiple-Valued Arithmetic Circuits Based on Arithmetic Description Language.
J. Multiple Valued Log. Soft Comput.
Naofumi Homma, Yuki Watanabe, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi
2008 — conf
High-Level Design of Multiple-Valued Arithmetic Circuits Based on Arithmetic Description Language.
ISMVL
Yuki Watanabe, Naofumi Homma, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi
2007 — conf
Algorithm-Level Optimization of Multiple-Valued Arithmetic Circuits Using Counter Tree Diagrams.
ISMVL
Naofumi Homma, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi
2007 J jnl
Design of Multiple-valued Arithmetic Circuits Using Counter Tree Diagrams.
J. Multiple Valued Log. Soft Comput.
Naofumi Homma, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi
2007 J jnl
Design of a Two-Bit-Per-Cell Content-Addressable Memory Using Single-Electron Transistors.
J. Multiple Valued Log. Soft Comput.
Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Yasuo Takahashi
2006 — conf
A High-Density Ternary Content-Addressable Memory Using Single-Electron Transistors.
ISMVL
Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Katsuhiko Nishiguchi, Yasuo Takahashi
2005 — conf
A Two-Bit-per-Cell Content-Addressable Memory Using Single-Electron Transistors.
ISMVL
Katsuhiko Degawa, Takafumi Aoki, Hiroshi Inokawa, Tatsuo Higuchi, Yasuo Takahashi
2005 J jnl
Prototype Fabrication of Field-Programmable Digital Filter LSIs Using Multiple-Valued Current-Mode Logic - Device Scaling and Future Prospects.
J. Multiple Valued Log. Soft Comput.
Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi
2004 — conf
A Single-Electron-Transistor Logic Gate Family and Its Application - Part I: Basic Components for Binary, Multiple-Valued and Mixed-Mode Logic.
ISMVL
Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Yasuo Takahashi
2004 — conf
A Single-Electron-Transistor Logic Gate Family and Its Application - Part II: Design and Simulation of a 7-3 Parallel Counter with Linear Summation and Multiple-Valued Latch Functions.
ISMVL
Hiroshi Inokawa, Yasuo Takahashi, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi
2003 — conf
A Field-Programmable Digital Filter Chip Using Multiple-Valued Current-Mode Logic.
ISMVL
Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi
2003 J jnl
Design of a Field-Programmable Digital Filter Chip Using Multiple-Valued Current-Mode Logic.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi