Katherine Shu-Min Li

103 papers A* 1A 11B 4C 13Misc 2Journal 29Unranked 43
YearRankTypeTitle / Venue / Authors
2026 J jnl
Security-oriented printed-circuit-board routing with deep reinforcement learning.
Integr.
Katherine Shu-Min Li, Fang-Chi Wu, Ching-Han Lai, Sying-Jyan Wang
2025 C conf
Design of Reliable and Modeling-Attack Resistant Strong PUFs for Lightweight Applications.
ISCAS
Sying-Jyan Wang, Gong-Chi Wang, Chi-Yun Chen, Katherine Shu-Min Li
2025 C conf
Masking Based Protection Mechanism for Ascon against CPA Attack.
ISCAS
Sying-Jyan Wang, Ho Lam Cheung, Katherine Shu-Min Li
2025 — conf
Privacy Preserving Based on SHA Encryption and Cluster Analysis in Federated Frequent Itemset Mining.
ACIIDS (1)
Tzung-Pei Hong, Chi-Chien Chen, Chun-Hao Chen, Katherine Shu-Min Li
2024 B conf
A Federated Mining Framework for Complete Erasable Itemsets.
IEEE Big Data
Tzung-Pei Hong, Meng-Jui Kuo, Chun-Hao Chen, Katherine Shu-Min Li
2024 J jnl
Enhanced Watermarking for Paper-Based Digital Microfluidic Biochips.
ACM Trans. Design Autom. Electr. Syst.
Jian-De Li, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho
2024 — conf
Federated Erasable-Itemset Mining with Quasi-Erasable Itemsets.
ACIIDS (1)
Tzung-Pei Hong, Meng-Jui Kuo, Chun-Hao Chen, Katherine Shu-Min Li
2024 J jnl
Reinforcement Learning Double DQN for Chip-Level Synthesis of Paper-Based Digital Microfluidic Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Katherine Shu-Min Li, Fang-Chi Wu, Jian-De Li, Sying-Jyan Wang
2023 J jnl
Design-for-reliability and on-the-fly fault tolerance procedure for paper-based digital microfluidic biochips with multiple faults.
Integr.
Jian-De Li, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho
2023 A conf
Machine-Learning Driven Sensor Data Analytics for Yield Enhancement of Wafer Probing.
ITC
Nadun Sinhabahu, Katherine Shu-Min Li, Sying-Jyan Wang, J. R. Wang, Matt Ho
2022 — conf
Design-for-Reliability and Probability-Based Fault Tolerance for Paper-Based Digital Microfluidic Biochips with Multiple Faults.
ASP-DAC
Jian-De Li, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho
2022 J jnl
Effective Natural Language Processing and Interpretable Machine Learning for Structuring CT Liver-Tumor Reports.
IEEE Access
Yi-Hsuan Chuang, Ja-Hwung Su, Ding-Hong Han, Yi-Wen Liao, Yeong-Chyi Lee, Yu-Fan Cheng, Tzung-Pei Hong, Katherine Shu-Min Li, Hsin-You Ou, Yi Lu, Chih-Chi Wang
2022 — conf
Improving IJTAG Test Efficiency and Security.
VLSI-DAT
Sying-Jyan Wang, Yen-Chang Shih, Katherine Shu-Min Li, Chen-Yeh Lin, Song-Kong Chong
2022 — conf
Intrusion Detection and Obfuscation Mechanism for PUF-Based Authentication.
ATS
Sying-Jyan Wang, Katherine Shu-Min Li, Chen-Yeh Lin, Song-Kong Chong
2022 B conf
Trojan Insertions of Fully Programmable Valve Arrays.
ETS
Nadun Sinhabahu, Jian-De Li, Katherine Shu-Min Li, Sying-Jyan Wang, Tsung-Yi Ho
2022 A conf
Wafer Defect Pattern Classification with Explainable-Decision Tree Technique.
ITC
Ken Chau-Cheung Cheng, Katherine Shu-Min Li, Sying-Jyan Wang, Andrew Yi-Ann Huang, Chen-Shiun Lee, Leon Li-Yang Chen, Peter Yi-Yu Liao, Nova Cheng-Yen Tsai
2022 A conf
Yield-Enhanced Probe Head Cleaning with AI-Driven Image and Signal Integrity Pattern Recognition for Wafer Test.
ITC
Nadun Sinhabahu, Katherine Shu-Min Li, Jian-De Li, J. R. Wang, Sying-Jyan Wang
2021 B conf
Automatic Inspection for Wafer Defect Pattern Recognition with Unsupervised Clustering.
ETS
Katherine Shu-Min Li, Leon Li-Yang Chen, Ken Chau-Cheung Cheng, Peter Yi-Yu Liao, Sying-Jyan Wang, Andrew Yi-Ann Huang, Nova Cheng-Yen Tsai, Leon Chou, Gus Chang-Hung Han, Jwu E. Chen, Hsing-Chung Liang, Chun-Lung Hsu
2021 A conf
Double DQN for Chip-Level Synthesis of Paper-Based Digital Microfluidic Biochips.
DATE
Fang-Chi Wu, Jian-De Li, Katherine Shu-Min Li, Sying-Jyan Wang, Tsung-Yi Ho
2021 — conf
Integrated Scratch Marker for Wafer Defect Diagnosis.
ITC-Asia
Katherine Shu-Min Li, Leon Li-Yang Chen, Peter Yi-Yu Liao, Sying-Jyan Wang, Andrew Yi-Ann Huang, Ken Chau-Cheung Cheng
2021 — conf
Machine Learning Assisted Challenge Selection for Modeling Attack Resistance in Strong PUFs.
VLSI-DAT
Sying-Jyan Wang, Tzu-Heng Chang, Katherine Shu-Min Li
2021 J jnl
Modeling Attack Resistant PUFs Based on Adversarial Attack Against Machine Learning.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Sying-Jyan Wang, Yu-Sheng Chen, Katherine Shu-Min Li
2021 A conf
Semi-Supervised Framework for Wafer Defect Pattern Recognition with Enhanced Labeling.
ITC
Leon Li-Yang Chen, Katherine Shu-Min Li, Xu-Hao Jiang, Sying-Jyan Wang, Andrew Yi-Ann Huang, Jwu E. Chen, Hsing-Chung Liang, Chun-Lung Hsu
2021 A conf
WGrid: Wafermap Grid Pattern Recognition with Machine Learning Techniques.
ITC
Peter Yi-Yu Liao, Katherine Shu-Min Li, Leon Li-Yang Chen, Sying-Jyan Wang, Andrew Yi-Ann Huang, Ken Chau-Cheung Cheng, Nova Cheng-Yen Tsai, Leon Chou
2020 A conf
Feature Selection for Malicious Traffic Detection with Machine Learning.
ICS
Sying-Jyan Wang, Cheng Xuan Cai, Yen-Wen Tseng, Katherine Shu-Min Li
2020 Misc conf
Innovative Practice on Wafer Test Innovations.
VTS
Dyi-Chung Hu, Hirohito Hashimoto, Li-Fong Tseng, Ken Chau-Cheung Cheng, Katherine Shu-Min Li, Sying-Jyan Wang, Sean Y.-S. Chen, Jwu E. Chen, Clark Liu, Andrew Yi-Ann Huang
2020 B conf
PWS: Potential Wafermap Scratch Defect Pattern Recognition with Machine Learning Techniques.
ETS
Katherine Shu-Min Li, Peter Yi-Yu Liao, Leon Chou, Ken Chau-Cheung Cheng, Andrew Yi-Ann Huang, Sying-Jyan Wang, Gus Chang-Hung Han
2020 A conf
TestDNA-E: Wafer Defect Signature for Pattern Recognition by Ensemble Learning.
ITC
Leon Li-Yang Chen, Katherine Shu-Min Li, Ken Chau-Cheung Cheng, Sying-Jyan Wang, Andrew Yi-Ann Huang, Leon Chou, Nova Cheng-Yen Tsai, Chen-Shiun Lee
2020 J jnl
Using Tree Structure to Mine High Temporal Fuzzy Utility Itemsets.
IEEE Access
Tzung-Pei Hong, Cheng-Yu Lin, Wei-Ming Huang, Katherine Shu-Min Li, Shyue-Liang Leon Wang, Jerry Chun-Wei Lin
2020 A conf
Wafer-Level Test Path Pattern Recognition and Test Characteristics for Test-Induced Defect Diagnosis.
DATE
Ken Chau-Cheung Cheng, Katherine Shu-Min Li, Andrew Yi-Ann Huang, Ji-Wei Li, Leon Li-Yang Chen, Nova Cheng-Yen Tsai, Sying-Jyan Wang, Chen-Shiun Lee, Leon Chou, Peter Yi-Yu Liao, Hsing-Chung Liang, Jwu E. Chen
2020 — conf
Watermarking for Paper-Based Digital Microfluidic Biochips.
ITC-Asia
Jian-De Li, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho
2019 A* conf
Adversarial Attack against Modeling Attack on PUFs.
DAC
Sying-Jyan Wang, Yu-Shen Chen, Katherine Shu-Min Li
2019 J jnl
Co-placement optimization in sensor-reusable cyber-physical digital microfluidic biochips.
Microelectron. J.
Jian-De Li, Chun-Hao Kuo, Guan-Ruei Lu, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho, Hung-Ming Chen, Shiyan Hu
2019 J jnl
Exploiting distribution of unknown values in test responses to optimize test output compactors.
Integr.
Sying-Jyan Wang, Kuan-Ting Yeh, Katherine Shu-Min Li
2019 A conf
TestDNA: Novel Wafer Defect Signature for Diagnosis and Yield Learning.
ITC
Andrew Yi-Ann Huang, Katherine Shu-Min Li, Cheng-Yen Tsai, Ken Chau-Cheung Cheng, Sying-Jyan Wang, Xu-Hao Jiang, Leon Chou, Chen-Shiun Lee
2018 — conf
Digital Rights Management for Paper-Based Microfluidic Biochips.
ATS
Jian-De Li, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho
2018 C conf
Register PUF with No Power-Up Restrictions.
ISCAS
Sying-Jyan Wang, Chin-Hung Lien, Katherine Shu-Min Li
2018 — conf
SOLAR: Simultaneous optimization of control-layer pins placement and channel routing in flow-based microfluidic biochips.
VLSI-DAT
Jia-Lin Wu, Katherine Shu-Min Li, Jain-De Li, Sying-Jyan Wang, Tsung-Yi Ho
2017 J jnl
2016 IEEE Education Society Awards, 2016 Frontiers in Education Conference Awards, and Selected IEEE Awards.
IEEE Trans. Educ.
Edwin C. Jones, Kathleen E. Wage, Sanjit A. Seshia, Susan M. Lord, Michael E. Auer, Lance C. Pérez, Katherine Shu-Min Li, S. L. Krishna Priya, Sasha Nikolic, Francisco Arcega, Richard A. Layton, Matthew W. Ohland, Kayode Peter Ayodele, Isaac A. Inyang, Lawrence O. Kehinde, Jana Reisslein, Amy M. Johnson, Martin Reisslein, James L. Huff, Joachim Walther, Brent K. Jesiek, Carla B. Zoltowski, William C. Oakes, Natasha Nesiba, Enrico Pontelli, Timothy Staley, Melany M. Ciampi, John Heywood, Diane T. Rover, Raman M. Unnikrishnan, Agnieszka Miguel
2017 J jnl
Design Methodology of Fault-Tolerant Custom 3D Network-on-Chip.
ACM Trans. Design Autom. Electr. Syst.
Katherine Shu-Min Li, Sying-Jyan Wang
2017 — conf
Design-for-testability for paper-based digital microfluidic biochips.
DFT
Jain-De Li, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho
2017 J jnl
Layout-Aware Optimized Prebond Silicon Interposer Test Synthesis.
IEEE Des. Test
Katherine Shu-Min Li, Sying-Jyan Wang, Ruei-Ting Gu, Bo-Chuan Cheng
2017 — conf
Testing Clock Distribution Networks.
ATS
Sying-Jyan Wang, Hsiang-Hsueh Chen, Chin-Hung Lien, Katherine Shu-Min Li
2016 J jnl
A Comprehensive Medicine Management System with Multiple Sources in a Nursing Home in Taiwan.
IEICE Trans. Inf. Syst.
Liang-Bi Chen, Wan-Jung Chang, Kuen-Min Lee, Chi-Wei Huang, Katherine Shu-Min Li
2016 C conf
A real-time mobile emergency assistance system for helping deaf-mute people/elderly singletons.
ICCE
Liang-Bi Chen, Chia-Wei Tsai, Wan-Jung Chang, Yuh-Ming Cheng, Katherine Shu-Min Li
2016 — conf
A wearable-glasses-based drowsiness-fatigue-detection system for improving road safety.
GCCE
Liang-Bi Chen, Wan-Jung Chang, Jian-Ping Su, Ji-Yi Ciou, Yi-Jhan Ciou, Cheng-Chin Kuo, Katherine Shu-Min Li
2016 C conf
An adaptive residential energy management scheme in the smart home.
ICCE
Liang-Bi Chen, Meng-Kang Chiang, Chia-Lin Liu, Katherine Shu-Min Li, Jing-Jou Tang
2016 C conf
An efficient fault tolerance path finding algorithm for improving the robustness of multichannel wireless mesh networks.
ICCE
Liang-Bi Chen, Bo-Chuan Cheng, You-Chiun Wang, Katherine Shu-Min Li, Jing-Jou Tang
2016 — conf
Congestion- and timing-driven droplet routing for pin-constrained paper-based microfluidic biochips.
ASP-DAC
Jain-De Li, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho
2016 — conf
Design and development of an extensible multi-protocol automotive gateway.
ICCE-TW
Hong-yuan Li, Liang-Bi Chen, Wan-Jung Chang, Jing-Jou Tang, Katherine Shu-Min Li
2016 — conf
Side-Channel Attack on Flipped Scan Chains.
ATS
Sying-Jyan Wang, Ting-Jui Choi, Katherine Shu-Min Li
2016 Misc conf
Test and diagnosis of paper-based microfluidic biochips.
VTS
Jain-De Li, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho
2016 — conf
Test generation for combinational hardware Trojans.
AsianHOST
Sying-Jyan Wang, Jhih-Yu Wei, Shih-Heng Huang, Katherine Shu-Min Li
2016 J jnl
WristEye: Wrist-Wearable Devices and a System for Supporting Elderly Computer Learners.
IEEE Access
Liang-Bi Chen, Hong-yuan Li, Wan-Jung Chang, Jing-Jou Tang, Katherine Shu-Min Li
2015 A conf
A breakpoint-based silicon debug technique with cycle-granularity for handshake-based SoC.
DATE
Hsin-Chen Chen, Cheng-Rong Wu, Katherine Shu-Min Li, Kuen-Jong Lee
2015 — conf
An intelligent vehicular telematics platform for vehicle driving safety supporting system.
ICCVE
Liang-Bi Chen, Hong-yuan Li, Wan-Jung Chang, Jing-Jou Tang, Katherine Shu-Min Li
2014 — conf
A Hybrid Multi-functions Digital Public Address System with Earthquake Early Warning.
IIH-MSP
Chung Heng Chuang, Tsung-Hsing Lin, Liang-Bi Chen, Tung-Lin Lee, Chaio Hsuan Chuang, Katherine Shu-Min Li, Chih-Lin Hung, Chao-Wen Wu
2014 J jnl
An Oscillation-Based On-Chip Temperature-Aware Dynamic Voltage and Frequency Scaling Scheme in System-on-a-Chip.
IEICE Trans. Inf. Syst.
Katherine Shu-Min Li, Yingchieh Ho, Yu-Wei Yang, Liang-Bi Chen
2014 C conf
Fast and accurate statistical static timing analysis.
ISCAS
Sying-Jyan Wang, Tsung-Huei Tzeng, Katherine Shu-Min Li
2014 — conf
Improving Output Compaction Efficiency with High Observability Scan Chains.
ATS
Sying-Jyan Wang, Che-Wei Kao, Katherine Shu-Min Li
2014 — conf
Optimized Pre-bond Test Methodology for Silicon Interposer Testing.
ATS
Katherine Shu-Min Li, Sying-Jyan Wang, Jia-Lin Wu, Cheng-You Ho, Yingchieh Ho, Ruei-Ting Gu, Bo-Chuan Cheng
2013 — conf
A 0.3 V low-power temperature-insensitive ring oscillator in 90 nm CMOS process.
VLSI-DAT
Yingchieh Ho, Katherine Shu-Min Li, Sying-Jyan Wang
2013 — conf
A Layout-Aware Test Methodology for Silicon Interposer in System-in-a-Package.
Asian Test Symposium
Katherine Shu-Min Li, Cheng-You Ho, Ruei-Ting Gu, Sying-Jyan Wang, Yingchieh Ho, Jiun-Jie Huang, Bo-Chuan Cheng, An-Ting Liu
2013 J jnl
CusNoC: Fast Full-Chip Custom NoC Generation.
IEEE Trans. Very Large Scale Integr. Syst.
Katherine Shu-Min Li
2013 J jnl
IEEE 1500 Compatible Multilevel Maximal Concurrent Interconnect Test.
IEEE Trans. Very Large Scale Integr. Syst.
Katherine Shu-Min Li, Yi-Yu Liao
2013 J jnl
Interconnect-Driven Floorplanning with Noise-Aware Buffer Planning.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Katherine Shu-Min Li, Yingchieh Ho, Liang-Bi Chen
2013 — conf
Leakage Monitoring Technique in Near-Threshold Systems with a Time-Based Bootstrapped Ring Oscillator.
Asian Test Symposium
Yingchieh Ho, Katherine Shu-Min Li, Sying-Jyan Wang
2013 — conf
Low-cost testing of TSVs in 3D stacks with pre-bond testable dies.
VLSI-DAT
Sying-Jyan Wang, Yu-Siao Chen, Katherine Shu-Min Li
2013 J jnl
Oscillation and Transition Tests for Synchronous Sequential Circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Katherine Shu-Min Li
2013 C conf
Synthesis of 3D clock tree with pre-bond testability.
ISCAS
Sying-Jyan Wang, Cheng-Hao Lin, Katherine Shu-Min Li
2012 — conf
De Bruijn graph-based communication modeling for fault tolerance in smart grids.
APCCAS
Bo-Chuan Cheng, Katherine Shu-Min Li, Sying-Jyan Wang
2012 — conf
Intelligent home management in the smart grids.
APCCAS
Meng-Kang Chiang, Katherine Shu-Min Li
2012 J jnl
Layout-Aware Multiple Scan Tree Synthesis for 3-D SoCs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Katherine Shu-Min Li, Yi-Yu Liao
2012 C conf
Low-power delay test architecture for pre-bond test.
ISCAS
Sying-Jyan Wang, Han-Hsuan Hsu, Katherine Shu-Min Li
2011 — conf
A Unified Interconnects Testing Scheme for 3D Integrated Circuits.
Asian Test Symposium
Chih-Yun Pai, Ruei-Ting Gu, Bo-Chuan Cheng, Liang-Bi Chen, Katherine Shu-Min Li
2011 — conf
Fault tolerant application-specific NoC topology synthesis for three-dimensional integrated circuits.
SoCC
Yi-Xue Zheng, Po-Ping Kan, Liang-Bi Chen, Kai-Yang Hsieh, Bo-Chuan Cheng, Katherine Shu-Min Li
2011 J jnl
Maximal Interconnect Resilient Methodology for Fault Tolerance, Yield, and Reliability Improvement in Network on Chip.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Katherine Shu-Min Li, Chih-Yun Pai, Liang-Bi Chen
2011 J jnl
Synthesizing Multiple Scan Trees to Optimize Test Application Time.
IEEE Des. Test Comput.
Katherine Shu-Min Li, Jr-Yang Huang
2010 — conf
Maximal Resilience for Reliability and Yield Enhancement in Interconnect Structure.
Asian Test Symposium
Chih-Yun Pai, Katherine Shu-Min Li
2010 J jnl
Multiple Scan Trees Synthesis for Test Time/Data and Routing Length Reduction Under Output Constraint.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Katherine Shu-Min Li
2009 J jnl
A Unified Detection Scheme for Crosstalk Effects in Interconnection Bus.
IEEE Trans. Very Large Scale Integr. Syst.
Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen
2009 — conf
IEEE 1500 Compatible Interconnect Test with Maximal Test Concurrency.
Asian Test Symposium
Katherine Shu-Min Li, Yi-Yu Liao, Yuo-Wen Liu, Jr-Yang Huang
2009 C conf
Level Converting Scan Flip-flops.
ISCAS
Katherine Shu-Min Li, Ming-Hua Hsieh, Sying-Jyan Wang
2009 C conf
Low Peak Power ATPG for n-Detection Test.
ISCAS
Sying-Jyan Wang, Kuo-Lin Fu, Katherine Shu-Min Li
2009 — conf
Multiple Scan Trees Synthesis for Test Time/Data and Routing Length Reduction under Output Constraint.
Asian Test Symposium
Katherine Shu-Min Li, Yu-Chen Hung, Jr-Yang Huang
2009 J jnl
Scan-Chain Partition for High Test-Data Compressibility and Low Shift Power Under Routing Constraint.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sying-Jyan Wang, Katherine Shu-Min Li, Shih-Cheng Chen, Huai-Yan Shiu, Yun-Lung Chu
2009 — conf
Temperature-aware dynamic frequency and voltage scaling for reliability and yield enhancement.
ASP-DAC
Yu-Wei Yang, Katherine Shu-Min Li
2008 C conf
Design and analysis of skewed-distribution scan chain partition for improved test data compression.
ISCAS
Sying-Jyan Wang, Shih-Cheng Chen, Katherine Shu-Min Li
2008 — conf
Interconnect-Driven Layout-Aware Multiple Scan Tree Synthesis for Test Time, Data Compression and Routing Optimization.
ATS
Katherine Shu-Min Li, Jr-Yang Huang
2008 J jnl
Layout-aware scan chain reorder for launch-off-shift transition test coverage.
ACM Trans. Design Autom. Electr. Syst.
Sying-Jyan Wang, Kuo-Lin Peng, Kuang-Cyun Hsiao, Katherine Shu-Min Li
2007 J jnl
IEEE Standard 1500 Compatible Oscillation Ring Test Methodology for Interconnect Delay and Crosstalk Detection.
J. Electron. Test.
Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen
2007 — conf
Layout-Aware Multi-Layer Multi-Level Scan Tree Synthesis.
ATS
Sying-Jyan Wang, Xin-Long Li, Katherine Shu-Min Li
2007 C conf
Low Capture Power Test Generation for Launch-off-Capture Transition Test Based on Don't-Care Filling.
ISCAS
Sying-Jyan Wang, Yan-Ting Chen, Katherine Shu-Min Li
2007 J jnl
Multilevel Full-Chip Routing With Testability and Yield Enhancement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Katherine Shu-Min Li, Yao-Wen Chang, Chung-Len Lee, Chauchin Su, Jwu E. Chen
2007 — conf
Test Data and Test Time Reduction for LOS Transition Test in Multi-Mode Segmented Scan Architecture.
ATS
Sying-Jyan Wang, Po-Chang Tsai, Hung-Ming Weng, Katherine Shu-Min Li
2006 J jnl
IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Katherine Shu-Min Li, Chauchin Su, Yao-Wen Chang, Chung-Len Lee, Jwu E. Chen
2006 — conf
IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults.
ASP-DAC
Katherine Shu-Min Li, Yao-Wen Chang, Chauchin Su, Chung-Len Lee, Jwu E. Chen
2006 — conf
Layout-Aware Scan Chain Reorder for Skewed-Load Transition Test Coverage.
ATS
Sying-Jyan Wang, Kuo-Lin Peng, Katherine Shu-Min Li
2005 — conf
Finite State Machine Synthesis for At-Speed Oscillation Testability.
Asian Test Symposium
Katherine Shu-Min Li, Chung-Len Lee, Tagin Jiang, Chauchin Su, Jwu E. Chen
2005 — conf
Multilevel full-chip routing with testability and yield enhancement.
SLIP
Katherine Shu-Min Li, Chung-Len Lee, Yao-Wen Chang, Chauchin Su, Jwu E. Chen
2005 — conf
Oscillation ring based interconnect test scheme for SOC.
ASP-DAC
Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen
2004 — conf
A Unified Approach to Detecting Crosstalk Faults of Interconnects in Deep Sub-Micron VLSI.
Asian Test Symposium
Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen
2003 — conf
Noise-aware buffer planning for interconnect-driven floorplanning.
ASP-DAC
Katherine Shu-Min Li, Yih-Huai Cherng, Yao-Wen Chang