Katell Morin-Allory

53 papers A 1B 1C 26Journal 7Unranked 17

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Automatic Assertion Mining in Assertion-Based Verification: Techniques, Challenges, and Future Directions. CoRR Mohammad Reza Heidari Iman, Giorgio Di Natale, Katell Morin-Allory
2025	C	`conf`	A Survey on Automatic Assertion Miners. DDECS Mohammad Reza Heidari Iman, Giorgio Di Natale, Katell Morin-Allory
2025	C	`conf`	Formal Analysis of Fault Propagation in Complex Digital Systems. MEMOCODE Damiano Zuccalà, Samuel Hon, Mohammad Reza Heidari Iman, Jean-Marc Daveau, Philippe Roche, Katell Morin-Allory
2024	C	`conf`	Formal Fault Injection in Digital Blocks with Mined Assertions. MEMOCODE Damiano Zuccalà, Paul Breuil, Jean-Marc Daveau, Philippe Roche, Katell Morin-Allory
2024	B	`conf`	Formal Resilience Metric Characterization in Complex Digital Systems. ETS Damiano Zuccalà, Jean-Marc Daveau, Philippe Roche, Katell Morin-Allory
2024	C	`conf`	WIP: Building an Education Ecosystem for Next Generation Microelectronics Experts in Green and Circular Economy with Digitally-Supported Teaching Methods for Sustainable Chips and Applications (EU Project GreenChips-EDU). FIE Klaus Hofmann, Ferdinand Keil, David Riehl, Alicja Michalowska-Forsyth, Nikolaus Czepl, Sarah Woywod, Dominik Zupan, Mario R. Casu, Carlo Ricciardi, Massimo Violante, Mariagrazia Graziano, Yuri Ardesi, Fabrizio Mo, Dominik Berger, Sabine Sill, Volker Visotschnig, Panagiota Morfouli, Liliana Prejbeanu, Katell Morin-Allory, Cyrille Chavet, Davide Bucci, Skandar Basrour, Jean-Christophe Crebier, Nhu-Huan Nguyen, Ernesto Quisbert-Trujillo, Christian Defélix, Isabelle Corbett-Etchevers, Johannes Sturm, Jens Peter Konrath, Ulla Birnbacher, Thomas Klinger, Wolfgang Werth, Jorge Fernandes, Marcelino B. Santos, Antonio Rubio, Alba Pagès-Zamora, Josep Pegueroles, Jordi Salazar, Beatriz Otero, J. Manuel Moreno, X. Aragones, Israel Martin, Aleix Sole, Dunja Suttnig, Julia Calabro, Floriberto Lima, Eric Jouseau, François Cerisier, Cristian Rivier, Sepp Eisenriegler, Harald Reichl, Miroslav Macan, Dubravko Kruselj, Mladen Puskaric, Mirjana Tatalovic, Vinko Zelenicic, Bernd Deutschmann
2023	—	`conf`	A Generic CDC Modeling for Data Stability Verification. ICECS Diana Kalel, Jean-Christophe Brignone, Laurent Fesquet, Katell Morin-Allory
2023	—	`conf`	Formal Temporal Characterization of Register Vulnerability in Digital Circuits. ISVLSI Damiano Zuccalà, Jean-Marc Daveau, Philippe Roche, Katell Morin-Allory
2023	C	`conf`	Method for Data-Driven Pruning in Micropipeline Circuits. VLSI-SoC Cristiano Merio, Xavier Lesage, Ali Naimi, Sylvain Engels, Katell Morin-Allory, Laurent Fesquet
2021	C	`conf`	A High-Level Design Flow for Locally Body Biased Asynchronous Circuits. VLSI-SoC Yoan Decoudu, Katell Morin-Allory, Laurent Fesquet
2021	C	`conf`	Cross-layer Approach to Assess FMEA on Critical Systems and Evaluate High-Level Model Realism. VLSI-SoC Julie Roux, Katell Morin-Allory, Vincent Beroulle, Régis Leveugle, Lilian Bossuet, Frédéric Cézilly, Frédéric Berthoz, Gilles Genévrier, François Cerisier
2021	—	`conf`	FMEA on Critical Systems: A Cross-Layer Approach Based on High-Level Models. VLSI-SoC (Selected Papers) Julie Roux, Katell Morin-Allory, Vincent Beroulle, Lilian Bossuet, Frédéric Cézilly, Frédéric Berthoz, Gilles Genévrier, François Cerisier, Régis Leveugle
2021	—	`conf`	FPU Reduced Variable Precision in Time: Application to the Jacobi Iterative Method. ISVLSI Noureddine Ait Said, Mounir Benabdenbi, Katell Morin-Allory
2020	C	`conf`	Cross Layer Fault Simulations for Analyzing the Robustness of RTL Designs in Airborne Systems. DDECS Julie Roux, Vincent Beroulle, Katell Morin-Allory, Régis Leveugle, Lilian Bossuet, Frédéric Cézilly, Frédéric Berthoz, Gilles Genévrier, François Cerisier
2020	—	`conf`	FPU Bit-Width Optimization for Approximate Computing: A Non-Intrusive Approach. DTIS Noureddine Ait Said, Mounir Benabdenbi, Katell Morin-Allory
2020	—	`conf`	From High-Level Synthesis to Bundled-Data Circuits. SAMOS Yoan Decoudu, Jean Simatic, Katell Morin-Allory, Laurent Fesquet
2020	—	`conf`	High Level Fault Injection Method for Evaluating Critical System Parameter Ranges. ICECS Julie Roux, Vincent Beroulle, Katell Morin-Allory, Régis Leveugle, Lilian Bossuet, Frédéric Cézilly, Frédéric Berthoz, Gilles Genévrier, François Cerisier
2019	C	`conf`	A Distributed Body-Biasing Strategy for Asynchronous Circuits. VLSI-SoC Laurent Fesquet, Yoan Decoudu, Alexis Rodrigo Iga Jadue, Thiago Ferreira de Paiva Leite, Otto Aureliano Rolloff, M. Diallo, Rodrigo Possamai Bastos, Katell Morin-Allory, Sylvain Engels
2019	—	`conf`	Comparison of Synchronous and Asynchronous FIR Filter Architectures. EBCCSP Yoan Decoudu, Jean Simatic, Pauline Alexandre, Katell Morin-Allory, Laurent Fesquet
2019	J	`jnl`	Mining Missing Assumptions from Counter-Examples. ACM Trans. Embed. Comput. Syst. Guillaume Plassan, Katell Morin-Allory, Dominique Borrione
2017	C	`conf`	Extraction of missing formal assumptions in under-constrained designs. MEMOCODE Guillaume Plassan, Katell Morin-Allory, Dominique Borrione
2017	J	`jnl`	Synthesis of Regular Expressions Revisited: From PSL SEREs to Hardware. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Fatemeh Negin Javaheri, Katell Morin-Allory, Dominique Borrione
2016	—	`conf`	Clock domain crossing formal verification: a meta-model. HLDVT Mejid Kebaili, Jean-Christophe Brignone, Katell Morin-Allory
2016	C	`conf`	Conclusively verifying clock-domain crossings in very large hardware designs. VLSI-SoC Guillaume Plassan, Hans-Jörg Peter, Katell Morin-Allory, Fahim Rahim, Shaker Sarwary, Dominique Borrione
2016	—	`conf`	Improving the Efficiency of Formal Verification: The Case of Clock-Domain Crossings. VLSI-SoC (Selected Papers) Guillaume Plassan, Hans-Jörg Peter, Katell Morin-Allory, Shaker Sarwary, Dominique Borrione
2015	J	`jnl`	Efficient and Correct by Construction Assertion-Based Synthesis. IEEE Trans. Very Large Scale Integr. Syst. Katell Morin-Allory, Fatemeh Negin Javaheri, Dominique Borrione
2015	C	`conf`	Enabler-based synchronizer model for clock domain crossing static verification. FDL Mejid Kebaili, Katell Morin-Allory, Jean-Christophe Brignone, Dominique Borrione
2013	C	`conf`	Fast prototyping from assertions: A pragmatic approach. MEMOCODE Katell Morin-Allory, Fatemeh Negin Javaheri, Dominique Borrione
2013	C	`conf`	SyntHorus-2: Automatic prototyping from PSL. VLSI-SoC Katell Morin-Allory, Fatemeh Negin Javaheri, Dominique Borrione
2011	—	`conf`	C-elements for Hardened Self-timed Circuits. PATMOS Florent Ouchet, Katell Morin-Allory, Laurent Fesquet
2011	C	`conf`	Does asynchronous technology bring robustness in synchronous circuit monitoring? FDL Alexandre Porcher, Katell Morin-Allory, Laurent Fesquet, Alejandro Chagoya
2011	—	`conf`	Formal Verification of C-element Circuits. ASYNC Chao Yan, Florent Ouchet, Laurent Fesquet, Katell Morin-Allory
2010	—	`conf`	Delay Insensitivity Does Not Mean Slope Insensitivity! ASYNC Florent Ouchet, Katell Morin-Allory, Laurent Fesquet
2010	C	`conf`	Synthesis of asynchronous monitors for critical electronic systems. DDECS Alexandre Porcher, Katell Morin-Allory, Laurent Fesquet
2010	J	`jnl`	Validating Assertion Language Rewrite Rules and Semantics With Automated Theorem Provers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Katell Morin-Allory, Marc Boule, Dominique Borrione, Zeljko Zilic
2009	C	`conf`	From Assertion-Based Verification to Assertion-Based Synthesis. VLSI-SoC Yann Oddos, Katell Morin-Allory, Dominique Borrione
2009	C	`conf`	High-level symbolic simulation for automatic model extraction. DDECS Florent Ouchet, Dominique Borrione, Katell Morin-Allory, Laurence Pierre
2009	—	`conf`	MYGEN: automata-based on-line test generator for assertion-based verification. ACM Great Lakes Symposium on VLSI Yann Oddos, Katell Morin-Allory, Dominique Borrione, Marc Boule, Zeljko Zilic
2009	C	`conf`	RAT-based formal verification of QDI asynchronous controllers. FDL Khaled Alsayeg, Katell Morin-Allory, Laurent Fesquet
2008	C	`conf`	Assertion-Based Design with Horus. MEMOCODE Yann Oddos, Katell Morin-Allory, Dominique Borrione
2008	—	`conf`	Proving and disproving assertion rewrite rules with automated theorem provers. HLDVT Katell Morin-Allory, Marc Boule, Dominique Borrione, Zeljko Zilic
2007	C	`conf`	Asynchronous online-monitoring of logical and temporal assertions. FDL Katell Morin-Allory, Laurent Fesquet, Benjamin Roustan, Dominique Borrione
2007	C	`conf`	Prototyping Generators for On-line Test Vector Generation Based on PSL Properties. DDECS Yann Oddos, Katell Morin-Allory, Dominique Borrione
2007	J	`jnl`	Synthesis of Property Monitors for Online Fault Detection. J. Circuits Syst. Comput. Katell Morin-Allory, Eric Gascard, Dominique Borrione
2006	C	`conf`	Asynchronous Assertion Monitors for multi-Clock Domain System Verification. IEEE International Workshop on Rapid System Prototyping Katell Morin-Allory, Laurent Fesquet, Dominique Borrione
2006	C	`conf`	On-Line Test Vector Generation from Temporal Constraints Written in PSL. VLSI-SoC Yann Oddos, Katell Morin-Allory, Dominique Borrione
2006	C	`conf`	On-line Monitoring of Properties Built on Regular Expressions. FDL Katell Morin-Allory, Dominique Borrione
2006	A	`conf`	Proven correct monitors from PSL specifications. DATE Katell Morin-Allory, Dominique Borrione
2005	—	`conf`	A proof of correctness for the construction of property monitors. HLDVT Katell Morin-Allory, Dominique Borrione
2005	—	`conf`	Proving Parameterized Systems: The Use of Pseudo-Pipelines in Polyhedral Logic. CHARME Katell Morin-Allory, David Cachera
2005	J	`jnl`	Verification of safety properties for parameterized regular systems. ACM Trans. Embed. Comput. Syst. David Cachera, Katell Morin-Allory
2004	—	`—`	Vérification Formelle dans le Modèle Polyédrique. (Formal Verification in the Polyhedral Model). Katell Morin-Allory
2003	C	`conf`	Verification of Control Properties in the Polyhedral Model. MEMOCODE David Cachera, Katell Morin-Allory