Katayoon Basharkhah

16 papers B 5C 1Misc 1Journal 1Unranked 8

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	An Event-Based Gate-Level Framework for Power Side-Channel Leakage Assessment. ISVLSI Katayoon Basharkhah, Zahra Hojati, Zainalabedin Navabi
2025	B	`conf`	An Integrated Framework for Aging Analysis Based on an Age-Aware Cell Library. ETS Amirmahdi Joudi, Negin Safari, Fatemeh MohammadZadeh, Katayoon Basharkhah, Fatemeh Sheikhshoaei, Zainalabedin Navabi
2025	B	`conf`	European Test Symposium Teams: an Anniversary Snapshot. ETS Maksim Jenihhin, Jaan Raik, Artur Jutman, Natalia Cherezova, Raimund Ubar, Liviu Miclea, Szilárd Enyedi, I. Stefan, Ovidiu Stan, Cosmina Corches, Z. Peng, Petru Eles, Rolf Drechsler, S. Eggersglüß, Görschwin Fey, Andreas Glowatz, Daniel Tille, Georges G. E. Gielen, Anthony Coyette, Wim Dobbelaere, Ronny Vanhooren, P.-Y. Chuang, Erik Jan Marinissen, Giorgio Di Natale, M. Barragan, Paolo Maistri, S. Mir, Vatajelu I. Vatajelu, Paolo Bernardi, S. Di Carlo, Paolo Prinetto, Matteo Sonza Reorda, Massimo Violante, Haralampos-G. Stratigopoulos, M. K. Michael, Stelios Neophytou, Stavros Hadjitheophanous, Kyriakos Christou, M. Skitsas, Alberto Bosio, Bastien Deveautour, P. Girard, Marcello Traiola, Arnaud Virazel, F. Fernandes Dos Santos, Angeliki Kritikakou, Gioele Casagranda, Marzio Vallero, Flavio Vella, Paolo Rech, Letícia Maria Bolzani Poehls, Milos Krstic, Marko S. Andjelkovic, F. Vargas, Grigor Tshagharyan, Gurgen Harutyunyan, Valery A. Vardanian, Samvel K. Shoukourian, Yervant Zorian, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas, Mottaqiallah Taouil, Moritz Fieback, Anteneh Gebregiorgis, Rajendra Bishnoi, Said Hamdioui, Abhijit Chatterjee, A. Saha, Suhasini Komarraju, K. Ma, Chandramouli N. Amarnath, Mehdi Baradaran Tahoori, Mahta Mayahinia, Maryam Rajabalipanah, Katayoon Basharkhah, N. Nosrati, Zahra Jahanpeima, Zain Navabi, Hans-Joachim Wunderlich, Sybille Hellebrand
2024	—	`conf`	Event-Based Power Analysis Integrated with Timing Characterization and Logic Simulation. ISVLSI Katayoon Basharkhah, Zainalabedin Navabi
2023	B	`conf`	Learning Electrical Behavior of Core Interconnects for System-Level Crosstalk Prediction. ETS Katayoon Basharkhah, Raheleh Sadat Mirhashemi, Nooshin Nosrati, Mohammad-Javad Zare, Zainalabedin Navabi
2021	B	`conf`	Online Testing of a Row-Stationary Convolution Accelerator. ETS Mohammad Rasoul Roshanshah, Katayoon Basharkhah, Zainalabedin Navabi
2021	—	`conf`	Testing a RISCV-Like Architecture With an HDL-Based Virtual Tester. DTIS Nooshin Nosrati, Katayoon Basharkhah, Hanieh Totonchi Asl, Zahra Mahdavi, Zainalabedin Navabi
2020	Misc	`conf`	ESL, Back-annotating Crosstalk Fault Models into High-level Communication Links. VTS Katayoon Basharkhah, Rezgar Sadeghi, Nooshin Nosrati, Zainalabedin Navabi
2020	C	`conf`	Reconfiguration of Embedded Accelerators by Microprogramming for Intensive Loop Computations. DDECS Saba Yousefzadeh, Katayoon Basharkhah, Nooshin Nosrati, Maryam Rajabalipanah, Seyedeh Maryam Ghasemi, Zainalabedin Navabi
2020	—	`conf`	Reducing DFT hardware overhead by use of a test microprogram in a microprogrammed hardware accelerator. DFT Maryam Rajabalipanah, Seyedeh Maryam Ghasemi, Nooshin Nosrati, Katayoon Basharkhah, Saba Yousefzadeh, Zainalabedin Navabi
2019	—	`conf`	An Accelerator-based Architecture Utilizing an Efficient Memory Link for Modern Computational Requirements. EWDTS Saba Yousefzadeh, Katayoon Basharkhah, Nooshin Nosrati, Rezgar Sadeghi, Jaan Raik, Maksim Jenihhin, Zainalabedin Navabi
2019	—	`conf`	An ESL Environment for Modeling Electrical Interconnect Faults. ISVLSI Nooshin Nosrati, Katayoon Basharkhah, Rezgar Sadeghi, Zainalabedin Navabi
2019	B	`conf`	Back-annotation of Interconnect Physical Properties for System-Level Crosstalk Modeling. ETS Rezgar Sadeghi, Nooshin Nosrati, Katayoon Basharkhah, Zainalabedin Navabi
2019	—	`conf`	From Abstract Modeling of ADAS Applications to an Accelerator-based Hardware Realization. EWDTS Samira Ahmadi Farsani, Katayoon Basharkhah, Amin Mohaghegh, Zainalabedin Navabi
2019	—	`conf`	Making System Level Test Possible by a Mixed-mode, Multi-level, Integrated Modeling Environment. EWDTS Nooshin Nosrati, Katayoon Basharkhah, Rezgar Sadeghi, Carna Zivkovic, Christoph Grimm, Zainalabedin Navabi
2018	J	`jnl`	A Comparison of MVDR and LCMV Beamformers' Floating Point Implementations on FPGAs. Wirel. Pers. Commun. Siavash Amin-Nejad, Tayyebeh Asgari Gashteroodkhani, Katayoon Basharkhah