Katarzyna Radecka

65 papers A* 1A 5B 2C 12Misc 3Journal 16Unranked 26

Year	Rank	Type	Title / Venue / Authors
2022	J	`jnl`	Wearable Vibrotactile System as an Assistive Technology Solution. Mob. Networks Appl. Majid Janidarmian, Atena Roshan Fekr, Katarzyna Radecka, Zeljko Zilic
2019	Misc	`conf`	Exploring Better Food Detection via Transfer Learning. MVA Jianing Sun, Katarzyna Radecka, Zeljko Zilic
2019	J	`jnl`	FoodTracker: A Real-time Food Detection Mobile Application by Deep Convolutional Neural Networks. CoRR Jianing Sun, Katarzyna Radecka, Zeljko Zilic
2017	J	`jnl`	A Comprehensive Analysis on Wearable Acceleration Sensors in Human Activity Recognition. Sensors Majid Janidarmian, Atena Roshan Fekr, Katarzyna Radecka, Zeljko Zilic
2017	—	`conf`	A Novel Algorithm to Reduce Machine Learning Efforts in Real-Time Sensor Data Analysis. MobiHealth Majid Janidarmian, Atena Roshan Fekr, Katarzyna Radecka, Zeljko Zilic
2017	—	`conf`	Designing and Evaluating a Vibrotactile Language for Sensory Substitution Systems. MobiHealth Majid Janidarmian, Atena Roshan Fekr, Katarzyna Radecka, Zeljko Zilic
2016	—	`conf`	Haptic feedback and human performance in a wearable sensor system. BHI Majid Janidarmian, Atena Roshan Fekr, Katarzyna Radecka, Zeljko Zilic
2016	J	`jnl`	Respiration Disorders Classification With Informative Features for m-Health Applications. IEEE J. Biomed. Health Informatics Atena Roshan Fekr, Majid Janidarmian, Katarzyna Radecka, Zeljko Zilic
2015	J	`jnl`	Design and Evaluation of an Intelligent Remote Tidal Volume Variability Monitoring System in E-Health Applications. IEEE J. Biomed. Health Informatics Atena Roshan Fekr, Katarzyna Radecka, Zeljko Zilic
2015	J	`jnl`	ICAT: Engine to Perform Range Analysis and Allocate Bit-Widths for Arithmetic Datapaths. J. Circuits Syst. Comput. Yu Pang, Yafeng Yan, Jinzhao Lin, Guoquan Li, Huawei Huang, Lei Shi, Katarzyna Radecka
2015	J	`jnl`	Movement analysis of the chest compartments and a real-time quality feedback during breathing therapy. Netw. Model. Anal. Health Informatics Bioinform. Atena Roshan Fekr, Majid Janidarmian, Katarzyna Radecka, Zeljko Zilic
2014	J	`jnl`	A Medical Cloud-Based Platform for Respiration Rate Measurement and Hierarchical Classification of Breath Disorders. Sensors Atena Roshan Fekr, Majid Janidarmian, Katarzyna Radecka, Zeljko Zilic
2014	—	`conf`	A hybrid arithmetic transform for precision analysis of floating-point polynomial specifications. NEWCAS Omid Sarbishei, Katarzyna Radecka, Zeljko Zilic
2014	—	`conf`	Affordable erehabilitation monitoring platform. IHTC Majid Janidarmian, Atena Roshan Fekr, Katarzyna Radecka, Zeljko Zilic
2014	—	`conf`	Automated diagnosis of knee pathology using sensory data. MobiHealth Majid Janidarmian, Katarzyna Radecka, Zeljko Zilic
2014	C	`conf`	Design of an e-Health Respiration and Body Posture Monitoring System and Its Application for Rib Cage and Abdomen Synchrony Analysis. BIBE Atena Roshan Fekr, Katarzyna Radecka, Zeljko Zilic
2014	—	`conf`	Development of a Remote Monitoring System for Respiratory Analysis. IoT360 (1) Atena Roshan Fekr, Majid Janidarmian, Katarzyna Radecka, Zeljko Zilic
2014	—	`conf`	Multi-sensor blind recalibration in mHealth applications. IHTC Atena Roshan Fekr, Majid Janidarmian, Katarzyna Radecka, Zeljko Zilic
2014	—	`conf`	Tidal volume variability and respiration rate estimation using a wearable accelerometer sensor. MobiHealth Atena Roshan Fekr, Katarzyna Radecka, Zeljko Zilic
2013	B	`conf`	A minimum MSE sensor fusion algorithm with tolerance to multiple faults. ETS Omid Sarbishei, Atena Roshan Fekr, Majid Janidarmian, Benjamin Nahill, Katarzyna Radecka
2013	C	`conf`	An efficient fault-tolerant sensor fusion algorithm for accelerometers. BSN Omid Sarbishei, Benjamin Nahill, Atena Roshan Fekr, Majid Janidarmian, Katarzyna Radecka, Zeljko Zilic, Boris Karajica
2013	J	`jnl`	On the Fixed-Point Accuracy Analysis and Optimization of Polynomial Specifications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Omid Sarbishei, Katarzyna Radecka
2013	—	`conf`	SAR Computation and Channel Modeling of Body Area Network. BODYNETS Yu Pang, Qian Lei, Jinzhao Lin, Zhiyong Luo, Zhangyong Li, Zeljko Zilic, Katarzyna Radecka
2013	—	`conf`	SAT-based reversible gate/wire replacement fault testing. MWSCAS Sayeeda Sultana, Atena Roshan Fekr, Katarzyna Radecka
2013	—	`conf`	Testing reversible adder/subtractor for missing control points. MWSCAS Sayeeda Sultana, Katarzyna Radecka
2012	J	`jnl`	Analytical Optimization of Bit-Widths in Fixed-Point LTI Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Omid Sarbishei, Katarzyna Radecka, Zeljko Zilic
2012	—	`conf`	Fixed-point accuracy analysis of datapaths with mixed CORDIC and polynomial computations. ASP-DAC Omid Sarbishei, Katarzyna Radecka
2012	—	`conf`	Issues in Multi-valued Multi-modal Sensor Fusion. ISMVL Majid Janidarmian, Zeljko Zilic, Katarzyna Radecka
2012	C	`conf`	MSE minimization and fault-tolerant data fusion for multi-sensor systems. ICCD Atena Roshan Fekr, Majid Janidarmian, Omid Sarbishei, Benjamin Nahill, Katarzyna Radecka, Zeljko Zilic
2012	C	`conf`	Verification of fixed-point datapaths with comparator units using Constrained Arithmetic Transform (CAT). ISCAS Omid Sarbishei, Katarzyna Radecka
2011	C	`conf`	A novel method of synthesizing reversible logic. ISCAS Yu Pang, Jinzhao Lin, Sayeeda Sultana, Katarzyna Radecka
2011	C	`conf`	A study on relating redundancy removal in classical circuits to reversible mapping. ICCD Sayeeda Sultana, Katarzyna Radecka, Yu Pang
2011	C	`conf`	An efficient algorithm of performing range analysis for fixed-point arithmetic circuits based on SAT checking. ISCAS Yu Pang, Katarzyna Radecka
2011	—	`conf`	An efficient hybrid engine to perform range analysis and allocate integer bit-widths for arithmetic circuits. ASP-DAC Yu Pang, Katarzyna Radecka, Zeljko Zilic
2011	C	`conf`	Analysis of Mean-Square-Error (MSE) for fixed-point FFT units. ISCAS Omid Sarbishei, Katarzyna Radecka
2011	—	`conf`	Fault tolerant glucose sensor readout and recalibration. Wireless Health Zeljko Zilic, Katarzyna Radecka
2011	C	`conf`	On the Fixed-Point Accuracy Analysis and Optimization of FFT Units with CORDIC Multipliers. IEEE Symposium on Computer Arithmetic Omid Sarbishei, Katarzyna Radecka
2011	C	`conf`	Positive Davio-based synthesis algorithm for reversible logic. ICCD Yu Pang, Shaoquan Wang, Zhilong He, Jinzhao Lin, Sayeeda Sultana, Katarzyna Radecka
2011	—	`conf`	Rev-Map: A Direct Gateway from Classical Irreversible Network to Reversible Network. ISMVL Sayeeda Sultana, Katarzyna Radecka
2011	—	`conf`	Reversible implementation of square-root circuit. ICECS Sayeeda Sultana, Katarzyna Radecka
2010	—	`conf`	An efficient method to perform range analysis for DSP circuits. ICECS Yu Pang, Katarzyna Radecka, Zeljko Zilic
2010	A	`conf`	Analysis of precision for scaling the intermediate variables in fixed-point arithmetic circuits. ICCAD Omid Sarbishei, Katarzyna Radecka
2010	—	`conf`	Analysis of range and precision for fixed-point linear arithmetic circuits with feedbacks. HLDVT Omid Sarbishei, Yu Pang, Katarzyna Radecka
2010	J	`jnl`	Optimization of Imprecise Circuits Represented by Taylor Series and Real-Valued Polynomials. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yu Pang, Katarzyna Radecka, Zeljko Zilic
2008	J	`jnl`	Design for Testability of QCA Logic Under Stuck-at-value Fault Model. J. Multiple Valued Log. Soft Comput. Sayeeda Sultana, Shahriar Al-Imam, Katarzyna Radecka
2008	A*	`conf`	Optimizing imprecise fixed-point arithmetic circuits specified by Taylor Series through arithmetic transform. DAC Yu Pang, Katarzyna Radecka
2007	J	`jnl`	Adiabatic Implementation of Reversible Logic Circuits in CMOS Technology. J. Multiple Valued Log. Soft Comput. Ali Khazamipour, Katarzyna Radecka
2007	A	`conf`	Reversible circuit technology mapping from non-reversible specifications. DATE Zeljko Zilic, Katarzyna Radecka, Ali Kazamiphur
2007	J	`jnl`	Scaling and Better Approximating Quantum Fourier Transform by Higher Radices. IEEE Trans. Computers Zeljko Zilic, Katarzyna Radecka
2006	—	`conf`	Algorithms for Compositions of Arithmetic Transforms and Their Extensions. ICECS Yu Pang, Katarzyna Radecka, Zeljko Zilic
2006	—	`conf`	Arithmetic Transforms of Imprecise Datapaths by Taylor Series Conversion. ICECS Yu Pang, Katarzyna Radecka, Zeljko Zilic
2006	Misc	`conf`	Energy Efficient Software-Based Self-Test for Wireless Sensor Network Nodes. VTS Rong Zhang, Zeljko Zilic, Katarzyna Radecka
2006	—	`conf`	Testing QCA Modular Logic. ICECS Sayeeda Sultana, Shahriar Al-Imam, Katarzyna Radecka
2004	A	`conf`	Architectures of Increased Availability Wireless Sensor Network Nodes. ITC Man Wah Chiang, Zeljko Zilic, Jean-Samuel Chenard, Katarzyna Radecka
2004	J	`jnl`	Design Verification by Test Vectors and Arithmetic Transform Universal Test Set. IEEE Trans. Computers Katarzyna Radecka, Zeljko Zilic
2004	C	`conf`	FPGA Emulation of Quantum Circuits. ICCD Ahmed Usman Khalid, Zeljko Zilic, Katarzyna Radecka
2002	—	`conf`	Identifying Redundant Wire Replacements for Synthesis and Verification. ASP-DAC/VLSI Design Katarzyna Radecka, Zeljko Zilic
2002	A	`conf`	Specifying and verifying imprecise sequential datapaths by Arithmetic Transforms. ICCAD Katarzyna Radecka, Zeljko Zilic
2002	—	`conf`	The Role of Super-Fast Transforms in Speeding Up Quantum Computations. ISMVL Zeljko Zilic, Katarzyna Radecka
2001	A	`conf`	: Identifying redundant gate replacements in verification by error modeling. ITC Zeljko Zilic, Katarzyna Radecka
2001	C	`conf`	Arithmetic Transforms for Verifying Compositions of Sequential Datapaths. ICCD Katarzyna Radecka, Zeljko Zilic
2001	—	`conf`	Combinational verification by simulations, SAT and BDDs. ICECS Katarzyna Radecka, Zeljko Zilic, Karim Khordoc
2000	Misc	`conf`	Using Arithmetic Transform for Verification of Datapath Circuits via Error Modeling. VTS Katarzyna Radecka, Zeljko Zilic
1999	B	`conf`	On Feasible Multivariate Polynomial Interpolations over Arbitrary Fields. ISSAC Zeljko Zilic, Katarzyna Radecka
1997	J	`jnl`	Arithmetic built-in self-test for DSP cores. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Katarzyna Radecka, Janusz Rajski, Jerzy Tyszer