Kartikeya Mayaram

122 papers A* 3A 9C 9Journal 47Unranked 53
YearRankTypeTitle / Venue / Authors
2020 J jnl
A Highly Linear OTA-Less 1-1 MASH VCO-Based ΔΣ ADC With an Efficient Phase Quantization Noise Extraction Technique.
IEEE J. Solid State Circuits
Hamidreza Maghami, Pedram Payandehnia, Hossein Mirzaie, Ramin Zanbaghi, Hossein Zareie, Justin B. Goins, Siladitya Dey, Kartikeya Mayaram, Terri S. Fiez
2019 — conf
0.9V, 79.7dB SNDR, 2MHz-BW, Highly linear OTA-less 1-1 MASH VCO-based ΔΣ with a Novel Phase Quantization Noise Extraction Technique.
CICC
Hamidreza Maghami, Pedram Payandehnia, Hossein Mirzaie, Ramin Zanbaghi, Siladitya Dey, Justin B. Goins, Kartikeya Mayaram, Terri S. Fiez
2019 — conf
A 12 MHz BW, 80 dB SNDR, 83 dB DR, 4
CICC
Siladitya Dey, Kartikeya Mayaram, Terri S. Fiez
2019 J jnl
A 72.4-dB SNDR 92-dB SFDR Blocker Tolerant CT $\Delta\Sigma$ Modulator With Inherent DWA.
IEEE Trans. Circuits Syst. II Express Briefs
Hossein Mirzaie, Hamidreza Maghami, Ramin Zanbaghi, Pedram Payandehnia, Kartikeya Mayaram, Terri S. Fiez
2019 J jnl
A Highly Linear OTA-Free VCO-Based 1-1 MASH $\Delta\Sigma$ ADC.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hamidreza Maghami, Pedram Payandehnia, Hossein Mirzaie, Ramin Zanbaghi, Siladitya Dey, Kartikeya Mayaram, Terri S. Fiez
2018 J jnl
A 50 MHz BW 76.1 dB DR Two-Stage Continuous-Time Delta-Sigma Modulator With VCO Quantizer Nonlinearity Cancellation.
IEEE J. Solid State Circuits
Siladitya Dey, Karthikeyan Reddy, Kartikeya Mayaram, Terri S. Fiez
2018 — conf
A Novel Time-Domain Phase Quantization Noise Extraction for a VCO-based Quantizer.
MWSCAS
Hamidreza Maghami, Hossein Mirzaie, Pedram Payandehnia, Kartikeya Mayaram, Ramin Zanbaghi, Terri S. Fiez
2017 J jnl
A 1-to-2048 Fully-Integrated Cascaded Digital Frequency Synthesizer for Low Frequency Reference Clocks Using Scrambling TDC.
IEEE Trans. Circuits Syst. I Regul. Pap.
Romesh Kumar Nandwana, Saurabh Saxena, Amr Elshazly, Kartikeya Mayaram, Pavan Kumar Hanumolu
2017 — conf
A 50 MHz BW 73.5 dB SNDR two-stage continuous-time ΔΣ modulator with VCO quantizer nonlinearity cancellation.
CICC
Siladitya Dey, Karthikeyan Reddy, Kartikeya Mayaram, Terri S. Fiez
2017 C conf
A highly linear OTA-free VCO-based 1-1 MASH ΔΣ ADC.
ISCAS
Hamidreza Maghami, Pedram Payandehnia, Hossein Mirzaie, Kartikeya Mayaram, Ramin Zanbaghi, Terri S. Fiez
2016 J jnl
Fast start-up analysis of resonator based oscillators using a power generation method.
IET Circuits Devices Syst.
Ankur Guha Roy, Kartikeya Mayaram, Terri S. Fiez
2016 — conf
JetNet: A proposed protocol for reliable packet delivery in low-power IoT applications.
WF-IoT
Justin B. Goins, Ankur Guha Roy, Kartikeya Mayaram, Terri S. Fiez
2015 J jnl
350 mV, 5 GHz Class-D Enhanced Swing Differential and Quadrature VCOs in 65 nm CMOS.
IEEE J. Solid State Circuits
Ankur Guha Roy, Siladitya Dey, Justin B. Goins, Terri S. Fiez, Kartikeya Mayaram
2014 — conf
A 350 mV, 5 GHz class-D enhanced swing quadrature VCO in 65 nm CMOS with 198.3 dBc/Hz FoM.
CICC
Ankur Guha Roy, Siladitya Dey, Justin B. Goins, Kartikeya Mayaram, Terri S. Fiez
2014 — conf
A 915MHz, 6Mb/s, 80pJ/b BFSK receiver with -76dBm sensitivity for high data rate wireless sensor networks.
VLSIC
Ronghua Ni, Kartikeya Mayaram, Terri S. Fiez
2013 J jnl
A 2.4 GHz Hybrid Polyphase Filter Based BFSK Receiver With High Frequency Offset Tolerance for Wireless Sensor Networks.
IEEE J. Solid State Circuits
Ronghua Ni, Kartikeya Mayaram, Terri S. Fiez
2012 J jnl
A 12.5-bit 4 MHz 13.8 mW MASH ΔΣ Modulator With Multirated VCO-Based ADC.
IEEE Trans. Circuits Syst. I Regul. Pap.
Samira Zali Asl, Saurabh Saxena, Pavan Kumar Hanumolu, Kartikeya Mayaram, Terri S. Fiez
2012 — conf
A 2.4GHz hybrid PPF based BFSK receiver with ±180ppm frequency offset tolerance for wireless sensor networks.
VLSIC
Ronghua Ni, Kartikeya Mayaram, Terri S. Fiez
2012 J jnl
Experimental Characterization and Analysis of an Asynchronous Approach for Reduction of Substrate Noise in Digital Circuitry.
IEEE Trans. Very Large Scale Integr. Syst.
Jim Le, Christopher Hanken, Martin Held, Michael S. Hagedorn, Kartikeya Mayaram, Terri S. Fiez
2011 J jnl
A 250 mV, 352 μ W GPS Receiver RF Front-End in 130 nm CMOS.
IEEE J. Solid State Circuits
Adam C. Heiberg, Thomas William Brown, Terri S. Fiez, Kartikeya Mayaram
2011 J jnl
A 475 mV, 4.9 GHz Enhanced Swing Differential Colpitts VCO With Phase Noise of -136 dBc/Hz at a 3 MHz Offset Frequency.
IEEE J. Solid State Circuits
Thomas William Brown, Farhad Farhabakhshian, Ankur Guha Roy, Terri S. Fiez, Kartikeya Mayaram
2011 — conf
A 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer.
CICC
Samira Zali Asl, Saurabh Saxena, Pavan Kumar Hanumolu, Kartikeya Mayaram, Terri S. Fiez
2011 J jnl
A Multiple-Input Boost Converter for Low-Power Energy Harvesting.
IEEE Trans. Circuits Syst. II Express Briefs
Chao Shi, Brian Miller, Kartikeya Mayaram, Terri S. Fiez
2011 J jnl
Design-Oriented Analysis of Circuits With Equality Constraints.
IEEE Trans. Circuits Syst. I Regul. Pap.
Igor Vytyaz, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram
2010 — conf
A 475 mV, 4.9 GHz enhanced swing differential Colpitts VCO in 130 nm CMOS with an FoM of 196.2 dBc/Hz.
CICC
Farhad Farhabakhshian, Thomas William Brown, Kartikeya Mayaram, Terri S. Fiez
2010 J jnl
An Ultralow-Power Receiver for Wireless Sensor Networks.
IEEE J. Solid State Circuits
James Ayers, Kartikeya Mayaram, Terri S. Fiez
2009 J jnl
A Digital PLL With a Stochastic Time-to-Digital Converter.
IEEE Trans. Circuits Syst. I Regul. Pap.
Volodymyr Kratyuk, Pavan Kumar Hanumolu, Kerem Ok, Un-Ku Moon, Kartikeya Mayaram
2009 J jnl
Automated Design and Optimization of Low-Noise Oscillators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Igor Vytyaz, David C. Lee, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram
2009 — conf
Comparison of supply noise and substrate noise reduction in SiGe BiCMOS and FDSOI processes.
ISQED
Wai Leng Cheong, Brian E. Owens, Hui En Pham, Christopher Hanken, Jim Le, Terri S. Fiez, Kartikeya Mayaram
2009 J jnl
Method for a Constant Loop Bandwidth in LC-VCO PLL Frequency Synthesizers.
IEEE J. Solid State Circuits
Ting Wu, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon
2008 — conf
A 0.4 nJ/b 900MHz CMOS BFSK super-regenerative receiver.
CICC
James Ayers, Kartikeya Mayaram, Terri S. Fiez
2008 — conf
A 900-MHz low-power transmitter with fast frequency calibration for wireless sensor networks.
CICC
Napong Panitantum, Kartikeya Mayaram, Terri S. Fiez
2008 J jnl
Efficient Far-Field Radio Frequency Energy Harvesting for Passively Powered Sensor Networks.
IEEE J. Solid State Circuits
Triet Le, Kartikeya Mayaram, Terri S. Fiez
2008 J jnl
Extraction of Parasitics in Inhomogeneous Substrates With a New Green Function-Based Method.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chenggang Xu, Ranjit Gharpurey, Terri S. Fiez, Kartikeya Mayaram
2008 — conf
Noise tolerant oscillator design using perturbation projection vector analysis.
CICC
Igor Vytyaz, Josh Carnes, Ting Wu, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram
2008 C conf
Parameter variation analysis for voltage controlled oscillators in phase-locked loops.
ISCAS
Igor Vytyaz, David C. Lee, Un-Ku Moon, Kartikeya Mayaram
2008 A conf
Periodic Steady-State Analysis Augmented with Design Equality Constraints.
DATE
Igor Vytyaz, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram
2008 J jnl
Sensitivity Analysis for Oscillators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Igor Vytyaz, David C. Lee, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram
2007 — conf
A 0.6GHz to 2GHz Digital PLL with Wide Tracking Range.
CICC
Volodymyr Kratyuk, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon
2007 — conf
A 4.2 GHz PLL Frequency Synthesizer with an Adaptively Tuned Coarse Loop.
CICC
Ting Wu, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon
2007 J jnl
A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy.
IEEE Trans. Circuits Syst. II Express Briefs
Volodymyr Kratyuk, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram
2007 C conf
A Low Power BFSK Super-Regenerative Transceiver.
ISCAS
James Ayers, Kartikeya Mayaram, Terri S. Fiez
2007 J jnl
An On-chip Calibration Technique for Reducing Supply Voltage Sensitivity in Ring Oscillators.
IEEE J. Solid State Circuits
Ting Wu, Kartikeya Mayaram, Un-Ku Moon
2007 — conf
Automated Extraction of Model Parameters for Noise Coupling Analysis in Silicon Substrates.
CICC
Brett Peterson, Kartikeya Mayaram, Terri S. Fiez
2007 — conf
Design and Analysis of Noise Tolerant Ring Oscillators Using Maneatis Delay Cells.
ICECS
Josh Carnes, Igor Vytyaz, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon
2007 C conf
Design of Very Low Noise 4.2GHz Clapp VCOs.
ISCAS
Raghuram Jonnalagedda, Kartikeya Mayaram
2007 — conf
Digitally-Enhanced Phase-Locking Circuits.
CICC
Pavan Kumar Hanumolu, Gu-Yeon Wei, Un-Ku Moon, Kartikeya Mayaram
2007 C conf
Issues in the Design and Simulation of a MEMS VCO based Phase-Locked Loop.
ISCAS
Maneesha Yellepeddi, Kartikeya Mayaram
2007 C conf
Noise Simulation and Modeling for MEMS Varactor Based RF VCOs.
ISCAS
Janakiram G. Sankaranarayanan, Kartikeya Mayaram
2007 A* conf
Parameter Finding Methods for Oscillators with a Specified Oscillation Frequency.
DAC
Igor Vytyaz, David C. Lee, Suihua Lu, Amit Mehrotra, Un-Ku Moon, Kartikeya Mayaram
2007 C conf
Periodic Steady-State Analysis of Oscillators with a Specified Oscillation Frequency.
ISCAS
Igor Vytyaz, David C. Lee, Suihua Lu, Amit Mehrotra, Un-Ku Moon, Kartikeya Mayaram
2007 A conf
Sensitivity analysis for oscillators.
ICCAD
Igor Vytyaz, David C. Lee, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram
2007 — conf
Simulation and Modeling of Substrate Noise Generation from Synchronous and Asynchronous Digital Logic Circuits.
CICC
Christopher Hanken, Jim Le, Terri S. Fiez, Kartikeya Mayaram
2007 C conf
Tradeoffs in the Design of CMOS Receivers for Low Power Wireless Sensor Networks.
ISCAS
James Ayers, Kartikeya Mayaram, Terri S. Fiez
2006 — conf
A 0.5 to 2.5GHz PLL with Fully Differential Supply-Regulated Tuning.
ISSCC
Merrick Brownlee, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon
2006 J jnl
A 0.5-GHz to 2.5-GHz PLL With Fully Differential Supply Regulated Tuning.
IEEE J. Solid State Circuits
Merrick Brownlee, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon
2006 J jnl
A comparison of substrate noise coupling in lightly and heavily doped CMOS processes for 2.4-GHz LNAs.
IEEE J. Solid State Circuits
Scott Hazenboom, Terri S. Fiez, Kartikeya Mayaram
2006 J jnl
An error control method for application of the discrete cosine transform to extraction of substrate parasitics in ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram
2006 J jnl
CEDA Currents.
IEEE Des. Test Comput.
Kartikeya Mayaram
2006 — conf
Comparison and Impact of Substrate Noise Generated by Clocked and Clockless Digital Circuitry.
CICC
Jim Le, Christopher Hanken, Martin Held, Michael S. Hagedorn, Kartikeya Mayaram, Terri S. Fiez
2006 J jnl
Comparison of Algorithms for Frequency Domain Coupled Device and Circuit Simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yutao Hu, Kartikeya Mayaram
2006 C conf
Dependence of LC VCO oscillation frequency on bias current.
ISCAS
Ting Wu, Un-Ku Moon, Kartikeya Mayaram
2006 — conf
Efficient Far-Field Radio Frequency Power Conversion System for Passively Powered Sensor Networks.
CICC
Triet Le, Kartikeya Mayaram, Terri S. Fiez
2006 J jnl
Frequency-Domain Simulation of Ring Oscillators With a Multiple-Probe Method.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xiaochun Duan, Kartikeya Mayaram
2006 J jnl
Piezoelectric micro-power generation interface circuits.
IEEE J. Solid State Circuits
Triet Le, Jifeng Han, Annette R. von Jouanne, Kartikeya Mayaram, Terri S. Fiez
2006 J jnl
Robust Simulation of High-Q Oscillators Using a Homotopy-Based Harmonic Balance Method.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xiaochun Duan, Kartikeya Mayaram
2006 J jnl
Schematic-Driven Substrate Noise Coupling Analysis in Mixed-Signal IC Designs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Patrick Birrer, Sasi Kumar Arunachalam, Martin Held, Kartikeya Mayaram, Terri S. Fiez
2006 — conf
Sizing Ground Taps to Minimize Substrate Noise Coupling in RF LNAs.
CICC
Arathi Sundaresan, Terri S. Fiez, Kartikeya Mayaram
2005 A* conf
A green function-based parasitic extraction method for inhomogeneous substrate layers.
DAC
Chenggang Xu, Ranjit Gharpurey, Terri S. Fiez, Kartikeya Mayaram
2005 — conf
A low spur fractional-N frequency synthesizer architecture.
ISCAS (3)
Volodymyr Kratyuk, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram
2005 — conf
A multiple-probe approach for robust frequency domain ring oscillator simulation.
CICC
Xiaochun Duan, Kartikeya Mayaram
2005 — conf
A new approach for ring oscillator simulation using the harmonic balance method.
ASP-DAC
Xiaochun Duan, Kartikeya Mayaram
2005 J jnl
Accurate Prediction of Substrate Parasitics in Heavily Doped CMOS Processes Using a Calibrated Boundary Element Solver.
IEEE Trans. Very Large Scale Integr. Syst.
Ajit Sharma, Patrick Birrer, Sasi Kumar Arunachalam, Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram
2005 J jnl
Accurate and efficient simulation of synchronous digital switching noise in systems on a chip.
IEEE Trans. Very Large Scale Integr. Syst.
Husni M. Habal, Kartikeya Mayaram, Terri S. Fiez
2005 — conf
An FMDLL based dual-loop frequency synthesizer for 5 GHz WLAN applications.
ISCAS (4)
Ting Wu, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram
2005 J jnl
An efficient and robust method for ring-oscillator simulation using the harmonic-balance method.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xiaochun Duan, Kartikeya Mayaram
2005 — conf
Analysis of supply and ground noise sensitivity in ring and LC oscillators.
ISCAS (6)
Volodymyr Kratyuk, Igor Vytyaz, Un-Ku Moon, Kartikeya Mayaram
2005 J jnl
On the numerical stability of Green's function for substrate coupling in integrated circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram
2005 J jnl
Simulation and measurement of supply and substrate noise in mixed-signal ICs.
IEEE J. Solid State Circuits
Brian E. Owens, Sirisha Adluri, Patrick Birrer, Robert Shreeve, Sasi Kumar Arunachalam, Kartikeya Mayaram, Terri S. Fiez
2004 — conf
A modified-Volterra-series technique for improving the accuracy of quasi-static harmonic balance analysis in coupled device and circuit simulation.
CICC
Yutao Hu, Kartikeya Mayaram
2004 — conf
A physical and analytical model for substrate noise coupling analysis.
ISCAS (5)
Robert Shreeve, Terri S. Fiez, Kartikeya Mayaram
2004 — conf
A predictive methodology for accurate substrate parasitic extraction.
ISCAS (5)
Ajit Sharma, Chenggang Xu, Wen Kung Chu, Nishath K. Verghese, Terri S. Fiez, Kartikeya Mayaram
2004 — conf
Accurate simulation of phase noise in RF MEMS VCOs.
ISCAS (3)
Manas Behera, Volodymyr Kratyuk, Yutao Hu, Kartikeya Mayaram
2004 — conf
An accurate and efficient estimation of switching noise in synchronous digital circuits.
ISCAS (2)
Husni M. Habal, Terri S. Fiez, Kartikeya Mayaram
2004 J jnl
An efficient formulation for substrate parasitic extraction accounting for nonuniform current distribution.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram
2004 — conf
An improved Z-parameter macro model for substrate noise coupling.
ISCAS (5)
Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram
2004 J jnl
Analysis of charge-pump phase-locked loops.
IEEE Trans. Circuits Syst. I Regul. Pap.
Pavan Kumar Hanumolu, Merrick Brownlee, Kartikeya Mayaram, Un-Ku Moon
2004 — conf
CrtSmile: a CAD tool for CMOS RF transistor substrate modeling incorporating layout effects.
ASP-DAC
Zhao Li, Ravikanth Suravarapu, Roy Hartono, Sambuddha Bhattacharya, Kartikeya Mayaram, Chuanjin Richard Shi
2004 — conf
Digital noise coupling mechanisms in a 2.4 GHz LNA for heavily and lightly doped CMOS substrates.
CICC
Scott Hazenboom, Terri S. Fiez, Kartikeya Mayaram
2004 A conf
Frequency domain simulation of high-Q oscillators with homotopy methods.
ICCAD
Xiaochun Duan, Kartikeya Mayaram
2004 — conf
Silencer!: a tool for substrate noise coupling analysis.
SoCC
Patrick Birrer, Terri S. Fiez, Kartikeya Mayaram
2003 — conf
A comparison of non-quasi-static and quasi-static harmonic balance implementations for coupled device and circuit simulation.
CICC
Yutao Hu, Kartikeya Mayaram
2003 — conf
Coupled Simulation of Circuit and Piezoelectric Laminates.
ISQED
Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram
2003 — conf
Piezoelectric power generation interface circuits.
CICC
Triet Le, Jifeng Han, Annette R. von Jouanne, Kartikeya Mayaram, Terri S. Fiez
2003 — conf
Strategies for simulation, measurement and suppression of digital noise in mixed-signal circuits.
CICC
Brian E. Owens, Patrick Birrer, Sirisha Adluri, Robert Shreeve, Sasi Kumar Arunachalam, Husni Habal, Shu-Ching Hsu, Ajit Sharma, Kartikeya Mayaram, Terri S. Fiez
2003 A conf
Symbolic Analysis of Nonlinear Analog Circuits.
DATE
Alicia Manthe, Zhao Li, Chuanjin Richard Shi, Kartikeya Mayaram
2002 — conf
A comprehensive geometry-dependent macromodel for substrate noise coupling in heavily doped CMOS processes.
CICC
Dicle Ozis, Terri S. Fiez, Kartikeya Mayaram
2002 — conf
An efficient algorithm for large-signal frequency-domain coupled device and circuit simulation [RF circuits].
ISCAS (5)
Yutao Hu, Kartikeya Mayaram
2002 — conf
An efficient modeling approach for substrate noise coupling analysis.
ISCAS (5)
Dicle Ozis, Kartikeya Mayaram, Terri S. Fiez
2002 — conf
Analysis of CMOS RF LNAs with ESD protection.
ISCAS (4)
V. Chandrasekhar, Kartikeya Mayaram
2002 — conf
Analysis of jitter in ring oscillators due to deterministic noise.
ISCAS (4)
Nathen Barton, Dicle Özis, Terri S. Fiez, Kartikeya Mayaram
2002 — conf
Design of low power 2.4 GHz CMOS LC oscillators with low phase-noise and large tuning range.
ISCAS (4)
N. Seshan, J. Rajagopalan, Kartikeya Mayaram
2002 — conf
HomSSPICE: a homotopy-based circuit simulator for periodic steady-state analysis of oscillators.
ISCAS (1)
Wanliang Ma, Ljiljana Trajkovic, Kartikeya Mayaram
2002 — conf
The effect of supply and substrate noise on jitter in ring oscillators.
CICC
Nathen Barton, Dicle Ozis, Terri S. Fiez, Kartikeya Mayaram
2000 J jnl
A scalable substrate noise coupling model for design of mixed-signal IC's.
IEEE J. Solid State Circuits
Anil Samavedam, Aline Sadate, Kartikeya Mayaram, Terri S. Fiez
2000 J jnl
A simple and accurate method for calculating the low frequency common-mode gain in a MOS differential amplifier with a current-mirror load.
IEEE Trans. Educ.
Ruoxin Jiang, Haiming Tang, Kartikeya Mayaram
2000 J jnl
A simple subcircuit extension of the BSIM3v3 model for CMOS RF design.
IEEE J. Solid State Circuits
Suet Fong Tin, Ashraf A. Osman, Kartikeya Mayaram, Chenming Hu
2000 — conf
Neural Network Design for Behavioral Model Generation with Shape Preserving Properties.
BMAS
Oleg Mikulchenko, Kartikeya Mayaram
1999 A conf
A scalable substrate noise coupling model for mixed-signal ICs.
ICCAD
Anil Samavedam, Kartikeya Mayaram, Terri S. Fiez
1999 — conf
Design-oriented substrate noise coupling macromodels for heavily doped CMOS processes.
ISCAS (6)
Anil Samavedam, Kartikeya Mayaram, Terri S. Fiez
1999 — conf
Substrate network modeling for CMOS RF circuit simulation.
CICC
Suet Fong Tin, Kartikeya Mayaram
1998 J jnl
Comments on "A small-signal MOSFET model for radio frequency IC applications".
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Suet Fong Tin, Ashraf A. Osman, Kartikeya Mayaram
1993 J jnl
A new matrix solution technique for general circuit simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Richard Burch, Ping Yang, Paul F. Cox, Kartikeya Mayaram
1993 J jnl
Algorithms for transient three-dimensional mixed-level circuit and device simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kartikeya Mayaram, Jue-Hsien Chern, Ping Yang
1992 J jnl
Coupling algorithms for mixed-level circuit and device simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kartikeya Mayaram, Donald O. Pederson
1991 A conf
Transient Three-Dimensional Mixed-Level Circuit and Device Simulation: Algorithms and Applications.
ICCAD
Kartikeya Mayaram, Ping Yang, Jue-Hsien Chern
1990 A conf
A Parallel Block-Diagonal Preconditioned Conjugate-Gradient Solution Algorithm for Circuit and Device Simulations.
ICCAD
Kartikeya Mayaram, Ping Yang, Jue-Hsien Chern, Richard Burch, Lawrence A. Arledge Jr., Paul F. Cox
1990 — book
Analog integrated circuits for communication - principles, simulation and design.
Donald O. Pederson, Kartikeya Mayaram
1989 A conf
PGS and PLUCGS-two new matrix solution techniques for general circuit simulation.
ICCAD
Richard Burch, Kartikeya Mayaram, Jue-Hsien Chern, Ping Yang, Paul F. Cox
1988 A conf
CODECS: a fixed mixed-level device and circuit simulator.
ICCAD
Kartikeya Mayaram, Donald O. Pederson
1988 J jnl
Techniques for multilayer channel routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Douglas Braun, Jeffrey L. Burns, Fabio Romeo, Alberto L. Sangiovanni-Vincentelli, Kartikeya Mayaram, Srinivas Devadas, Hi-Keung Tony Ma
1986 A* conf
Chameleon: a new multi-layer channel router.
DAC
Douglas Braun, Jeffrey L. Burns, Srinivas Devadas, Hi-Keung Tony Ma, Kartikeya Mayaram, Fabio Romeo, Alberto L. Sangiovanni-Vincentelli