Kartik Mohanram

86 papers A* 12A 27B 1C 3Misc 5Journal 18Unranked 20

Year	Rank	Type	Title / Venue / Authors
2019	—	`conf`	ASSET: Architectures for Smart Security of Non-Volatile Memories. ISVLSI Shivam Swami, Kartik Mohanram
2018	A*	`conf`	ACME: advanced counter mode encryption for secure non-volatile memories. DAC Shivam Swami, Kartik Mohanram
2018	A	`conf`	ADAM: Architecture for write disturbance mitigation in scaled phase change memory. DATE Shivam Swami, Kartik Mohanram
2018	J	`jnl`	ARSENAL: Architecture for Secure Non-Volatile Memories. IEEE Comput. Archit. Lett. Shivam Swami, Kartik Mohanram
2018	A*	`conf`	CASTLE: compression architecture for secure low latency, low energy, high endurance NVMs. DAC Poovaiah M. Palangappa, Kartik Mohanram
2018	J	`jnl`	LEO: Low Overhead Encryption ORAM for Non-Volatile Memories. IEEE Comput. Archit. Lett. Joydeep Rakshit, Kartik Mohanram
2018	J	`jnl`	MFNW: An MLC/TLC Flip-N-Write Architecture. ACM J. Emerg. Technol. Comput. Syst. Ali Alsuwaiyan, Kartik Mohanram
2018	A	`conf`	RAPID: read acceleration for improved performance and endurance in MLC/TLC NVMs. ICCAD Poovaiah M. Palangappa, Kartik Mohanram
2018	C	`conf`	ReadPRO: Read Prioritization Scheduling in ORAM for Efficient Obfuscation in Main Memories. ICCD Joydeep Rakshit, Kartik Mohanram
2018	A*	`conf`	STASH: security architecture for smart hybrid memories. DAC Shivam Swami, Joydeep Rakshit, Kartik Mohanram
2017	A*	`conf`	ASSURE: Authentication Scheme for SecURE Energy Efficient Non-Volatile Memories. DAC Joydeep Rakshit, Kartik Mohanram
2017	A	`conf`	COVERT: Counter OVErflow ReducTion for efficient encryption of non-volatlle memories. DATE Shivam Swami, Kartik Mohanram
2017	J	`jnl`	CompEx++: Compression-Expansion Coding for Energy, Latency, and Lifetime Improvements in MLC/TLC NVMs. ACM Trans. Archit. Code Optim. Poovaiah M. Palangappa, Kartik Mohanram
2017	J	`jnl`	ECS: Error-Correcting Strings for Lifetime Improvements in Nonvolatile Memories. ACM Trans. Archit. Code Optim. Shivam Swami, Poovaiah M. Palangappa, Kartik Mohanram
2017	—	`conf`	L NANOARCH Ali Alsuwaiyan, Kartik Mohanram
2017	J	`jnl`	Reliable Nonvolatile Memories: Techniques and Measures. IEEE Des. Test Shivam Swami, Kartik Mohanram
2017	Misc	`conf`	Virtual Two-Port Memory Architecture for Asymmetric Memory Technologies. VLSID Jiayin Li, Kartik Mohanram
2016	—	`conf`	An Offline Frequent Value Encoding for Energy-Efficient MLC/TLC Non-volatile Memories. ACM Great Lakes Symposium on VLSI Ali Alsuwaiyan, Kartik Mohanram
2016	A*	`conf`	CompEx: Compression-expansion coding for energy, latency, and lifetime improvements in MLC/TLC NVM. HPCA Poovaiah M. Palangappa, Kartik Mohanram
2016	Misc	`conf`	E3R: Energy Efficient Error Recovery for Multi/Triple-Level Cell Non-volatile Memories. VLSID Shivam Swami, Kartik Mohanram
2016	J	`jnl`	Monolayer Transistor SRAMs: Toward Low-Power, Denser Memory Systems. ACM J. Emerg. Technol. Comput. Syst. Joydeep Rakshit, Kartik Mohanram, Runlai Wan, Kai Tak Lam, Jing Guo
2016	A*	`conf`	SECRET: smartly EnCRypted energy efficient non-volatile memories. DAC Shivam Swami, Joydeep Rakshit, Kartik Mohanram
2016	J	`jnl`	WOM-Code Solutions for Low Latency and High Endurance in Phase Change Memory. IEEE Trans. Computers Poovaiah M. Palangappa, Jiayin Li, Kartik Mohanram
2015	—	`conf`	Flip-Mirror-Rotate: An Architecture for Bit-write Reduction and Wear Leveling in Non-volatile Memories. ACM Great Lakes Symposium on VLSI Poovaiah M. Palangappa, Kartik Mohanram
2015	—	`conf`	MFNW: A Flip-N-Write architecture for multi-level cell non-volatile memories. NANOARCH Ali Alsuwaiyan, Kartik Mohanram
2015	A*	`conf`	Monolayer transition metal dichalcogenide and black phosphorus transistors for low power robust SRAM design. DAC Joydeep Rakshit, Runlai Wan, Kai Tak Lam, Jing Guo, Kartik Mohanram
2015	J	`jnl`	Two-Port PCM Architecture for Network Processing. IEEE Trans. Very Large Scale Integr. Syst. Jiayin Li, David B. Dgien, Nathan Altay Hunter, Yirong Zhao, Kartik Mohanram
2014	—	`conf`	Compression architecture for bit-write reduction in non-volatile memory technologies. NANOARCH David B. Dgien, Poovaiah M. Palangappa, Nathan Altay Hunter, Jiayin Li, Kartik Mohanram
2014	J	`jnl`	Time-Borrowing Circuit Designs and Hardware Prototyping for Timing Error Resilience. IEEE Trans. Computers Mihir R. Choudhury, Vikas Chandra, Robert C. Aitken, Kartik Mohanram
2014	A	`conf`	Write-once-memory-code phase change memory. DATE Jiayin Li, Kartik Mohanram
2013	J	`jnl`	Low Cost Concurrent Error Masking Using Approximate Logic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mihir R. Choudhury, Kartik Mohanram
2013	A	`conf`	Mempack: an order of magnitude reduction in the cost, risk, and time for memory compiler certification. DATE Kartik Mohanram, Matthew Wartell, Sundar Iyer
2013	—	`conf`	Multi-port FinFET SRAM design. ACM Great Lakes Symposium on VLSI Yirong Zhao, Jiayin Li, Kartik Mohanram
2012	—	`conf`	Ambipolar circuits for analog, mixed-signal, and radio-frequency applications. NANOARCH Kartik Mohanram, Xuebei Yang, Masoud Rostami, Guanxiong Liu, Alexander A. Balandin
2012	A	`conf`	High performance reliable variable latency carry select addition. DATE Kai Du, Peter J. Varman, Kartik Mohanram
2011	J	`jnl`	An Efficient Gate Library for Ambipolar CNTFET Logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. M. Haykel Ben Jamaa, Kartik Mohanram, Giovanni De Micheli
2011	J	`jnl`	Dual-V IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Masoud Rostami, Kartik Mohanram
2011	A	`conf`	Reliability-driven don't care assignment for logic synthesis. DATE Andrew Zukoski, Mihir R. Choudhury, Kartik Mohanram
2011	A	`conf`	Robust 6T Si tunneling transistor SRAM design. DATE Xuebei Yang, Kartik Mohanram
2011	C	`conf`	Static window addition: A new paradigm for the design of variable latency adders. ICCD Kai Du, Peter J. Varman, Kartik Mohanram
2011	A	`conf`	Unequal-error-protection codes in SRAMs for mobile multimedia applications. ICCAD Xuebei Yang, Kartik Mohanram
2011	A*	`conf`	Universal logic modules based on double-gate carbon nanotube transistors. DAC Andrew Zukoski, Xuebei Yang, Kartik Mohanram
2010	A	`conf`	Analytical model for TDDB-based performance degradation in combinational logic. DATE Mihir R. Choudhury, Vikas Chandra, Kartik Mohanram, Robert C. Aitken
2010	A	`conf`	Bi-decomposition of large Boolean functions using blocking edge graphs. ICCAD Mihir R. Choudhury, Kartik Mohanram
2010	—	`conf`	Dominant critical gate identification for power and yield optimization in logic circuits. ACM Great Lakes Symposium on VLSI Mihir R. Choudhury, Masoud Rostami, Kartik Mohanram
2010	—	`conf`	Graphene tunneling FET and its applications in low-power circuit design. ACM Great Lakes Symposium on VLSI Xuebei Yang, Jyotsna Chauhan, Jing Guo, Kartik Mohanram
2010	—	`conf`	Novel dual- ASP-DAC Masoud Rostami, Kartik Mohanram
2010	A	`conf`	Power consumption of logic circuits in ambipolar carbon nanotube technology. DATE M. Haykel Ben Jamaa, Kartik Mohanram, Giovanni De Micheli
2010	—	`conf`	Semi-analytical model for schottky-barrier carbon nanotube and graphene nanoribbon transistors. ACM Great Lakes Symposium on VLSI Xuebei Yang, Gianluca Fiori, Giuseppe Iannaccone, Kartik Mohanram
2010	A	`conf`	TIMBER: Time borrowing and error relaying for online timing error resilience. DATE Mihir R. Choudhury, Vikas Chandra, Kartik Mohanram, Robert C. Aitken
2009	A	`conf`	Masking timing errors on speed-paths in logic circuits. DATE Mihir R. Choudhury, Kartik Mohanram
2009	J	`jnl`	Modeling stochasticity and robustness in gene regulatory networks. Bioinform. Abhishek Garg, Kartik Mohanram, Alessandro Di Cara, Giovanni De Micheli, Ioannis Xenarios
2009	A	`conf`	Novel library of logic gates with ambipolar CNTFETs: Opportunities for multi-level logic synthesis. DATE M. Haykel Ben Jamaa, Kartik Mohanram, Giovanni De Micheli
2009	J	`jnl`	Reliability Analysis of Logic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mihir R. Choudhury, Kartik Mohanram
2009	J	`jnl`	Soft Error Rate Reduction Using Circuit Optimization and Transient Filter Insertion. J. Electron. Test. Mihir R. Choudhury, Quming Zhou, Kartik Mohanram
2009	A*	`conf`	Timing-driven optimization using lookahead logic circuits. DAC Mihir R. Choudhury, Kartik Mohanram
2008	A	`conf`	Approximate logic circuits for low overhead, non-intrusive concurrent error detection. DATE Mihir R. Choudhury, Kartik Mohanram
2008	—	`conf`	Error Detection and Tolerance for Scaled Electronic Technologies. DFT Kartik Mohanram
2008	A	`conf`	Graphene nanoribbon FETs: technology exploration and CAD. ICCAD Kartik Mohanram, Jing Guo
2008	A*	`conf`	Technology exploration for graphene nanoribbon FETs. DAC Mihir R. Choudhury, Youngki Yoon, Jing Guo, Kartik Mohanram
2008	B	`conf`	Tunable Transient Filters for Soft Error Rate Reduction in Combinational Circuits. ETS Quming Zhou, Mihir R. Choudhury, Kartik Mohanram
2007	A	`conf`	Accurate and scalable reliability analysis of logic circuits. DATE Mihir R. Choudhury, Kartik Mohanram
2007	A	`conf`	Interactive presentation: Single-ended coding techniques for off-chip interconnects to commodity memory. DATE Mihir R. Choudhury, Kyle Ringgenberg, Scott Rixner, Kartik Mohanram
2007	A	`conf`	Parallel domain decomposition for simulation of large-scale power grids. ICCAD Kai Sun, Quming Zhou, Kartik Mohanram, Danny C. Sorensen
2007	—	`conf`	Parameter-Variation-Aware Analysis for Noise Robustness. ISQED Mosin Mondal, Kartik Mohanram, Yehia Massoud
2007	A	`conf`	Power signal processing: a new perspective for power analysis and optimization. ISLPED Quming Zhou, Lin Zhong, Kartik Mohanram
2006	—	`conf`	Dependable != unaffordable. ASID Alan L. Cox, Kartik Mohanram, Scott Rixner
2006	Misc	`conf`	Design Optimization for Robustness to Single Event Upsets. VTS Quming Zhou, Mihir R. Choudhury, Kartik Mohanram
2006	A	`conf`	Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques. ICCAD Mihir R. Choudhury, Quming Zhou, Kartik Mohanram
2006	A*	`conf`	Elmore model for energy estimation in RC trees. DAC Quming Zhou, Kartik Mohanram
2006	J	`jnl`	Gate sizing to radiation harden combinational logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Quming Zhou, Kartik Mohanram
2006	A	`conf`	Large power grid analysis using domain decomposition. DATE Quming Zhou, Kai Sun, Kartik Mohanram, Danny C. Sorensen
2005	Misc	`conf`	Closed-Form Simulation and Robustness Models for SEU-Tolerant Design. VTS Kartik Mohanram
2005	A	`conf`	Simulation of transients caused by single-event upsets in combinational logic. ITC Kartik Mohanram
2005	A*	`conf`	Structure preserving reduction of frequency-dependent interconnect. DAC Quming Zhou, Kartik Mohanram, Athanasios C. Antoulas
2004	A	`conf`	Analysis of delay caused by bridging faults in RLC interconnects. ITC Quming Zhou, Kartik Mohanram
2004	—	`conf`	Context-Independent Codes for Off-Chip Interconnects. PACS Kartik Mohanram, Scott Rixner
2004	A	`conf`	Cost-effective radiation hardening technique for combinational logic. ICCAD Quming Zhou, Kartik Mohanram
2004	J	`jnl`	Lowering power consumption in concurrent checkers via input ordering. IEEE Trans. Very Large Scale Integr. Syst. Kartik Mohanram, Nur A. Touba
2003	A	`conf`	Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits. ITC Kartik Mohanram, Nur A. Touba
2003	Misc	`conf`	Eliminating Non-Determinism During Test of High-Speed Source Synchronous Differential Buses. VTS Kartik Mohanram, Nur A. Touba
2003	—	`conf`	Partial Error Masking to Reduce Soft Error Failure Rate in Logic Circuits. DFT Kartik Mohanram, Nur A. Touba
2003	C	`conf`	Synthesis of Low-Cost Parity-Based Partially Self-Checking Circuits. IOLTS Kartik Mohanram, Egor S. Sogomonyan, Michael Gössel, Nur A. Touba
2002	—	`conf`	A methodology for automated insertion of concurrent error detection hardware in synthesizable Verilog RTL. ISCAS (1) Kartik Mohanram, C. V. Krishna, Nur A. Touba
2002	—	`conf`	Input Ordering in Concurrent Checkers to Reduce Power Consumption. DFT Kartik Mohanram, Nur A. Touba
1999	—	`conf`	An Embedded Core DFT Scheme to Obtain Highly Compressed Test Sets. Asian Test Symposium Abhijit Jas, Kartik Mohanram, Nur A. Touba