Karthikeyan Reddy

12 papers C 1Journal 6Unranked 5
YearRankTypeTitle / Venue / Authors
2018 J jnl
A 50 MHz BW 76.1 dB DR Two-Stage Continuous-Time Delta-Sigma Modulator With VCO Quantizer Nonlinearity Cancellation.
IEEE J. Solid State Circuits
Siladitya Dey, Karthikeyan Reddy, Kartikeya Mayaram, Terri S. Fiez
2017 — conf
A 50 MHz BW 73.5 dB SNDR two-stage continuous-time ΔΣ modulator with VCO quantizer nonlinearity cancellation.
CICC
Siladitya Dey, Karthikeyan Reddy, Kartikeya Mayaram, Terri S. Fiez
2015 — conf
A 54mW 1.2GS/s 71.5dB SNDR 50MHz BW VCO-based CT ΔΣ ADC using dual phase/frequency feedback in 65nm CMOS.
VLSIC
Karthikeyan Reddy, Siladitya Dey, Sachin Rao, Brian Young, Praveen Prabha, Pavan Kumar Hanumolu
2015 J jnl
A Highly Digital VCO-Based ADC Architecture for Current Sensing Applications.
IEEE J. Solid State Circuits
Praveen Prabha, Seong Joong Kim, Karthikeyan Reddy, Sachin Rao, Nathanael Griesert, Arun Rao, Greg Winter, Pavan Kumar Hanumolu
2014 J jnl
A Deterministic Digital Background Calibration Technique for VCO-Based ADCs.
IEEE J. Solid State Circuits
Sachin Rao, Karthikeyan Reddy, Brian Young, Pavan Kumar Hanumolu
2014 — conf
A VCO-based current-to-digital converter for sensor applications.
CICC
Praveen Prabha, Seong Joong Kim, Karthikeyan Reddy, Sachin Rao, Nathanael Griesert, Arun Rao, Greg Winter, Pavan Kumar Hanumolu
2014 J jnl
An 8 Gb/s-64 Mb/s, 2.3-4.2 mW/Gb/s Burst-Mode Transmitter in 90 nm CMOS.
IEEE J. Solid State Circuits
Mrunmay Talegaonkar, Amr Elshazly, Karthikeyan Reddy, Praveen Prabha, Tejasvi Anand, Pavan Kumar Hanumolu
2012 J jnl
A 16-mW 78-dB SNDR 10-MHz BW CT Delta Sigma ADC Using Residue-Cancelling VCO-Based Quantizer.
IEEE J. Solid State Circuits
Karthikeyan Reddy, Sachin Rao, Rajesh Inti, Brian Young, Amr Elshazly, Mrunmay Talegaonkar, Pavan Kumar Hanumolu
2012 — conf
A 16mW 78dB-SNDR 10MHz-BW CT-ΔΣ ADC using residue-cancelling VCO-based quantizer.
ISSCC
Karthikeyan Reddy, Sachin Rao, Rajesh Inti, Brian Young, Amr Elshazly, Mrunmay Talegaonkar, Pavan Kumar Hanumolu
2008 — conf
A 20.7mW continuous-time ΔΣ modulator with 15MHz bandwidth and 70 dB dynamic range.
ESSCIRC
Karthikeyan Reddy, Shanthi Pavan
2007 J jnl
Fundamental Limitations of Continuous-Time Delta-Sigma Modulators Due to Clock Jitter.
IEEE Trans. Circuits Syst. I Regul. Pap.
Karthikeyan Reddy, Shanthi Pavan
2006 C conf
Fundamental limitations of continuous-time delta-sigma modulators due to clock jitter.
ISCAS
Karthikeyan Reddy, Shanthi Pavan