Karthikeyan Natarajan

11 papers A* 1A 2B 1Misc 5Journal 1Unranked 1
YearRankTypeTitle / Venue / Authors
2023 J jnl
Novel Technique for Manufacturing, System-Level, and In-System Testing of Large SoC Using Functional Protocol-Based High-Speed I/O.
IEEE Des. Test
Amit Pandey, Brendan Tully, Abhijeet Samudra, Ajay Nagarandal, Karthikeyan Natarajan, Rahul Singhal
2022 A conf
Comprehensive Power-Aware ATPG Methodology for Complex Low-Power Designs.
ITC
Khader S. Abdel-Hafez, Michael Dsouza, Likith Kumar Manchukonda, Elddie Tsai, Karthikeyan Natarajan, Ting-Pu Tai, Wenhao Hsueh, Smith Lai
2022 A conf
High Speed IO Access for Test forms the foundation for Silicon Lifecycle Management.
ITC
Amit Pandey, Brendan Tully, Karthikeyan Natarajan
2022 Misc conf
Novel Technique for Manufacturing & In-system Testing of Large Scale SoC using Functional Protocol Based High-Speed I/O.
VTS
Amit Pandey, Brendan Tully, Abhijeet Samudra, Ajay Nagarandal, Karthikeyan Natarajan, Rahul Singhal
2022 B conf
Power Aware Test.
ETS
Likith Kumar Manchukonda, Karthikeyan Natarajan, Manish Arora
2019 A* conf
High Performance Graph Convolutional Networks with Applications in Testability Analysis.
DAC
Yuzhe Ma, Haoxing Ren, Brucek Khailany, Harbinder Sikka, Lijuan Luo, Karthikeyan Natarajan, Bei Yu
2018 Misc conf
Lossless Parallel Implementation of a Turbo Decoder on GPU.
HiPC
Karthikeyan Natarajan, Nitin Chandrachoodan
2016 Misc conf
A programmable method for low-power scan shift in SoC integrated circuits.
VTS
Ran Wang, Bonita Bhaskaran, Karthikeyan Natarajan, Ayub Abdollahian, Kaushik Narayanun, Krishnendu Chakrabarty, Amit Sanghani
2016 Misc conf
Dynamic docking architecture for concurrent testing and peak power reduction.
VTS
Milind Sonawane, Pavan Kumar Datla Jagannadha, Sailendra Chadalavada, Shantanu Sarangi, Mahmut Yilmaz, Amit Sanghani, Karthikeyan Natarajan, Jonathon E. Colburn, Anubhav Sinha
2015 — conf
Non-uniform DFT implementation for channel simulations in GPU.
NCC
Karthikeyan Natarajan, Nitin Chandrachoodan
2011 Misc conf
Design and implementation of a time-division multiplexing scan architecture using serializer and deserializer in GPU chips.
VTS
Amit Sanghani, Bo Yang, Karthikeyan Natarajan, Chunsheng Liu