Karthikeyan Lingasubramanian

16 papers C 3Misc 3Journal 6Unranked 4
YearRankTypeTitle / Venue / Authors
2020 J jnl
A Viterbi decoder and its hardware Trojan models: an FPGA-based implementation study.
PeerJ Comput. Sci.
Varsha Kakkara, Karthi Balasubramanian, B. Yamuna, Deepak Mishra, Karthikeyan Lingasubramanian, Senthil Murugan
2019 Misc conf
Effect of sign-bit-flipping trojan on turbo coded communication systems.
ICDCN
Karthi Balasubramanian, B. Yamuna, Salija P, Karthikeyan Lingasubramanian, Deepak Mishra
2018 C conf
Effect of hardware Trojans on the performance of a coded communication system.
ICCE
A. R. Aravind, S. R. Kesavaraman, Karthi Balasubramanian, B. Yamuna, Karthikeyan Lingasubramanian
2018 C conf
Study of hardware trojans based security vulnerabilities in cyber physical systems.
ICCE
Karthikeyan Lingasubramanian, Ranveer Kumar, Nagendra Babu Gunti, Thomas H. Morris
2017 J jnl
Effective usage of redundancy to aid neutralization of hardware Trojans in Integrated Circuits.
Integr.
Gunti Nagendra Babu, Karthikeyan Lingasubramanian
2017 — conf
Fault Sensitive Neutralization of Hardware Trojans Using Multi-level Triple Modular Redundancy Scheme.
iNIS
Nagendra Babu Gunti, Karthikeyan Lingasubramanian
2017 — conf
Neutralization of the Effect of Hardware Trojan in SCADA System Using Selectively Placed TMR.
iNIS
Nagendra Babu Gunti, Karthikeyan Lingasubramanian
2014 C conf
Realizing a security aware triple modular redundancy scheme for robust integrated circuits.
VLSI-SoC
Gunti Nagendra Babu, Aman Khatri, Karthikeyan Lingasubramanian
2011 J jnl
Maximum error modeling for fault-tolerant computation using maximum a posteriori (MAP) hypothesis.
Microelectron. Reliab.
Karthikeyan Lingasubramanian, Syed M. Alam, Sanjukta Bhanja
2011 — conf
Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-Gating.
PATMOS
Karthikeyan Lingasubramanian, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino
2009 Misc conf
An Error Model to Study the Behavior of Transient Errors in Sequential Circuits.
VLSI Design
Karthikeyan Lingasubramanian, Sanjukta Bhanja
2009 J jnl
Probabilistic Error Modeling for Nano-Domain Logic Circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Thara Rejimon, Karthikeyan Lingasubramanian, Sanjukta Bhanja
2009 J jnl
Study of Circuit-Specific Error Bounds for Fault-Tolerant Computation using Maximum a posteriori (MAP) Hypothesis
CoRR
Karthikeyan Lingasubramanian, Syed M. Alam, Sanjukta Bhanja
2007 — conf
Probabilistic maximum error modeling for unreliable logic circuits.
ACM Great Lakes Symposium on VLSI
Karthikeyan Lingasubramanian, Sanjukta Bhanja
2006 J jnl
A stimulus-free graphical probabilistic switching model for sequential circuits using dynamic bayesian networks.
ACM Trans. Design Autom. Electr. Syst.
Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan
2005 Misc conf
Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks.
VLSI Design
Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan