Karthik Duraisami

11 papers A 2C 2Journal 4Unranked 3
YearRankTypeTitle / Venue / Authors
2010 J jnl
Thermal-Aware Clock Tree Design to Increase Timing Reliability of Embedded SoCs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ashutosh Chakraborty, Karthik Duraisami, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino
2009 — conf
Using soft-edge flip-flops to compensate NBTI-induced delay degradation.
ACM Great Lakes Symposium on VLSI
Karthik Duraisami, Enrico Macii, Massimo Poncino
2008 J jnl
Dynamic Thermal Clock Skew Compensation Using Tunable Delay Buffers.
IEEE Trans. Very Large Scale Integr. Syst.
Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
2008 — conf
Energy efficiency bounds of pulse-encoded buses.
ACM Great Lakes Symposium on VLSI
Karthik Duraisami, Enrico Macii, Massimo Poncino
2008 J jnl
Implementation of a thermal management unit for canceling temperature-dependent clock skew variations.
Integr.
Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino
2008 J jnl
Thermal-Aware Design Techniques for Nanometer CMOS Circuits.
J. Low Power Electron.
Andrea Calimera, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, R. Iris Bahar, Alberto Macii, Enrico Macii, Massimo Poncino
2007 C conf
Design Exploration of a Thermal Management Unit for Dynamic Control of Temperature-Induced Clock Skew.
ISCAS
Karthik Duraisami, Prassanna Sithambaram, Ashoka Visweswara Sathanur, Alberto Macii, Enrico Macii, Massimo Poncino
2006 — conf
Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective.
PATMOS
Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino
2006 A conf
Dynamic thermal clock skew compensation using tunable delay buffers.
ISLPED
Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
2006 C conf
Implications of ultra low-voltage devices on design techniques for controlling leakage in NanoCMOS circuits.
ISCAS
Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino
2006 A conf
Thermal resilient bounded-skew clock tree optimization methodology.
DATE
Ashutosh Chakraborty, Prassanna Sithambaram, Karthik Duraisami, Alberto Macii, Enrico Macii, Massimo Poncino