Karem A. Sakallah

158 papers A* 23A 42B 13C 9Misc 1Journal 40Unranked 28

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	QSM-Cutoff: Systematic Derivation of Quantified Cutoff Formulas for Distributed Protocols. CAV (3) Yun-Rong Luo, Aman Goel, Karem A. Sakallah
2024	—	`conf`	SAT-Based Quantified Symmetric Minimization of the Reachable States of Distributed Protocols: An Update. ISoLA (3) Yun-Rong Luo, Aman Goel, Karem A. Sakallah
2023	J	`jnl`	Regularity and quantification: a new approach to verify distributed protocols. Innov. Syst. Softw. Eng. Aman Goel, Karem A. Sakallah
2023	B	`conf`	SAT-Based Quantified Symmetric Minimization of the Reachable States of Distributed Protocols. FMCAD Katalin Fazekas, Aman Goel, Karem A. Sakallah
2023	C	`conf`	Towards an Automatic Proof of the Bakery Algorithm. FORTE Aman Goel, Stephan Merz, Karem A. Sakallah
2021	—	`conf`	Invited Talk: AVR: Word-Level Verification by Equality Abstraction of Data State. SMT Karem A. Sakallah
2021	—	`conf`	On Symmetry and Quantification: A New Approach to Verify Distributed Protocols. NFM Aman Goel, Karem A. Sakallah
2021	J	`jnl`	On Symmetry and Quantification: A New Approach to Verify Distributed Protocols. CoRR Aman Goel, Karem A. Sakallah
2021	—	`ch.`	Symmetry and Satisfiability. Handbook of Satisfiability Karem A. Sakallah
2021	B	`conf`	Towards an Automatic Proof of Lamport's Paxos. FMCAD Aman Goel, Karem A. Sakallah
2021	J	`jnl`	Towards an Automatic Proof of Lamport's Paxos. CoRR Aman Goel, Karem A. Sakallah
2020	—	`conf`	AVR: Abstractly Verifying Reachability. TACAS (1) Aman Goel, Karem A. Sakallah
2020	B	`conf`	EUFicient Reachability in Software with Arrays. FMCAD Denis Bueno, Arlen Cox, Karem A. Sakallah
2019	A	`conf`	Empirical Evaluation of IC3-Based Model Checking Techniques on Verilog RTL Designs. DATE Aman Goel, Karem A. Sakallah
2019	A*	`conf`	I4: incremental inference of inductive invariants for verification of distributed protocols. SOSP Haojun Ma, Aman Goel, Jean-Baptiste Jeannin, Manos Kapritsos, Baris Kasikci, Karem A. Sakallah
2019	—	`conf`	Model Checking of Verilog RTL Using IC3 with Syntax-Guided Abstraction. NFM Aman Goel, Karem A. Sakallah
2019	A	`conf`	Towards Automatic Inference of Inductive Invariants. HotOS Haojun Ma, Aman Goel, Jean-Baptiste Jeannin, Manos Kapritsos, Baris Kasikci, Karem A. Sakallah
2019	B	`conf`	euforia: Complete Software Model Checking with Uninterpreted Functions. VMCAI Denis Bueno, Karem A. Sakallah
2014	A*	`conf`	Unbounded Scalable Verification Based on Approximate Property-Directed Reachability and Datapath Abstraction. CAV Suho Lee, Karem A. Sakallah
2013	B	`conf`	Conflict Analysis and Branching Heuristics in the Search for Graph Automorphisms. ICTAI Paolo Codenotti, Hadi Katebi, Karem A. Sakallah, Igor L. Markov
2013	A	`conf`	Detecting Traditional Packers, Decisively. RAID Denis Bueno, Kevin J. Compton, Karem A. Sakallah, Michael D. Bailey
2013	A	`conf`	Generalized Boolean symmetries through nested partition refinement. ICCAD Hadi Katebi, Karem A. Sakallah, Igor L. Markov
2012	J	`jnl`	Conflict Anticipation in the Search for Graph Automorphisms CoRR Hadi Katebi, Karem A. Sakallah, Igor L. Markov
2012	B	`conf`	Conflict Anticipation in the Search for Graph Automorphisms. LPAR Hadi Katebi, Karem A. Sakallah, Igor L. Markov
2012	J	`jnl`	Graph Symmetry Detection and Canonical Labeling: Differences and Synergies CoRR Hadi Katebi, Karem A. Sakallah, Igor L. Markov
2012	—	`conf`	Graph Symmetry Detection and Canonical Labeling: Differences and Synergies. Turing-100 Hadi Katebi, Karem A. Sakallah, Igor L. Markov
2011	J	`jnl`	Anatomy and Empirical Evaluation of Modern SAT Solvers. Bull. EATCS Karem A. Sakallah, João Marques-Silva
2011	J	`jnl`	Breaking Instance-Independent Symmetries In Exact Graph Coloring CoRR Fadi A. Aloul, Igor L. Markov, Arathi Ramani, Karem A. Sakallah
2011	A	`conf`	Distilling critical attack graph surface iteratively through minimum-cost SAT solving. ACSAC Heqing Huang, Su Zhang, Xinming Ou, Atul Prakash, Karem A. Sakallah
2011	A	`conf`	Empirical Study of the Anatomy of Modern Sat Solvers. SAT Hadi Katebi, Karem A. Sakallah, João P. Marques Silva
2011	—	`conf`	Generating Data Race Witnesses by an SMT-Based Analysis. NASA Formal Methods Mahmoud Said, Chao Wang, Zijiang Yang, Karem A. Sakallah
2011	A	`ed.`	Theory and Applications of Satisfiability Testing - SAT 2011 - 14th International Conference, SAT 2011, Ann Arbor, MI, USA, June 19-22, 2011. Proceedings SAT Karem A. Sakallah, Laurent Simon
2010	A	`conf`	Incorporating user control in automated interactive scheduling systems. Conference on Designing Interactive Systems Jina Huh, Martha E. Pollack, Hadi Katebi, Karem A. Sakallah, Ned Kirsch
2010	A	`conf`	Symmetry and Satisfiability: An Update. SAT Hadi Katebi, Karem A. Sakallah, Igor L. Markov
2010	C	`conf`	Trace-Driven Verification of Multithreaded Programs. ICFEM Zijiang Yang, Karem A. Sakallah
2009	J	`jnl`	A branch and bound algorithm for extracting smallest minimal unsatisfiable subformulas. Constraints An Int. J. Mark H. Liffiton, Maher N. Mneimneh, Inês Lynce, Zaher S. Andraus, João Marques-Silva, Karem A. Sakallah
2009	B	`conf`	Dynamic Path Reduction for Software Model Checking. IFM Zijiang Yang, Bashar Al-Rawi, Karem A. Sakallah, Xiaowan Huang, Scott A. Smolka, Radu Grosu
2009	J	`jnl`	Dynamic symmetry-breaking for Boolean satisfiability. Ann. Math. Artif. Intell. Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah
2009	A	`conf`	Generalizing Core-Guided Max-SAT. SAT Mark H. Liffiton, Karem A. Sakallah
2009	—	`ch.`	Symmetry and Satisfiability. Handbook of Satisfiability Karem A. Sakallah
2008	J	`jnl`	Algorithms for Computing Minimal Unsatisfiable Subsets of Constraints. J. Autom. Reason. Mark H. Liffiton, Karem A. Sakallah
2008	A*	`conf`	Faster symmetry discovery using sparsity of symmetries. DAC Paul T. Darga, Karem A. Sakallah, Igor L. Markov
2008	B	`conf`	Reveal: A Formal Verification Tool for Verilog Designs. LPAR Zaher S. Andraus, Mark H. Liffiton, Karem A. Sakallah
2008	A	`conf`	Searching for Autarkies to Trim Unsatisfiable Clause Sets. SAT Mark H. Liffiton, Karem A. Sakallah
2007	B	`conf`	Improved Design Debugging Using Maximum Satisfiability. FMCAD Sean Safarpour, Hratch Mangassarian, Andreas G. Veneris, Mark H. Liffiton, Karem A. Sakallah
2007	J	`jnl`	Report on the SAT 2007 Conference on Theory and Applications of Satisfiability Testing. AI Mag. João Marques-Silva, Karem A. Sakallah, Inês Lynce
2007	J	`jnl`	Solution and Optimization of Systems of Pseudo-Boolean Constraints. IEEE Trans. Computers Fadi A. Aloul, Arathi Ramani, Karem A. Sakallah, Igor L. Markov
2007	J	`jnl`	Symmetry breaking for pseudo-Boolean formulas. ACM J. Exp. Algorithmics Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah
2007	A	`ed.`	Theory and Applications of Satisfiability Testing - SAT 2007, 10th International Conference, Lisbon, Portugal, May 28-31, 2007, Proceedings SAT João Marques-Silva, Karem A. Sakallah
2006	A	`conf`	A Progressive Simplifier for Satisfiability Modulo Theories. SAT Hossein M. Sheini, Karem A. Sakallah
2006	B	`conf`	Ario: A Linear Integer Arithmetic Logic Solver. FMCAD Hossein M. Sheini, Karem A. Sakallah
2006	J	`jnl`	Breaking Instance-Independent Symmetries In Exact Graph Coloring. J. Artif. Intell. Res. Arathi Ramani, Igor L. Markov, Karem A. Sakallah, Fadi A. Aloul
2006	J	`jnl`	Efficient Symmetry Breaking for Boolean Satisfiability. IEEE Trans. Computers Fadi A. Aloul, Karem A. Sakallah, Igor L. Markov
2006	A	`conf`	From Propositional Satisfiability to Satisfiability Modulo Theories. SAT Hossein M. Sheini, Karem A. Sakallah
2006	J	`jnl`	Pueblo: A Hybrid Pseudo-Boolean SAT Solver. J. Satisf. Boolean Model. Comput. Hossein M. Sheini, Karem A. Sakallah
2006	—	`conf`	Refinement strategies for verification methods based on datapath abstraction. ASP-DAC Zaher S. Andraus, Mark H. Liffiton, Karem A. Sakallah
2006	A	`conf`	SMT( ICCAD Hossein M. Sheini, Karem A. Sakallah
2005	A	`conf`	A Branch-and-Bound Algorithm for Extracting Smallest Minimal Unsatisfiable Formulas. SAT Maher N. Mneimneh, Inês Lynce, Zaher S. Andraus, João Marques-Silva, Karem A. Sakallah
2005	B	`conf`	A SAT-Based Decision Procedure for Mixed Logical/Integer Linear Problems. CPAIOR Hossein M. Sheini, Karem A. Sakallah
2005	A	`conf`	A Scalable Method for Solving Satisfiability of Integer Linear Arithmetic Logic. SAT Hossein M. Sheini, Karem A. Sakallah
2005	—	`conf`	Dynamic symmetry-breaking for improved Boolean optimization. ASP-DAC Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah
2005	A*	`conf`	Identifying Conflicts in Overconstrained Temporal Problems. IJCAI Mark H. Liffiton, Michael D. Moffitt, Martha E. Pollack, Karem A. Sakallah
2005	A	`conf`	On Finding All Minimally Unsatisfiable Subformulas. SAT Mark H. Liffiton, Karem A. Sakallah
2005	A	`conf`	On Solving Soft Temporal Constraints Using SAT Techniques. CP Hossein M. Sheini, Bart Peintner, Karem A. Sakallah, Martha E. Pollack
2005	J	`jnl`	Principles of Sequential-Equivalence Verification. IEEE Des. Test Comput. Maher N. Mneimneh, Karem A. Sakallah
2005	A	`conf`	Pueblo: A Modern Pseudo-Boolean SAT Solver. DATE Hossein M. Sheini, Karem A. Sakallah
2004	J	`jnl`	A Comparative Study of Two Boolean Formulations of FPGA Detailed Routing Constraints. IEEE Trans. Computers Gi-Joon Nam, Fadi A. Aloul, Karem A. Sakallah, Rob A. Rutenbar
2004	A*	`conf`	AMUSE: a minimally-unsatisfiable subformula extractor. DAC Yoonna Oh, Maher N. Mneimneh, Zaher S. Andraus, Karem A. Sakallah, Igor L. Markov
2004	A*	`conf`	Automatic abstraction and verification of verilog models. DAC Zaher S. Andraus, Karem A. Sakallah
2004	A	`conf`	Breaking Instance-Independent Symmetries in Exact Graph Coloring. DATE Arathi Ramani, Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah
2004	A*	`conf`	Exploiting structure in symmetry detection for CNF. DAC Paul T. Darga, Mark H. Liffiton, Karem A. Sakallah, Igor L. Markov
2004	J	`jnl`	MINCE: A Static Global Variable-Ordering Heuristic for SAT Search and BDD Manipulation. J. Univers. Comput. Sci. Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah
2004	—	`conf`	Preserving synchronizing sequences of sequential circuits after retiming. ASP-DAC Maher N. Mneimneh, Karem A. Sakallah, John Moondanos
2004	—	`conf`	ShatterPB: symmetry-breaking for pseudo-Boolean formulas. ASP-DAC Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah
2003	A	`conf`	Computing Vertex Eccentricity in Exponentially Large Graphs: QBF Formulation and Solution. SAT Maher N. Mneimneh, Karem A. Sakallah
2003	A*	`conf`	Efficient Symmetry Breaking for Boolean Satisfiability. IJCAI Fadi A. Aloul, Karem A. Sakallah, Igor L. Markov
2003	—	`conf`	FORCE: a fast and easy-to-implement variable-ordering heuristic. ACM Great Lakes Symposium on VLSI Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah
2003	—	`conf`	SAT-based sequential depth computation. ASP-DAC Maher N. Mneimneh, Karem A. Sakallah
2003	J	`jnl`	Satometer: how much have we searched? IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Fadi A. Aloul, Brian D. Sierawski, Karem A. Sakallah
2003	A*	`conf`	Shatter: efficient symmetry-breaking for boolean satisfiability. DAC Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah
2003	J	`jnl`	Solving difficult instances of Boolean satisfiability in the presence of symmetry. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah
2003	J	`jnl`	Transistor placement for noncomplementary digital VLSI cell synthesis. ACM Trans. Design Autom. Electr. Syst. Michael A. Riepe, Karem A. Sakallah
2003	J	`jnl`	sub-SAT: a formulation for relaxed Boolean satisfiability with applications in routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hui Xu, Rob A. Rutenbar, Karem A. Sakallah
2002	J	`jnl`	A new FPGA detailed routing approach via search-based Booleansatisfiability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar
2002	—	`conf`	Efficient Gate and Input Ordering for Circuit-to-BDD Conversion. IWLS Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah
2002	A	`conf`	Generic ILP versus specialized 0-1 ILP: an update. ICCAD Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah
2002	B	`conf`	Hybrid Routing for FPGAs by Integrating Boolean Satisfiability with Geometric Search. FPL Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar
2002	C	`conf`	Improving the Efficiency of Circuit-to-BDD Conversion by Gate and Input Ordering. ICCD Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah
2002	—	`conf`	Majority-Based Decomposition of Carry Logic in Binary Adders. IWLS Leyla Nazhandali, Karem A. Sakallah
2002	A	`conf`	Resynthesis of multi-level circuits under tight constraints using symbolic optimization. ICCAD Victor N. Kravets, Karem A. Sakallah
2002	—	`conf`	Robust SAT-Based Search Algorithm for Leakage Power Reduction. PATMOS Fadi A. Aloul, Soha Hassoun, Karem A. Sakallah, David T. Blaauw
2002	J	`jnl`	Satisfiability models and algorithms for circuit delay computation. ACM Trans. Design Autom. Electr. Syst. Luís Guerra e Silva, João Marques-Silva, Luís Miguel Silveira, Karem A. Sakallah
2002	A*	`conf`	Satometer: how much have we searched? DAC Fadi A. Aloul, Brian D. Sierawski, Karem A. Sakallah
2002	A	`conf`	Search-Based SAT Using Zero-Suppressed BDDs. DATE Fadi A. Aloul, Maher N. Mneimneh, Karem A. Sakallah
2002	A*	`conf`	Solving difficult SAT instances in the presence of symmetry. DAC Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah
2002	—	`conf`	ZBDD-Based Backtrack Search SAT Solver. IWLS Fadi A. Aloul, Maher N. Mneimneh, Karem A. Sakallah
2002	—	`conf`	sub-SAT: a formulation for relaxed boolean satisfiability with applications in routing. ISPD Hui Xu, Rob A. Rutenbar, Karem A. Sakallah
2001	A	`conf`	A boolean satisfiability-based incremental rerouting approach with application to FPGAs. DATE Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar
2001	—	`conf`	A comparative study of two Boolean formulations of FPGA detailed routing constraints. ISPD Gi-Joon Nam, Fadi A. Aloul, Karem A. Sakallah, Rob A. Rutenbar
2001	A*	`conf`	An Advanced Timing Characterization Method Using Mode Dependency. DAC Hakan Yalcin, Robert Palermo, Mohammad Mortazavi, Cyrus Bamji, Karem A. Sakallah, John P. Hayes
2001	J	`jnl`	Fast and accurate timing characterization using functionalinformation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hakan Yalcin, Mohammad Mortazavi, Robert Palermo, Cyrus Bamji, Karem A. Sakallah, John P. Hayes
2001	A	`conf`	Faster SAT and Smaller BDDs via Common Function Structure. ICCAD Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah
2001	A*	`conf`	SATIRE: A New Incremental Satisfiability Engine. DAC Jesse Whittemore, Joonyoung Kim, Karem A. Sakallah
2001	A*	`conf`	Scalable Hybrid Verification of Complex Microprocessors. DAC Maher N. Mneimneh, Fadi A. Aloul, Christopher T. Weaver, Saugata Chatterjee, Karem A. Sakallah, Todd M. Austin
2000	A	`conf`	An Experimental Study of Satisfiability Search Heuristics. DATE Karem A. Sakallah, Fadi A. Aloul, João P. Marques Silva
2000	A*	`conf`	Boolean satisfiability in electronic design automation. DAC João P. Marques Silva, Karem A. Sakallah
2000	A	`conf`	Constructive Library-Aware Synthesis Using Symmetries. DATE Victor N. Kravets, Karem A. Sakallah
2000	A	`conf`	Generalized Symmetries in Boolean Functions. ICCAD Victor N. Kravets, Karem A. Sakallah
2000	A*	`conf`	Invited Tutorial: Boolean Satisfiability Algorithms and Applications in Electronic Design Automation. CAV João Marques-Silva, Karem A. Sakallah
2000	A	`conf`	On Applying Incremental Satisfiability to Delay Fault Testing. DATE Joonyoung Kim, Jesse Whittemore, Karem A. Sakallah, João P. Marques Silva
2000	C	`conf`	On Solving Stack-Based Incremental Satisfiability Problems. ICCD Joonyoung Kim, Jesse Whittemore, Karem A. Sakallah
1999	A*	`conf`	Functional Timing Analysis for IP Characterization. DAC Hakan Yalcin, Mohammad Mortazavi, Robert Palermo, Cyrus Bamji, Karem A. Sakallah
1999	J	`jnl`	GRASP: A Search Algorithm for Propositional Satisfiability. IEEE Trans. Computers João P. Marques Silva, Karem A. Sakallah
1999	Misc	`conf`	Satisfiability-Based Detailed FPGA Routing. VLSI Design Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar
1999	—	`conf`	Satisfiability-Based Functional Delay Fault Testing. VLSI Joonyoung Kim, João Marques-Silva, Karem A. Sakallah
1999	A	`conf`	Satisfiability-Based Layout Revisited: Detailed Routing of Complex FPGAs vis Search-Based Boolean SAT. FPGA Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar
1999	J	`jnl`	Timing verification of sequential dynamic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. David Van Campenhout, Trevor N. Mudge, Karem A. Sakallah
1999	—	`conf`	Transistor level micro-placement and routing for two-dimensional digital VLSI cell synthesis. ISPD Michael A. Riepe, Karem A. Sakallah
1998	A	`conf`	AFTA: A Formal Delay Model for Functional Timing Analysis. DATE V. Chandramouli, Jesse Whittemore, Karem A. Sakallah
1998	A*	`conf`	Congestion Driven Quadratic Placement. DAC Phiroze N. Parakh, Richard B. Brown, Karem A. Sakallah
1998	A*	`conf`	M32: A Constructive multilevel Logic Synthesis System. DAC Victor N. Kravets, Karem A. Sakallah
1998	J	`jnl`	Overview of complementary GaAs technology for high-speed VLSI circuits. IEEE Trans. Very Large Scale Integr. Syst. Richard B. Brown, Bruce Bernhardt, M. LaMacchia, J. Abrokwah, Phiroze N. Parakh, Todd D. Basso, Spencer M. Gold, S. Stetson, Claude R. Gauthier, D. Foster, B. Crawforth, T. McQuire, Karem A. Sakallah, Ronald J. Lomax, Trevor N. Mudge
1998	J	`jnl`	The edge-based design rule model revisited. ACM Trans. Design Autom. Electr. Syst. Michael A. Riepe, Karem A. Sakallah
1998	—	`conf`	Timing analysis using propositional satisfiability. ICECS Luís Guerra e Silva, João P. Marques Silva, Luís Miguel Silveira, Karem A. Sakallah
1997	—	`conf`	Robust Search Algorithms for Test Pattern Generation. FTCS João P. Marques Silva, Karem A. Sakallah
1997	—	`conf`	Signal Delay in Coupled, Distributed RC Lines in the Presence of Temporal Proximity. ARVLSI V. Chandramouli, Karem A. Sakallah, Ayman I. Kayssi
1996	A	`conf`	An approximate timing analysis method for datapath circuits. ICCAD Hakan Yalcin, John P. Hayes, Karem A. Sakallah
1996	B	`conf`	Conflict Analysis in Search Algorithms for Satisfiability. ICTAI João P. Marques Silva, Karem A. Sakallah
1996	A	`conf`	GRASP - a new search algorithm for satisfiability. ICCAD João P. Marques Silva, Karem A. Sakallah
1996	A*	`conf`	Modeling the Effects of Temporal Proximity of Input Transitions on Gate Propagation Delay and Transition Time. DAC V. Chandramouli, Karem A. Sakallah
1996	J	`jnl`	Ravel-XL: a hardware accelerator for assigned-delay compiled-code logic gate simulation. IEEE Trans. Very Large Scale Integr. Syst. Michael A. Riepe, João P. Marques Silva, Karem A. Sakallah, Richard B. Brown
1996	A	`conf`	Timing verification of sequential domino circuits. ICCAD David Van Campenhout, Trevor N. Mudge, Karem A. Sakallah
1995	J	`jnl`	Critical paths in circuits with level-sensitive latches. IEEE Trans. Very Large Scale Integr. Syst. Timothy M. Burks, Karem A. Sakallah, Trevor N. Mudge
1995	J	`jnl`	Maximum rate single-phase clocking of a closed pipeline including wave pipelining, stoppability, and startability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chuan-Hua Chang, Edward S. Davidson, Karem A. Sakallah
1995	A*	`conf`	The Aurora RAM Compiler. DAC Ajay Chandna, C. David Kibler, Richard B. Brown, Mark Roberts, Karem A. Sakallah
1995	J	`jnl`	Timing models for gallium arsenide direct-coupled FET logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ayman I. Kayssi, Karem A. Sakallah
1994	A*	`conf`	Dynamic Search-Space Pruning Techniques in Path Sensitization. DAC João P. Marques Silva, Karem A. Sakallah
1994	C	`conf`	Efficient and Robust Test Generation-Based Timing Analysis. ISCAS João P. Marques Silva, Karem A. Sakallah
1994	C	`conf`	Macromodel Simplification Using Dimensional Analysis. ISCAS Ayman I. Kayssi, Karem A. Sakallah
1994	A	`conf`	Optimization of critical paths in circuits with level-sensitive latches. ICCAD Timothy M. Burks, Karem A. Sakallah
1993	C	`conf`	An Analysis of Path Sensitization Criteria. ICCD João P. Marques Silva, Karem A. Sakallah
1993	—	`conf`	Concurrent path sensitization in timing analysis. EURO-DAC João P. Marques Silva, Karem A. Sakallah
1993	A	`conf`	Min-max linear programming and the timing analysis of digital circuits. ICCAD Timothy M. Burks, Karem A. Sakallah
1993	C	`conf`	Ravel-XL: A Hardware Accelerator for Assigned-Delay Compiled-Code Logic Gate Simulation. ICCD Michael A. Riepe, João P. Marques Silva, Karem A. Sakallah, Richard B. Brown
1993	J	`jnl`	Synchronization of pipelines. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Karem A. Sakallah, Trevor N. Mudge, Timothy M. Burks, Edward S. Davidson
1992	J	`jnl`	Analysis and design of latch-controlled synchronous digital circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Karem A. Sakallah, Trevor N. Mudge, Oyekunle A. Olukotun
1992	—	`conf`	Delay macromodels for the timing analysis of GaAs DCFL. EURO-DAC Ayman I. Kayssi, Karem A. Sakallah
1992	A	`conf`	Identification of critical paths in circuits with level-sensitive latches. ICCAD Timothy M. Burks, Karem A. Sakallah, Trevor N. Mudge
1992	A	`conf`	Ravel: assigned-delay compiled-code logic simulation. ICCAD Emily J. Shriver, Karem A. Sakallah
1992	A	`conf`	Using constraint geometry to determine maximum rate pipeline clocking. ICCAD Chuan-Hua Chang, Edward S. Davidson, Karem A. Sakallah
1991	A	`conf`	FPD - An Environment for Exact Timing Analysis. ICCAD João P. Marques Silva, Karem A. Sakallah, Luís M. Vidigal
1991	J	`jnl`	Multilevel optimization in the design of a high-performance GaAs microcomputer. IEEE J. Solid State Circuits Oyekunle A. Olukotun, Richard B. Brown, Ronald J. Lomax, Trevor N. Mudge, Karem A. Sakallah
1991	C	`conf`	Optimal Clocking of Circular Pipelines. ICCD Karem A. Sakallah, Trevor N. Mudge, Timothy M. Burks, Edward S. Davidson
1991	J	`jnl`	The Design of a Microsupercomputer. Computer Trevor N. Mudge, Richard B. Brown, William P. Bimingham, Jeffrey A. Dykstra, Ayman I. Kayssi, Ronald J. Lomax, Kunle Olukotun, Karem A. Sakallah, Raymond A. Milano
1990	J	`jnl`	A first-order charge conserving MOS capacitance model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Karem A. Sakallah, Yao-Tsung Yen, Steve S. Greenberg
1990	A*	`conf`	Analysis and Design of Latch-Controlled Synchronous Digital Circuits. DAC Karem A. Sakallah, Trevor N. Mudge, Kunle Olukotun
1990	—	`conf`	Clock Qualification Algorithm for Timing Analysis of Custom CMOS VLSI Circuits with Overlapped Clocking Disciplines and On-section Clock Derivation. ICSI Somanathan C. Menon, Karem A. Sakallah
1985	J	`jnl`	SAMSON2: An Event Driven VLSI Circuit Simulator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Karem A. Sakallah, Stephen W. Director