Karam S. Chatha

72 papers A* 8A 13B 1C 4Misc 14Journal 14Unranked 17
YearRankTypeTitle / Venue / Authors
2014 Misc ed.
2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES 2014, Uttar Pradesh, India, October 12-17, 2014
CASES
Karam S. Chatha, Rolf Ernst, Anand Raghunathan, Ravishankar R. Iyer
2014 J jnl
An Embedded Architecture for Energy-Efficient Stream Computing.
IEEE Embed. Syst. Lett.
Amrit Panda, Karam S. Chatha
2014 — conf
An embedded co-processor architecture for energy-efficient stream computing.
ESTIMedia
Amrit Panda, Karam S. Chatha
2014 J jnl
Guest Editors' Introduction - Special Issue on Network-on-Chip.
IEEE Trans. Computers
Ran Ginosar, Karam S. Chatha
2013 J jnl
Scheduling of synchronous data flow models onto scratchpad memory-based embedded processors.
ACM Trans. Embed. Comput. Syst.
Weijia Che, Karam S. Chatha
2012 Misc conf
Dynamic scheduling of stream programs on embedded multi-core processors.
CODES+ISSS
Haeseung Lee, Weijia Che, Karam S. Chatha
2012 A* conf
System-level synthesis of memory architecture for stream processing sub-systems of a MPSoC.
DAC
Glenn Leary, Weijia Che, Karam S. Chatha
2012 A* conf
Unrolling and retiming of stream applications onto embedded multicore processors.
DAC
Weijia Che, Karam S. Chatha
2011 A* conf
Compilation of stream programs onto scratchpad memory based embedded multicore processors through retiming.
DAC
Weijia Che, Karam S. Chatha
2011 — ed.
NOCS 2011, Fifth ACM/IEEE International Symposium on Networks-on-Chip, Pittsburgh, Pennsylvania, USA, May 1-4, 2011
NOCS
Radu Marculescu, Michael Kishinevsky, Ran Ginosar, Karam S. Chatha
2011 J jnl
Performance Optimal Online DVFS and Task Migration Techniques for Thermally Constrained Multi-Core Processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Vinay Hanumaiah, Sarma B. K. Vrudhula, Karam S. Chatha
2011 — conf
Scheduling of stream programs onto SPM enhanced processors with code overlay.
ESTIMedia
Weijia Che, Karam S. Chatha
2010 Misc conf
A holistic approach to network-on-chip synthesis.
CODES+ISSS
Glenn Leary, Karam S. Chatha
2010 C conf
A lightweight run-time scheduler for multitasking multicore stream applications.
ICCD
Michael A. Baker, Karam S. Chatha
2010 Misc conf
A performance model and code overlay generator for scratchpad enhanced embedded processors.
CODES+ISSS
Michael A. Baker, Amrit Panda, Nikhil Ghadge, Aniruddha Kadne, Karam S. Chatha
2010 A conf
Compilation of stream programs for multicore processors that incorporate scratchpad memories.
DATE
Weijia Che, Amrit Panda, Karam S. Chatha
2010 Misc conf
Design of NoC for SoC with Multiple Use Cases Requiring Guaranteed Performance.
VLSI Design
Glenn Leary, Karam S. Chatha
2010 — conf
Design of an Automatic Target Recognition algorithm on the IBM Cell Broadband Engine.
ASAP
Weijia Che, Karam S. Chatha
2010 A conf
Scheduling of synchronous data flow models on scratchpad memory based embedded processors.
ICCAD
Weijia Che, Karam S. Chatha
2010 A* conf
Thermal aware task sequencing on embedded processors.
DAC
Sushu Zhang, Karam S. Chatha
2009 Misc conf
A scalable parallel H.264 decoder on the cell broadband engine architecture.
CODES+ISSS
Michael A. Baker, Pravin Dalale, Karam S. Chatha, Sarma B. K. Vrudhula
2009 Misc conf
Automated technique for design of NoC with minimal communication latency.
CODES+ISSS
Glenn Leary, Karam S. Chatha
2009 J jnl
Circuits and systems for real-time security and copyright protection of multimedia.
Comput. Electr. Eng.
Saraju P. Mohanty, Nasir D. Memon, Karam S. Chatha
2009 J jnl
Design of Network-on-Chip Architectures With a Genetic Algorithm-Based Technique.
IEEE Trans. Very Large Scale Integr. Syst.
Glenn Leary, Krishnan Srinivasan, Krishna Mehta, Karam S. Chatha
2009 A conf
Maximizing performance of thermally constrained multi-core processors by dynamic voltage and frequency control.
ICCAD
Vinay Hanumaiah, Sarma B. K. Vrudhula, Karam S. Chatha
2009 A conf
Near optimal battery-aware energy management.
ISLPED
Sushu Zhang, Karam S. Chatha, Goran Konjevod
2009 A conf
Performance optimal speed control of multi-core processors under thermal constraints.
DATE
Vinay Hanumaiah, Sarma B. K. Vrudhula, Karam S. Chatha
2009 A* conf
Throughput optimal task allocation under thermal constraints for multi-core processors.
DAC
Vinay Hanumaiah, Ravishankar Rao, Sarma B. K. Vrudhula, Karam S. Chatha
2008 J jnl
Automated Techniques for Synthesis of Application-Specific Network-on-Chip Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Karam S. Chatha, Krishnan Srinivasan, Goran Konjevod
2008 — conf
Automated techniques for energy efficient scheduling on homogeneous and heterogeneous chip multi-processor architectures.
ASP-DAC
Sushu Zhang, Karam S. Chatha
2008 Misc conf
Power reduction via macroblock prioritization for power aware H.264 video applications.
CODES+ISSS
Michael A. Baker, Viswesh Parameswaran, Karam S. Chatha, Baoxin Li
2008 A conf
System-level thermal aware design of applications with uncertain execution time.
ICCAD
Sushu Zhang, Karam S. Chatha
2007 A conf
An ILP formulation for system-level application mapping on network processor architectures.
DATE
Christopher Ostler, Karam S. Chatha
2007 — conf
Application Specific Network-on-Chip Design with Guaranteed Quality Approximation Algorithms.
ASP-DAC
Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod
2007 A* conf
Approximation Algorithm for Data Mapping on Block Multi-threaded Network Processor Architectures.
DAC
Christopher Ostler, Karam S. Chatha
2007 — conf
Approximation Algorithm for Process Mapping on Network Processor Architectures.
ASP-DAC
Christopher Ostler, Karam S. Chatha, Goran Konjevod
2007 A conf
Approximation algorithm for the temperature-aware scheduling problem.
ICCAD
Sushu Zhang, Karam S. Chatha
2007 A conf
Approximation algorithms for power minimization of earliest deadline first and rate monotonic schedules.
ISLPED
Sushu Zhang, Karam S. Chatha, Goran Konjevod
2007 J jnl
ILP and heuristic techniques for system-level design on network processor architectures.
ACM Trans. Design Autom. Electr. Syst.
Christopher Ostler, Karam S. Chatha, Vijay Ramamurthi, Krishnan Srinivasan
2007 J jnl
Integer linear programming and heuristic techniques for system-level low power scheduling on multiprocessor architectures under throughput constraints.
Integr.
Krishnan Srinivasan, Karam S. Chatha
2007 J jnl
Optimization of media processing workflows with adaptive operator behaviors.
Multim. Tools Appl.
Lina Peng, K. Selçuk Candan, Christopher B. Mayer, Karam S. Chatha, Kyung Dong Ryu
2007 Misc conf
Performance and resource optimization of NoC router architecture for master and slave IP cores.
CODES+ISSS
Glenn Leary, Krishna Mehta, Karam S. Chatha
2007 Misc conf
Smart driver for power reduction in next generation bistable electrophoretic display technology.
CODES+ISSS
Michael A. Baker, Aviral Shrivastava, Karam S. Chatha
2006 — conf
A Methodology for Layout Aware Design and Optimization of Custom Network-on-Chip Architectures.
ISQED
Krishnan Srinivasan, Karam S. Chatha
2006 A conf
A low complexity heuristic for design of custom network-on-chip architectures.
DATE
Krishnan Srinivasan, Karam S. Chatha
2006 Misc conf
Layout aware design of mesh based NoC architectures.
CODES+ISSS
Krishnan Srinivasan, Karam S. Chatha
2006 J jnl
Linear-programming-based techniques for synthesis of network-on-chip architectures.
IEEE Trans. Very Large Scale Integr. Syst.
Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod
2006 — conf
Modular Design of Media Retrieval Workflows Using ARIA.
CIVR
Lina Peng, Gisik Kwon, Yinpeng Chen, K. Selçuk Candan, Hari Sundaram, Karam S. Chatha, Maria Luisa Sapino
2005 Misc conf
A Technique for Throughput and Register Optimization during Resource Constrained Pipelined Scheduling.
VLSI Design
Nagendran Rangan, Karam S. Chatha
2005 A conf
A technique for low energy mapping and routing in network-on-chip architectures.
ISLPED
Krishnan Srinivasan, Karam S. Chatha
2005 A conf
An automated technique for topology and route generation of application specific on-chip interconnection networks.
ICCAD
Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod
2005 Misc conf
ISIS: A Genetic Algorithm Based Technique for Custom On-Chip Interconnection Network Synthesis.
VLSI Design
Krishnan Srinivasan, Karam S. Chatha
2005 A* conf
Media processing workflow design and execution with ARIA.
ACM Multimedia
Lina Peng, Gisik Kwon, K. Selçuk Candan, Kyung Dong Ryu, Karam S. Chatha, Hari Sundaram, Yinpeng Chen
2005 J jnl
Quality-of-service and error control techniques for mesh-based network-on-chip architectures.
Integr.
Praveen Vellanki, Nilanjan Banerjee, Karam S. Chatha
2005 — conf
SAGA: synthesis technique for guaranteed throughput NoC architectures.
ASP-DAC
Krishnan Srinivasan, Karam S. Chatha
2005 — conf
System Level Methodology for Programming CMP Based Multi-Threaded Network Processor Architectures.
ISVLSI
Vijaykumar Ramamurthi, Jason McCollum, Christopher Ostler, Karam S. Chatha
2004 A conf
A Power and Performance Model for Network-on-Chip Architectures.
DATE
Nilanjan Banerjee, Praveen Vellanki, Karam S. Chatha
2004 — conf
A Technique for Energy versus Quality of Service Trade-Off for MPEG-2 Decoder.
ISVLSI
Krishnan Srinivasan, Vijay Ramamurthi, Karam S. Chatha
2004 A* conf
ARIA: an adaptive and programmable media-flow architecture for interactive arts.
ACM Multimedia
Lina Peng, K. Selçuk Candan, Kyung Dong Ryu, Karam S. Chatha, Hari Sundaram
2004 Misc conf
An ILP Formulation for System Level Throughput and Power Optimization in Multiprocessor SoC Architectures.
VLSI Design
Krishnan Srinivasan, Karam S. Chatha
2004 — conf
Efficient Stream Routing in Quality- and Resource-Adaptive Flow Architectures.
Multimedia Information Systems
K. Selçuk Candan, Lina Peng, Kyung Dong Ryu, Karam S. Chatha, Christopher B. Mayer
2004 C conf
Linear Programming based Techniques for Synthesis of Network-on-Chip Architectures.
ICCD
Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod
2004 — conf
Quality-of-service and error control techniques for network-on-chip architectures.
ACM Great Lakes Symposium on VLSI
Praveen Vellanki, Nilanjan Banerjee, Karam S. Chatha
2004 — conf
System-Level Design Techniques for Throughput and Power Optimization of Multiprocessor SoC Architectures.
ISVLSI
Krishnan Srinivasan, Nagender Telkar, Vijay Ramamurthi, Karam S. Chatha
2002 J jnl
Hardware-software partitioning and pipelined scheduling of transformative applications.
IEEE Trans. Very Large Scale Integr. Syst.
Karam S. Chatha, Ranga Vemuri
2001 — conf
MAGELLAN: multiway hardware-software partitioning and scheduling for latency minimization of hierarchical control-dataflow task graphs.
CODES
Karam S. Chatha, Ranga Vemuri
2000 J jnl
An Iterative Algorithm for Hardware-Software Partitioning, Hardware Design Space Exploration and Scheduling.
Des. Autom. Embed. Syst.
Karam S. Chatha, Ranga Vemuri
1999 C conf
An Iterative Algorithm for Partitioning and Scheduling of Area Constrained HW-SW Systems.
IEEE International Workshop on Rapid System Prototyping
Karam S. Chatha, Ranga Vemuri
1999 B conf
Hardware-Software Codesign for Dynamically Reconfigurable Architectures.
FPL
Karam S. Chatha, Ranga Vemuri
1998 — conf
A Tool for Partitioning and Pipelined Scheduling of Hardware-Software Systems.
ISSS
Karam S. Chatha, Ranga Vemuri
1998 C conf
Performance Evaluation Tool for Rapid Prototyping of Hardware-Software Codesigns.
International Workshop on Rapid System Prototyping
Karam S. Chatha, Ranga Vemuri
1998 — conf
RECOD: a retiming heuristic to optimize resource and memory utilization in HW/SW codesigns.
CODES
Karam S. Chatha, Ranga Vemuri