Kanishka Lahiri

41 papers A* 7A 7B 4Misc 9Journal 9Unranked 5
YearRankTypeTitle / Venue / Authors
2020 — conf
Characterizing the Scale-Up Performance of Microservices using TeaStore.
IISWC
Sriyash Caculo, Kanishka Lahiri, Subramaniam Kalambur
2019 B conf
Performance Scaling of Cassandra on High-Thread Count Servers.
ICPE
Disha Talreja, Kanishka Lahiri, Subramaniam Kalambur, Prakash Sathyanath Raghavendra
2017 B conf
DARTS: Performance-counter driven sampling using binary translators.
ISPASS
Rajesh Kumar, Suchita Pati, Kanishka Lahiri
2017 B conf
Fast IPC estimation for performance projections using proxy suites and decision trees.
ISPASS
Kanishka Lahiri, Subhash Kunnoth
2015 Misc conf
Characterizing Large Dataset GPU Compute Workloads Targeting Systems with Die-Stacked Memory.
HiPC
Srividya Ramanathan, Gautam Hazari, Kanishka Lahiri, Francesco Spadini
2010 J jnl
Variation-Aware System-Level Power Analysis.
IEEE Trans. Very Large Scale Integr. Syst.
Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey
2009 J jnl
Variation-Tolerant Dynamic Power Management at the System-Level.
IEEE Trans. Very Large Scale Integr. Syst.
Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey
2008 J jnl
Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication.
IEEE Trans. Very Large Scale Integr. Syst.
Krishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey
2007 A* conf
Accelerating System-on-Chip Power Analysis Using Hybrid Power Estimation.
DAC
Mohammad Ali Ghodrat, Kanishka Lahiri, Anand Raghunathan
2007 Misc conf
Automatic Power Modeling of Infrastructure IP for System-on-Chip Power Analysis.
VLSI Design
Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan
2007 A* conf
System-on-Chip Power Management Considering Leakage Power Variations.
DAC
Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey
2007 Misc conf
Tutorial 5: SoC Communication Architectures: Technology, Current Practice, Research, and Trends.
VLSI Design
Nikil D. Dutt, Kaustav Banerjee, Luca Benini, Kanishka Lahiri, Sudeep Pasricha
2006 A conf
Adaptive data placement in an embedded multiprocessor thread library.
DATE
Phillip Stanley-Marbell, Kanishka Lahiri, Anand Raghunathan
2006 A conf
Considering process variations during system-level power analysis.
ISLPED
Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey
2006 A conf
Integrated data relocation and bus reconfiguration for adaptive system-on-chip platforms.
DATE
Krishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey
2006 A conf
Power analysis of mobile 3D graphics.
DATE
Bren Mochocki, Kanishka Lahiri, Srihari Cadambi
2006 A* conf
Signature-based workload estimation for mobile 3D graphics.
DAC
Bren Mochocki, Kanishka Lahiri, Srihari Cadambi, Xiaobo Sharon Hu
2006 J jnl
The LOTTERYBUS on-chip communication architecture.
IEEE Trans. Very Large Scale Integr. Syst.
Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana
2005 B conf
Battery discharge characteristics of wireless sensor nodes: an experimental analysis.
SECON
Chulsung Park, Kanishka Lahiri, Anand Raghunathan
2005 A* conf
FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology.
DAC
Krishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey
2005 Misc conf
Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models.
VLSI Design
Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan, Srimat T. Chakradhar
2005 — conf
SOFTENIT: a methodology for boosting the software content of system-on-chip designs.
ACM Great Lakes Symposium on VLSI
Abhishek Mitra, Marcello Lajolo, Kanishka Lahiri
2004 Misc conf
Configurable Platforms With Dynamic Platform Management: An Efficient Alternative to Application-Specific System-on-Chips.
VLSI Design
Krishna Sekar, Kanishka Lahiri, Sujit Dey
2004 J jnl
Design of high-performance system-on-chips using communication architecture tuners.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana, Sujit Dey
2004 J jnl
Design space exploration for optimizing on-chip communication architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kanishka Lahiri, Anand Raghunathan, Sujit Dey
2004 J jnl
Efficient power profiling for battery-driven embedded system design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kanishka Lahiri, Anand Raghunathan, Sujit Dey
2004 Misc conf
Power analysis of system-level on-chip communication architectures.
CODES+ISSS
Kanishka Lahiri, Anand Raghunathan
2003 A conf
Dynamic Platform Management for Configurable Platform-Based System-on-Chips.
ICCAD
Krishna Sekar, Kanishka Lahiri, Sujit Dey
2002 — conf
Battery-efficient architecture for an 802.11 MAC processor.
ICC
Kanishka Lahiri, Anand Raghunathan, Sujit Dey
2002 A* conf
Communication architecture based power management for battery efficient system design.
DAC
Kanishka Lahiri, Sujit Dey, Anand Raghunathan
2002 J jnl
Communication-Based Power Management.
IEEE Des. Test Comput.
Kanishka Lahiri, Sujit Dey, Anand Raghunathan
2002 — conf
Embedded Tutorial: Battery-Driven System Design: A New Frontier in Low Power Design.
ASP-DAC/VLSI Design
Kanishka Lahiri, Anand Raghunathan, Sujit Dey, Debashis Panigrahi
2002 — conf
Fast system-level power profiling for battery-efficient system design.
CODES
Kanishka Lahiri, Anand Raghunathan, Sujit Dey
2001 Misc conf
Battery Life Estimation of Mobile Embedded Systems.
VLSI Design
Debashis Panigrahi, Sujit Dey, Ramesh R. Rao, Kanishka Lahiri, Carla-Fabiana Chiasserini, Anand Raghunathan
2001 Misc conf
Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures.
VLSI Design
Kanishka Lahiri, Sujit Dey, Anand Raghunathan
2001 A* conf
LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs.
DAC
Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana
2001 J jnl
System-level performance analysis for designing on-chipcommunication architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kanishka Lahiri, Anand Raghunathan, Sujit Dey
2000 A* conf
Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chips.
DAC
Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana, Sujit Dey
2000 A conf
Efficient Exploration of the SoC Communication Architecture Design Space.
ICCAD
Kanishka Lahiri, Anand Raghunathan, Sujit Dey
2000 Misc conf
Performance Analysis of Systems with Multi-Channel Communication Architectures.
VLSI Design
Kanishka Lahiri, Sujit Dey, Anand Raghunathan
1999 A conf
Fast performance analysis of bus-based system-on-chip communication architectures.
ICCAD
Kanishka Lahiri, Anand Raghunathan, Sujit Dey