Kanglin Xiao

15 papers B 1C 3Journal 5Unranked 6
YearRankTypeTitle / Venue / Authors
2024 J jnl
A 28nm 8Kb Reconfigurable SRAM Computing-In-Memory Macro With Input-Sparsity Optimized DTC for Multi-Mode MAC Operations.
IEEE Trans. Circuits Syst. II Express Briefs
Kanglin Xiao, Xin Qiao, Xiaoxin Cui, Jiahao Song, Haoyang Luo, Xin'an Wang, Yuan Wang
2024 J jnl
How the Brain Achieves Real-Time Vision: A Spiking Position Perception Model.
IEEE Trans. Cogn. Dev. Syst.
Kefei Liu, Jingjie Shang, Xiaoxin Cui, Chenglong Zou, Yisong Kuang, Kanglin Xiao, Yi Zhong, Yuan Wang
2023 J jnl
A 28nm 32Kb SRAM Computing-in-Memory Macro With Hierarchical Capacity Attenuator and Input Sparsity-Optimized ADC for 4b Mac Operation.
IEEE Trans. Circuits Syst. II Express Briefs
Kanglin Xiao, Xiaoxin Cui, Xin Qiao, Jiahao Song, Haoyang Luo, Xin'an Wang, Yuan Wang
2023 J jnl
Real-Time Target Tracking System With Spiking Neural Networks Implemented on Neuromorphic Chips.
IEEE Trans. Circuits Syst. II Express Briefs
Kefei Liu, Xiaoxin Cui, Xiang Ji, Yisong Kuang, Chenglong Zou, Yi Zhong, Kanglin Xiao, Yuan Wang
2022 J jnl
A 128 Kb DAC-less 6T SRAM computing-in-memory macro with prioritized subranging ADC for AI edge applications.
Microelectron. J.
Kanglin Xiao, Xiaoxin Cui, Xin Qiao, Xin'an Wang, Yuan Wang
2022 C conf
A 28nm 64Kb SRAM based Inference-Training Tri-Mode Computing-in-Memory Macro.
ISCAS
Nanbing Pan, Xiaoxin Cui, Xin Qiao, Kanglin Xiao, Qingyu Guo, Yuan Wang
2022 C conf
A Computing-in-Memory SRAM Macro Based on Fully-Capacitive-Coupling With Hierarchical Capacity Attenuator for 4-b MAC Operation.
ISCAS
Kanglin Xiao, Xiaoxin Cui, Xin Qiao, Nanbing Pan, Xin'an Wang, Yuan Wang
2022 — conf
A Full-Neuron Memory Model Designed for Neuromorphic Systems.
AICAS
Kefei Liu, Xiaoxin Cui, Chenglong Zou, Yisong Kuang, Yi Zhong, Kanglin Xiao, Yuan Wang
2022 — conf
A Reconfigurable SRAM Computing-in-Memory Macro Supporting Ping-Pong Operation and CIM pipeline for Multi-mode MAC operations.
ICTA
Kanglin Xiao, Xiaoxin Cui, Xin Qiao, Xin'an Wang, Yuan Wang
2021 B conf
An SNN-Based and Neuromorphic-Hardware-Implementable Noise Filter with Self-adaptive Time Window for Event-Based Vision Sensor.
IJCNN
Kanglin Xiao, Xiaoxin Cui, Kefei Liu, Xiaole Cui, Xin'an Wang
2021 C conf
Design and Implementation of a Temperature Self-Compensation Balanced Hybrid Ring Oscillator BHRO.
ISCAS
Kanglin Xiao, Bo Wang, Changpei Qiu, Xin'an Wang
2019 — conf
BNReLU: Combine Batch Normalization and Rectified Linear Unit to Reduce Hardware Overhead.
ASICON
Jiexian Ge, Xiaoxin Cui, Kanglin Xiao, Chenglong Zou, Yi-Hsiang Chen, Rongshan Wei
2019 — conf
Improved Discrete Wavelet Analysis and Principal Component Analysis for EEG Signal Processing.
ASICON
Yi-Hsiang Chen, Xiaoxin Cui, Kanglin Xiao, Dunshan Yu
2018 — conf
A balanced hybrid ring oscillator for precise temperature compensation.
MWSCAS
Kanglin Xiao, Bo Wang, Xiaoqi Lin, Changpei Qiu
2018 — conf
A multi-phase detecting method for spurs cancellation in all digital fractional-N phase-lock loops.
MWSCAS
Tingbing Ouyang, Kanglin Xiao, Xiaoqi Lin, Changpei Qiu, Bo Wang