Kang-Deog Suh - RankMe

12 papers Journal 12

Year	Rank	Type	Title / Venue / Authors
2010	J	`jnl`	Boosted Bit Line Program Scheme for Low Operating Voltage MLC NAND Flash Memory. IEICE Trans. Electron. Youngsun Song, Ki-Tae Park, Myounggon Kang, Yunheub Song, Sungsoo Lee, Youngho Lim, Kang-Deog Suh
2010	J	`jnl`	Dynamic Vpass Controlled Program Scheme and Optimized Erase Vth Control for High Program Inhibition in MLC NAND Flash Memories. IEEE J. Solid State Circuits Ki-Tae Park, Youngsun Song, Myounggon Kang, Sungsoo Lee, Youngho Lim, Kang-Deog Suh, Chilhee Chung
2003	J	`jnl`	A 90-nm CMOS 1.8-V 2-Gb NAND flash memory for mass storage applications. IEEE J. Solid State Circuits June Lee, Sung-Soo Lee, Oh-Suk Kwon, Kyeong-Han Lee, Dae-Seok Byeon, In-Young Kim, Kyoung-Hwa Lee, Young-Ho Lim, Byung-Soon Choi, Jong-Sik Lee, Wang-Chul Shin, Jeong-Hyuk Choi, Kang-Deog Suh
2002	J	`jnl`	High-performance 1-Gb-NAND flash memory with 0.12-μm technology. IEEE J. Solid State Circuits June Lee, Heung-Soo Im, Dae-Seok Byeon, Kyeong-Han Lee, Dong-hyuk Chae, Kyong-Hwa Lee, Sang Won Hwang, Sung-Soo Lee, Young-Ho Lim, Jae-Duk Lee, Jung-Dal Choi, Young-Il Seo, Jong-Sik Lee, Kang-Deog Suh
2001	J	`jnl`	A dual-mode NAND flash memory: 1-Gb multilevel and high-performance 512-Mb single-level modes. IEEE J. Solid State Circuits Taehee Cho, Yeong-Taek Lee, Eun-Cheol Kim, Jin-Wook Lee, Sunmi Choi, Seungjae Lee, Dong-Hwan Kim, Wook-Ghee Han, Young-Ho Lim, Jae-Duk Lee, Jung-Dal Choi, Kang-Deog Suh
2000	J	`jnl`	A 0.4-μm 3.3-V 1T1C 4-Mb nonvolatile ferroelectric RAM with fixed bitline reference voltage scheme and data protection circuit. IEEE J. Solid State Circuits Byung-Gil Jeon, Mun-Kyu Choi, Yoonjong Song, Seung-Kyu Oh, Yeonbae Chung, Kang-Deog Suh, Kinam Kim
2000	J	`jnl`	A 3.3-V, 4-Mb nonvolatile ferroelectric RAM with selectively driven double-pulsed plate read/write-back scheme. IEEE J. Solid State Circuits Yeonbae Chung, Byung-Gil Jeon, Kang-Deog Suh
1998	J	`jnl`	An 8-bit-resolution, 360-μs write time nonvolatile analog memory based on differentially balanced constant-tunneling-current scheme (DBCS). IEEE J. Solid State Circuits Kyu-Hyoun Kim, Kwyro Lee, Tae-Sung Jung, Kang-Deog Suh
1997	J	`jnl`	A 120-mm IEEE J. Solid State Circuits Jin-Ki Kim, Koji Sakui, Sung-Soo Lee, Yasuo Itoh, Suk-Chon Kwon, Kazuhisa Kanazawa, Ki-Jun Lee, Hiroshi Nakamura, Kang-Young Kim, Toshihiko Himeno, Jang-Rae Kim, Kazushige Kanda, Tae-Sung Jung, Yoichi Oshima, Kang-Deog Suh, Kazuhiko Hashimoto, Sung-Tae Ahn, Junichi Miyamoto
1997	J	`jnl`	A 3.3-V single power supply 16-Mb nonvolatile virtual DRAM using a NAND flash memory technology. IEEE J. Solid State Circuits Tae-Sung Jung, Do-Chan Choi, Sung-Hee Cho, Myong-Jae Kim, Seung-Keun Lee, Byung-Soon Choi, Jin-Sun Yum, San-Hong Kim, Dong-Gi Lee, Jong-Chang Son, Myung-Sik Yong, Heung-Kwun Oh, Sung-Bu Jun, Woung-Moo Lee, E. Haq, Kang-Deog Suh, S. B. Ali, Hyung-Kyu Lim
1996	J	`jnl`	A 117-mm IEEE J. Solid State Circuits Tae-Sung Jung, Young-Joon Choi, Kang-Deog Suh, Byung-Hoon Suh, Jin-Ki Kim, Young-Ho Lim, Yong-Nam Koh, Jong-Wook Park, Ki-Jong Lee, Jung-Hoon Park, Kee-Tae Park, Jhang-Rae Kim, Jeong-Hyong Yi, Hyung-Kyu Lim
1995	J	`jnl`	A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme. IEEE J. Solid State Circuits Kang-Deog Suh, Byung-Hoon Suh, Young-Ho Lim, Jin-Ki Kim, Young-Joon Choi, Yong-Nam Koh, Sung-Soo Lee, Suk-Chon Kwon, Byung-Soon Choi, Jin-Sun Yum, Jung-Hyuk Choi, Jang-Rae Kim, Hyung-Kyu Lim