Kan Shi - RankMe

20 papers A* 3A 3B 1C 1Misc 1Journal 5Unranked 6

Year	Rank	Type	Title / Venue / Authors
2026	A*	`conf`	TurboFuzz: FPGA Accelerated Hardware Fuzzing for Processor Agile Verification. HPCA Yang Zhong, Haoran Wu, Xueqi Li, Sa Wang, David Boland, Yungang Bao, Kan Shi
2025	—	`conf`	Corvus: Efficient HW/SW Co-Verification Framework for RISC-V Instruction Extensions with FPGA Acceleration. ASP-DAC Zijian Jiang, Keran Zheng, David Boland, Yungang Bao, Kan Shi
2025	A	`conf`	Hercules: Efficient Verification of High-Level Synthesis Designs with FPGA Acceleration. FPGA Shuoxiang Xu, Zijian Jiang, Yuxin Zhang, David Boland, Yungang Bao, Kan Shi
2025	A	`conf`	Latency Insensitivity Testing for Dataflow HLS Designs. FPGA Jianyi Cheng, Lianghui Wang, Zijian Jiang, Yungang Bao, Kan Shi
2025	J	`jnl`	Lyra: A Hardware-Accelerated RISC-V Verification Framework with Generative Model-Based Processor Fuzzing. CoRR Juncheng Huo, Yunfan Gao, Xinxin Liu, Sa Wang, Yungang Bao, Xitong Gao, Kan Shi
2025	—	`conf`	Poby: SmartNIC-accelerated Image Provisioning for Coldstart in Clouds. USENIX ATC Zihao Chang, Jiaqi Zhu, Haifeng Sun, Yunlong Xie, Kan Shi, Ninghui Sun, Yungang Bao, Sa Wang
2025	J	`jnl`	TurboFuzz: FPGA Accelerated Hardware Fuzzing for Processor Agile Verification. CoRR Yang Zhong, Haoran Wu, Xueqi Li, Sa Wang, David Boland, Yungang Bao, Kan Shi
2024	—	`conf`	Hassert: Hardware Assertion-Based Verification Framework with FPGA Acceleration. ASPLOS (4) Ziqing Zhang, Weijie Weng, Yaning Li, Lijia Cai, Haoyu Wang, David Boland, Yungang Bao, Kan Shi
2023	A	`conf`	ENCORE: Efficient Architecture Verification Framework with FPGA Acceleration. FPGA Kan Shi, Shuoxiang Xu, Yuhan Diao, David Boland, Yungang Bao
2023	J	`jnl`	Functional Verification for Agile Processor Development: A Case for Workflow Integration. J. Comput. Sci. Technol. Yinan Xu, Zihao Yu, Kaifan Wang, Huaqiang Wang, Jiawei Lin, Yue Jin, Linjuan Zhang, Zifei Zhang, Dan Tang, Sa Wang, Kan Shi, Ninghui Sun, Yungang Bao
2022	B	`conf`	Increasing Flexibility of Cloud FPGA Virtualization. FPL Jinjie Ruan, Yisong Chang, Ke Zhang, Kan Shi, Mingyu Chen, Yungang Bao
2022	A*	`conf`	Towards Developing High Performance RISC-V Processors Using Agile Methodology. MICRO Yinan Xu, Zihao Yu, Dan Tang, Guokai Chen, Lu Chen, Lingrui Gou, Yue Jin, Qianruo Li, Xin Li, Zuojun Li, Jiawei Lin, Tong Liu, Zhigang Liu, Jiazhan Tan, Huaqiang Wang, Huizhe Wang, Kaifan Wang, Chuanqi Zhang, Fawang Zhang, Linjuan Zhang, Zifei Zhang, Yangyang Zhao, Yaoyang Zhou, Yike Zhou, Jiangrui Zou, Ye Cai, Dandan Huan, Zusong Li, Jiye Zhao, Zihao Chen, Wei He, Qiyuan Quan, Xingwu Liu, Sa Wang, Kan Shi, Ninghui Sun, Yungang Bao
2015	J	`jnl`	Imprecise Datapath Design: An Overclocking Approach. ACM Trans. Reconfigurable Technol. Syst. Kan Shi, David Boland, George A. Constantinides
2014	—	`conf`	Combining grey systems theory and entropy method to evaluate the organizational health. FSKD Xiaoqian Liu, Kan Shi, Lei Xing
2014	A*	`conf`	Datapath Synthesis for Overclocking: Online Arithmetic for Latency-Accuracy Trade-offs. DAC Kan Shi, David Boland, Edward A. Stott, Samuel Bayliss, George A. Constantinides
2014	J	`jnl`	Delay Test for Diagnosis of Power Switches. IEEE Trans. Very Large Scale Integr. Syst. S. Saqib Khursheed, Kan Shi, Bashir M. Al-Hashimi, Peter R. Wilson, Krishnendu Chakrabarty
2014	—	`conf`	Efficient FPGA implementation of digit parallel online arithmetic operators. FPT Kan Shi, David Boland, George A. Constantinides
2013	Misc	`conf`	Accuracy-Performance Tradeoffs on an FPGA through Overclocking. FCCM Kan Shi, David Boland, George A. Constantinides
2013	C	`conf`	Overclocking datapath for latency-error tradeoff. ISCAS Kan Shi, David Boland, George A. Constantinides
2009	—	`conf`	The Influence Factors and Mechanism of Societal Risk Perception. Complex (2) Rui Zheng, Kan Shi, Shu Li