Kamran Azadet

27 papers B 1C 5Misc 2Journal 8Unranked 11
YearRankTypeTitle / Venue / Authors
2021 — conf
10.6 A 12b 16GS/s RF-Sampling Capacitive DAC for Multi-Band Soft-Radio Base-Station Applications with On-Chip Transmission-Line Matching Network in 16nm FinFET.
ISSCC
Daniel Gruber, Martin Clara, Ramón Sanchez-Perez, Yu-shan Wang, Christoph Duller, Gerald Rauter, Patrick Torta, Kamran Azadet
2021 — conf
10.7 A 64GS/s 4×-Interpolated 1b Semi-Digital FIR DAC for Wideband Calibration and BIST of RF-Sampling A/D Converters.
ISSCC
Martin Clara, Daniel Gruber, Albert Molina, Matteo Camponeschi, Yu-shan Wang, Christian Lindholm, Hundo Shin, Ramón Sanchez-Perez, Christoph Duller, Patrick Torta, Kamran Azadet
2021 J jnl
A 12-b 16-GS/s RF-Sampling Capacitive DAC for Multi-Band Soft Radio Base-Station Applications With On-Chip Transmission-Line Matching Network in 16-nm FinFET.
IEEE J. Solid State Circuits
Daniel Gruber, Martin Clara, Ramón Sanchez-Perez, Yu-shan Wang, Christoph Duller, Gerald Rauter, Patrick Torta, Gerhard Knoblinger, Kamran Azadet
2021 — conf
A K-Band 12.1-to-16.6GHz Subsampling ADPLL with 47.3fsrms Jitter Based on a Stochastic Flash TDC and Coupled Dual-Core DCO in 16nm FinFET CMOS.
ISSCC
Edwin Thaller, Run Levinger, Evgeny Shumaker, Aryeh Farber, Sergey Bershansky, Nir Geron, Ashoke Ravi, Rotem Banin, Jasmin Kadry, Gil Horovitz, Christian Krassnitzer, Christoph Duller, Patrick Torta, Mark Elzinga, Kamran Azadet
2015 — conf
A 150 MHz bandwidth continuous-time ΔΣ modulator in 28 nm CMOS with DAC calibration.
MWSCAS
Rui Wang, Yang You, Guoying Wu, Xiaoke Wen, Tianshi He, Jinghong Chen, Kamran Azadet, Ping Gui
2015 J jnl
Nonlinearity Modeling of a Chireix Outphasing Power Amplifier.
IEEE Trans. Circuits Syst. I Regul. Pap.
Taesong Hwang, Kamran Azadet, Ross S. Wilson, Jenshan Lin
2012 C conf
A power-optimized reconfigurable CT ΔΣ modulator in 65nm CMOS.
ISCAS
Rui Wang, Xiaoke Wen, Kamran Azadet, Changzhi Li, Jinghong Chen
2007 Misc conf
Toward Maximizing Throughput in Wireless Relay: A General User Cooperation Model.
CISS
Meng Yu, Jing (Tiffany) Li, Rick S. Blum, Kamran Azadet
2006 J jnl
A Multi-Carrier QAM Transceiver for Ultra-Wideband Optical Communication.
IEEE J. Solid State Circuits
Jinghong Chen, Fadi Saibi, Eduard Säckinger, Joseph H. Othmer, Meng-Lin (Mark) Yu, Fuji Yang, Jenshan Lin, Titus Huang, Tingping Liu, Kamran Azadet
2005 — conf
An integrated CMOS transceiver for a 40Gb/s SCM optical communication system.
CICC
Jinghong Chen, Fadi Saibi, Eduard Säckinger, Kamran Azadet, Joe Othmer, Mark YU, Fuji Yang, Jenshan Lin, Titus Huang, Tingping Liu
2003 — conf
Frequency-interleaving technique for high-speed A/D conversion.
ISCAS (1)
Guillaume Ding, Catherine Dehollain, Michel J. Declercq, Kamran Azadet
2002 — conf
A low power adaptive filter using dynamic reduced 2's-complement representation.
CICC
Zhan Yu, Meng-Lin Yu, Kamran Azadet, Alan N. Willson Jr.
2002 J jnl
Equalization and FEC techniques for optical transceivers.
IEEE J. Solid State Circuits
Kamran Azadet, Erich F. Haratsch, Helen Kim, Fadi Saibi, Jeffrey H. Saunders, Michael Shaffer, Leilei Song, Meng-Lin Yu
2002 — conf
The use of reduced two's-complement representation in low-power DSP design.
ISCAS (1)
Zhan Yu, Meng-Lin Yu, Kamran Azadet, Alan N. Willson Jr.
2001 J jnl
A 1-Gb/s joint equalizer and trellis decoder for 1000BASE-T Gigabit Ethernet.
IEEE J. Solid State Circuits
Erich F. Haratsch, Kamran Azadet
2001 — conf
DSP techniques for optical transceivers.
CICC
Kamran Azadet, Erich Haratsch, Helen Kim, Fadi Saibi, Jeffrey H. Saunders, Mike Shaffer, Leilei Song, Meng-Lin Yu
2000 — conf
A low complexity joint equalizer and decoder for 1000Base-T Gigabit Ethernet.
CICC
Erich F. Haratsch, Kamran Azadet
2000 C conf
High-speed reduced-state sequence estimation.
ISCAS
Erich F. Haratsch, Kamran Azadet
2000 B conf
Pipelined reduced-state sequence estimation.
GLOBECOM
Erich F. Haratsch, Kamran Azadet
2000 — conf
Reduced-State Sequence Estimation with Tap-Selectable Decision-Feedback.
ICC (1)
Erich F. Haratsch, Andrew J. Blanksby, Kamran Azadet
1998 J jnl
A 200-mW, 3.3-V, CMOS color camera IC producing 352×288 24-b video at 30 frames/s.
IEEE J. Solid State Circuits
Marc J. Loinaz, Kanwar Jit Singh, Andrew J. Blanksby, David A. Inglis, Kamran Azadet, Bryan D. Ackland
1998 J jnl
Low-power equalizer architectures for high-speed modems.
IEEE Commun. Mag.
Kamran Azadet, Chris J. Nicole
1998 Misc conf
Reconfigurable hardware for efficient implementation of programmable FIR filters.
ICASSP
Tracy C. Denk, Chris J. Nicol, Patrik Larsson, Kamran Azadet
1997 J jnl
A low-power 128-tap digital adaptive equalizer for broadband modems.
IEEE J. Solid State Circuits
Chris J. Nicol, Patrik Larsson, Kamran Azadet, Jay H. O'Neill
1995 C conf
A Mismatch-Free CMOS Dynamic Voltage Comparator.
ISCAS
Kamran Azadet, Alex G. Dickinson, David A. Inglis
1994 C conf
Mixed-Mode Continuous-Time Video Acquisition Filters.
ISCAS
Kamran Azadet, J. Porte, F. Yang, J. E. D. Hurwitz
1994 C conf
The Design of CMOS Transconductor for High Frequency Continuous-Time Filter Applications.
ISCAS
F. Yang, PatrickSenn Loumeaeu, Kamran Azadet, Patrice Senn