Kamil Mielcarek

19 papers Journal 6Unranked 11

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	Hardware Reduction for FSMs With Extended State Codes. IEEE Access Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, Malgorzata Mazurkiewicz
2024	J	`jnl`	Reducing the number of LUTs for Mealy FSMs with state transformation. Int. J. Appl. Math. Comput. Sci. Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek
2022	J	`jnl`	Improving Characteristics of FSMs With Mixed Codes of Outputs. IEEE Access Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski, Kamil Mielcarek
2022	—	`book`	Logic Synthesis for VLSI-Based Combined Finite State Machines - Synthesis Targeting ASICs, CPLDs and FPGAs Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, Malgorzata Mazurkiewicz, Elzbieta Kawecka
2022	J	`jnl`	Reducing LUT Count for Mealy FSMs With Transformation of States. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Alexander A. Barkalov, Larysa Titarenko, Kamil Mielcarek
2020	J	`jnl`	Improving characteristics of LUT-based Mealy FSMs. Int. J. Appl. Math. Comput. Sci. Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek
2020	—	`book`	Logic Synthesis for FPGA-Based Control Units - Structural Decomposition in Logic Design Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, Slawomir Chmielewski
2019	—	`conf`	Decreasing Number of LUTs for Moore FSMs. MIXDES Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, Kazimierz Krzywicki, Wojciech Zajac
2019	—	`conf`	Design of FPGA-Based Mealy FSMs with Counters. MOCAST Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski, Kamil Mielcarek
2019	—	`conf`	Designing FPGA-Based Mealy FSMs with Two Levels of Logic. MOCAST Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek
2019	—	`conf`	Encoding of Microoperations in FPGA-Based Moore FSMs. MOCAST Alexander Barkalov, Larysa Titarenko, Malgorzata Mazurkiewicz, Kamil Mielcarek
2018	—	`conf`	Design of FPGA-based Mealy FSMs with Counters. MIXDES Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, Slawomir Chmielewski
2018	—	`conf`	Encoding of Terms in LUT-based Mealy FSMs. MIXDES Alexander Barkalov, Larysa Titarenko, Malgorzata Mazurkiewicz, Kamil Mielcarek
2018	J	`jnl`	Hardware Reduction for Lut-Based Mealy FSMs. Int. J. Appl. Math. Comput. Sci. Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek
2018	—	`conf`	Twofold State Assignment for LUT-based Mealy FSMs. MIXDES Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek
2018	—	`conf`	Twofold state assignment for FPGA-based mealy FSMs. MOCAST Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek
2017	—	`conf`	Designing HFPGA-based Mealy FSMs with transformation of output functions. MIXDES Kamil Mielcarek, Alexander Barkalov, Larysa Titarenko
2017	—	`conf`	Designing Moore FSM with Transformation of State Codes. CISIM Kamil Mielcarek, Alexander Barkalov, Larisa Titarenko
2017	—	`conf`	Designing Moore FSM with extended class codes. MOCAST Kamil Mielcarek, Alexander Barkalov, Larysa Titarenko