Kaiyan Chang - RankMe

17 papers A* 2A 2Journal 12Unranked 1

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A System Architecture for Low Latency Multiprogramming Quantum Computing. CoRR Yilun Zhao, Yu Chen, Kaiyan Chang, He Li, Bing Li, Yinhe Han, Ying Wang
2025	J	`jnl`	A data-centric chip design agent framework for Verilog code generation. ACM Trans. Design Autom. Electr. Syst. Kaiyan Chang, Wenlong Zhu, Kun Wang, Xinyang He, Nan Yang, Zhirong Chen, Dantong Jin, Cangyuan Li, Yunhao Zhou, Hao Yan, Zhuoliang Zhao, Yuan Cheng, Mengdi Wang, Shengwen Liang, Yinhe Han, Xiaowei Li, Huawei Li, Ying Wang
2025	J	`jnl`	AutoSilicon: Scaling Up RTL Design Generation Capability of Large Language Models. ACM Trans. Design Autom. Electr. Syst. Cangyuan Li, Chujie Chen, Yudong Pan, Wenjun Xu, Yiqi Liu, Kaiyan Chang, Yujie Wang, Mengdi Wang, Huawei Li, Yinhe Han, Ying Wang
2025	J	`jnl`	ChipSeek-R1: Generating Human-Surpassing RTL with LLM via Hierarchical Reward-Driven Reinforcement Learning. CoRR Zhirong Chen, Kaiyan Chang, Zhuolin Li, Xinyang He, Chujie Chen, Cangyuan Li, Mengdi Wang, Haobo Xu, Yinhe Han, Ying Wang
2025	A*	`conf`	LLMulator: Generalizable Cost Modeling for Dataflow Accelerators with Input-Adaptive Control Flow. MICRO Kaiyan Chang, Wenlong Zhu, Shengwen Liang, Huawei Li, Ying Wang
2025	J	`jnl`	LLMulator: Generalizable Cost Modeling for Dataflow Accelerators with Input-Adaptive Control Flow. CoRR Kaiyan Chang, Wenlong Zhu, Shengwen Liang, Huawei Li, Ying Wang
2025	J	`jnl`	Large Processor Chip Model. CoRR Kaiyan Chang, Mingzhi Chen, Yunji Chen, Zhirong Chen, Dongrui Fan, Junfeng Gong, Nan Guo, Yinhe Han, Qinfen Hao, Shuo Hou, Xuanjing Huang, Pengwei Jin, Changxin Ke, Cangyuan Li, Guangli Li, Huawei Li, Kuan Li, Naipeng Li, Shengwen Liang, Cheng Liu, Hongwei Liu, Jiahua Liu, Junliang Lv, Jianan Mu, Jin Qin, Bin Sun, Chenxi Wang, Duo Wang, Mingjun Wang, Ying Wang, Chenggang Wu, Peiyang Wu, Teng Wu, Xiao Xiao, Mengyao Xie, Chenwei Xiong, Ruiyuan Xu, Mingyu Yan, Xiaochun Ye, Kuai Yu, Rui Zhang, Shuoming Zhang, Jiacheng Zhao
2025	—	`conf`	RTLMarker: Protecting LLM-Generated RTL Copyright via a Hardware Watermarking Framework. ASP-DAC Kun Wang, Kaiyan Chang, Mengdi Wang, Xingqi Zou, Haobo Xu, Yinhe Han, Ying Wang
2025	J	`jnl`	RTLMarker: Protecting LLM-Generated RTL Copyright via a Hardware Watermarking Framework. CoRR Kun Wang, Kaiyan Chang, Mengdi Wang, Xinqi Zou, Haobo Xu, Yinhe Han, Ying Wang
2024	A*	`conf`	Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework. DAC Kaiyan Chang, Kun Wang, Nan Yang, Ying Wang, Dantong Jin, Wenlong Zhu, Zhirong Chen, Cangyuan Li, Hao Yan, Yunhao Zhou, Zhuoliang Zhao, Yuan Cheng, Yudong Pan, Yiqi Liu, Mengdi Wang, Shengwen Liang, Yinhe Han, Huawei Li, Xiaowei Li
2024	J	`jnl`	Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework. CoRR Kaiyan Chang, Kun Wang, Nan Yang, Ying Wang, Dantong Jin, Wenlong Zhu, Zhirong Chen, Cangyuan Li, Hao Yan, Yunhao Zhou, Zhuoliang Zhao, Yuan Cheng, Yudong Pan, Yiqi Liu, Mengdi Wang, Shengwen Liang, Yinhe Han, Huawei Li, Xiaowei Li
2024	A	`conf`	Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation. ICCAD Kaiyan Chang, Zhirong Chen, Yunhao Zhou, Wenlong Zhu, Kun Wang, Haobo Xu, Cangyuan Li, Mengdi Wang, Shengwen Liang, Huawei Li, Yinhe Han, Ying Wang
2024	J	`jnl`	Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation. CoRR Kaiyan Chang, Zhirong Chen, Yunhao Zhou, Wenlong Zhu, Kun Wang, Haobo Xu, Cangyuan Li, Mengdi Wang, Shengwen Liang, Huawei Li, Yinhe Han, Ying Wang
2023	J	`jnl`	ChipGPT: How far are we from natural language hardware design. CoRR Kaiyan Chang, Ying Wang, Haimeng Ren, Mengdi Wang, Shengwen Liang, Yinhe Han, Huawei Li, Xiaowei Li
2023	A	`conf`	Full State Quantum Circuit Simulation Beyond Memory Limit. ICCAD Yilun Zhao, Yu Chen, He Li, Ying Wang, Kaiyan Chang, Bingmeng Wang, Bing Li, Yinhe Han
2021	J	`jnl`	ArchNet: A data hiding design for distributed machine learning systems. J. Syst. Archit. Kaiyan Chang, Wei Jiang, Jinyu Zhan, Zicheng Gong, Weijia Pan
2020	J	`jnl`	ArchNet: Data Hiding Model in Distributed Machine Learning System. CoRR Kaiyan Chang, Wei Jiang, Zicheng Gong, Xiangyu Wen, Zhiyuan He, Weijia Pan