Kailash Chandrashekar

16 papers A 1C 1Journal 6Unranked 8

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	A Synchronous 13.1 GHz Backside Resonant Clocking Mesh Implemented on a Graphics Core in an 18A Class Technology. IEEE Solid State Circuits Lett. Ragh Kuttappa, Vinayak Honkote, Amreesh Rao, Gaurav Kamalkar, Kailash Chandrashekar, Eric Finley, Chaitanya Sankuratri, Faran Rafiq, Robert Orton, Nils Hernandez, Anuradha Srinivasan, Tanay Karnik
2021	J	`jnl`	A Self-Calibrated 2-bit Time-Period Comparator-Based Synthesized Fractional-N MDLL in 22-nm FinFET CMOS. IEEE J. Solid State Circuits Somnath Kundu, Likai Chai, Kailash Chandrashekar, Stefano Pellerano, Brent R. Carlton
2020	—	`conf`	25.5 A Self-Calibrated 1.2-to-3.8GHz 0.0052mm2 Synthesized Fractional-N MDLL Using a 2b Time-Period Comparator in 22nm FinFET CMOS. ISSCC Somnath Kundu, Likai Chai, Kailash Chandrashekar, Stefano Pellerano, Brent R. Carlton
2020	C	`conf`	Transformer-Combining Digital PA with Efficiency Peaking at 0, -6, and -12 dB Backoff in 32nm CMOS. ISCAS Parmoon Seddighrad, Yorgos Palaskas, Hongtao Xu, Paolo Madoglio, Kailash Chandrashekar, David J. Allstot
2017	—	`conf`	13.6 A 2.4GHz WLAN digital polar transmitter with synthesized digital-to-time converter in 14nm trigate/FinFET technology for IoT and wearable applications. ISSCC Paolo Madoglio, Hongtao Xu, Kailash Chandrashekar, Luis Cuellar, Muhammad Faisal, Yee William Li, Hyung Seok Kim, Khoa Minh Nguyen, Yulin Tan, Brent R. Carlton, Vaibhav A. Vaidya, Yanjie Wang, Thomas Tetzlaff, Satoshi Suzuki, Amr Fahim, Parmoon Seddighrad, Jianyong Xie, Zhichao Zhang, Divya Shree Vemparala, Ashoke Ravi, Stefano Pellerano, Yorgos Palaskas
2017	A	`conf`	A 32nm, 0.65-10GHz, 0.9/0.3 ps/σ TX/RX jitter single inductor digital fractional-n clock generator for reconfigurable serial I/O. ISLPED William Y. Li, Hyung Seok Kim, Kailash Chandrashekar, Khoa Minh Nguyen, Ashoke Ravi
2013	J	`jnl`	A Digital Fractional-N PLL With a PVT and Mismatch Insensitive TDC Utilizing Equivalent Time Sampling Technique. IEEE J. Solid State Circuits Hyung Seok Kim, Carlos Ornelas, Kailash Chandrashekar, Dan Shi, Pin-En Su, Paolo Madoglio, Yee William Li, Ashoke Ravi
2012	J	`jnl`	A 2.4-GHz 20-40-MHz Channel WLAN Digital Outphasing Transmitter Utilizing a Delay-Based Wideband Phase Modulator in 32-nm CMOS. IEEE J. Solid State Circuits Ashoke Ravi, Paolo Madoglio, Hongtao Xu, Kailash Chandrashekar, Marian Verhelst, Stefano Pellerano, Luis Cuellar, Mariano Aguirre-Hernandez, Masoud Sajadieh, J. E. Zarate-Roldan, Ofir Bochobza-Degani, Hasnain Lakdawala, Yorgos Palaskas
2012	—	`conf`	A 2.4GHz WLAN transceiver with fully-integrated highly-linear 1.8V 28.4dBm PA, 34dBm T/R switch, 240MS/s DAC, 320MS/s ADC, and DPLL in 32nm SoC CMOS. VLSIC Yulin Tan, Jon Duster, Chang-Tsung Fu, Erkan Alpman, Ajay Balankutty, Chun C. Lee, Ashoke Ravi, Stefano Pellerano, Kailash Chandrashekar, Hyung Seok Kim, Brent R. Carlton, Satoshi Suzuki, M. Shafi, Yorgos Palaskas, Hasnain Lakdawala
2012	—	`conf`	A 20dBm 2.4GHz digital outphasing transmitter for WLAN application in 32nm CMOS. ISSCC Paolo Madoglio, Ashoke Ravi, Hongtao Xu, Kailash Chandrashekar, Marian Verhelst, Stefano Pellerano, Luis Cuellar, Mariano Aguirre, Masoud Sajadieh, Ofir B. Degani, Hasnain Lakdawala, Yorgos Palaskas
2012	—	`conf`	A 32nm CMOS all-digital reconfigurable fractional frequency divider for LO generation in multistandard SoC radios with on-the-fly interference management. ISSCC Kailash Chandrashekar, Stefano Pellerano, Paolo Madoglio, Ashoke Ravi, Yorgos Palaskas
2012	—	`conf`	A digital fractional-N PLL with a 3mW 0.004mm ESSCIRC Hyung Seok Kim, Carlos Ornelas, Kailash Chandrashekar, Pin-En Su, Paolo Madoglio, Yee William Li, Ashoke Ravi
2011	J	`jnl`	A 10 b 50 MS/s Opamp-Sharing Pipeline A/D With Current-Reuse OTAs. IEEE Trans. Very Large Scale Integr. Syst. Kailash Chandrashekar, Bertan Bakkaloglu
2010	J	`jnl`	A 20-MS/s to 40-MS/s Reconfigurable Pipeline ADC Implemented With Parallel OTA Scaling. IEEE Trans. Circuits Syst. II Express Briefs Kailash Chandrashekar, Marco Corsi, John W. Fattaruso, Bertan Bakkaloglu
2009	—	`conf`	A 10b 50MS/s opamp-sharing pipeline A/D with current-reuse OTAs. CICC Kailash Chandrashekar, Bertan Bakkaloglu
2008	—	`conf`	A fully integrated pulsed-LASER time-of-flight measurement system with 12ps single-shot precision. CICC Tino Copani, Bert Vermeire, Anuj Jain, Habib Karaki, Kailash Chandrashekar, Sushmit Goswami, Jennifer Kitchen, Hoon Hee Chung, Ilker Deligoz, Bertan Bakkaloglu, Hugh J. Barnaby, Sayfe Kiaei