Kailash Chandra Ray

50 papers C 1Journal 38Unranked 11
YearRankTypeTitle / Venue / Authors
2026 J jnl
An energy-efficient adaptive two stage pipeline RISC-V based soft-processor for edge-computing applications.
Int. J. Parallel Emergent Distributed Syst.
Sujeet Kumar, Kailash Chandra Ray
2026 J jnl
FCMFID: A Full Coverage Multi-bit Fault-Tolerant Instruction Decoder for RISC-V based softcore.
Integr.
Sujeet Kumar, Kailash Chandra Ray
2026 J jnl
Micro-Architecture of LW Driven Bubble-Free Five-Stage Pipelined RISC-V Processor Core for Energy Constraint Low-End Application.
IEEE Trans. Circuits Syst. I Regul. Pap.
Sujeet Kumar, Kailash Chandra Ray
2025 J jnl
A Parity-based Multi-bit Fault-Tolerant Instruction Decoder for RISC-V pipelined soft processor.
Integr.
Sujeet Kumar, Kailash Chandra Ray
2025 J jnl
An Efficient Method for Detection and Localization of Myocardial Infarction Using Ramanujan Sums Wavelet Transform and Machine Learning Framework.
IEEE Trans. Instrum. Meas.
Akanksha Gupta, Kailash Chandra Ray
2024 J jnl
An Efficient Method and Hardware System for Monitoring of Illegal Logging Events in Forest.
IEEE Syst. J.
Vivek Singh, Kailash Chandra Ray, Somanath Tripathy
2023 J jnl
An Efficient Fault-Tolerant Instruction Decoder for RISC-V Based Dual-Core Soft-Processors.
IEEE Trans. Circuits Syst. I Regul. Pap.
Satyam Shukla, Utkarsh, Md Azam, Kailash Chandra Ray
2023 J jnl
An energy-efficient single-cycle RV32I microprocessor for edge computing applications.
Integr.
Satyam Shukla, Punyesh Kumar Jha, Kailash Chandra Ray
2023 J jnl
VLSI Architecture of DCT-Based Harmonic Wavelet Transform for Time-Frequency Analysis.
IEEE Trans. Instrum. Meas.
Pritiranjan Khatua, Kailash Chandra Ray
2023 J jnl
VLSI Architecture of Modified Complex Harmonic Wavelet Transform.
Circuits Syst. Signal Process.
Pritiranjan Khatua, Kailash Chandra Ray
2022 J jnl
A Low Computational Complexity Modified Complex Harmonic Wavelet Transform.
Circuits Syst. Signal Process.
Pritiranjan Khatua, Kailash Chandra Ray
2022 J jnl
A Low-Overhead Reconfigurable RISC-V Quad-Core Processor Architecture for Fault-Tolerant Applications.
IEEE Access
Satyam Shukla, Kailash Chandra Ray
2022 J jnl
An Efficient DCT-II Based Harmonic Wavelet Transform for Time-Frequency Analysis.
J. Signal Process. Syst.
Pritiranjan Khatua, Kailash Chandra Ray
2022 J jnl
An Efficient Method for Detection and Localization of Myocardial Infarction.
IEEE Trans. Instrum. Meas.
Garima Sahu, Kailash Chandra Ray
2022 — conf
An Efficient Signal Processing Technique for Automated Cardiovascular Disease Detection.
iSES
Garima Sahu, Akanksha Gupta, Kailash Chandra Ray
2021 J jnl
ASIC Implementation of Low PAPR Multidevice Variable-Rate Architecture for IEEE 802.11ah.
IEEE Trans. Instrum. Meas.
Rakesh Palisetty, Amit Kumar Panda, Kailash Chandra Ray
2020 J jnl
A Coupled Variable Input LCG Method and its VLSI Architecture for Pseudorandom Bit Generation.
IEEE Trans. Instrum. Meas.
Amit Kumar Panda, Kailash Chandra Ray
2020 J jnl
High-Speed Area-Efficient VLSI Architecture of Three-Operand Binary Adder.
IEEE Trans. Circuits Syst.
Amit Kumar Panda, Rakesh Palisetty, Kailash Chandra Ray
2020 J jnl
Multiuser Variable Rate GO-OFDMA Architecture and Its FPGA Prototype.
IEEE Syst. J.
Rakesh Palisetty, Kailash Chandra Ray
2019 — conf
A Basis Function for DCT Based Discrete Orthogonal S-Transform.
iSES
Pritiranjan Khatua, Kailash Chandra Ray
2019 — conf
An Efficient Signal Processing Technique for Automated Myocardial Infarction Detection.
iSES
Garima Sahu, Kailash Chandra Ray
2019 — conf
Area-Efficient Parallel-Prefix Binary Comparator.
iSES
Amit Kumar Panda, Rakesh Palisetty, Kailash Chandra Ray
2019 — conf
Blind Detection and Classification Algorithm for Smart Audio Monitoring System.
iSES
Vivek Singh, Kailash Chandra Ray, Somanath Tripathy
2019 J jnl
CORDIC-Based VLSI Architectures of Running DFT with Refreshing Mechanism.
J. Signal Process. Syst.
Kailash Chandra Ray, Anindya Sundar Dhar
2019 — conf
Design and ASIC Implementation of a Reconfigurable Fault-Tolerant ALU for Space Applications.
iSES
Satyam Shukla, Kailash Chandra Ray
2019 J jnl
Modified Dual-CLCG Method and its VLSI Architecture for Pseudorandom Bit Generation.
IEEE Trans. Circuits Syst. I Regul. Pap.
Amit Kumar Panda, Kailash Chandra Ray
2019 J jnl
Performance Analysis and FPGA Prototype of Variable Rate GO-OFDMA Baseband Transmission Scheme.
Wirel. Pers. Commun.
Akash Agarwal, Vibhooti Kumar Sinha, Rakesh Palisetty, Preetam Kumar, Kailash Chandra Ray, Kamlesh Kumar, Tulika Pandey
2018 J jnl
A Personalized Point-of-Care Platform for Real-Time ECG Monitoring.
IEEE Trans. Consumer Electron.
Sandeep Raj, Kailash Chandra Ray
2018 J jnl
An Efficient VLSI Architecture for Computation of Discrete Fractional Fourier Transform.
J. Signal Process. Syst.
Kailash Chandra Ray, M. V. N. V. Prasad, Anindya Sundar Dhar
2018 J jnl
Automated recognition of cardiac arrhythmias using sparse decomposition over composite dictionary.
Comput. Methods Programs Biomed.
Sandeep Raj, Kailash Chandra Ray
2018 J jnl
FPGA Prototype and Real Time Analysis of Multiuser Variable Rate CI-GO-OFDMA.
IEEE Trans. Instrum. Meas.
Rakesh Palisetty, Kailash Chandra Ray
2018 J jnl
Sparse representation of ECG signals for automated recognition of cardiac arrhythmias.
Expert Syst. Appl.
Sandeep Raj, Kailash Chandra Ray
2017 J jnl
A VLSI architecture of CORDIC-based popular windows and its FPGA prototype.
Int. J. High Perform. Syst. Archit.
Vikas Kumar, Kailash Chandra Ray, Preetam Kumar
2017 — conf
Application of variational mode decomposition and ABC optimized DAG-SVM in arrhythmia analysis.
ISED
Sandeep Raj, Kailash Chandra Ray
2017 J jnl
ECG Signal Analysis Using DCT-Based DOST and PSO Optimized SVM.
IEEE Trans. Instrum. Meas.
Sandeep Raj, Kailash Chandra Ray
2017 — conf
Single cycle RISC-V micro architecture processor and its FPGA prototype.
ISED
Don Kurian Dennis, Ayushi Priyam, Sukhpreet Singh Virk, Sajal Agrawal, Tanuj Sharma, Arijit Mondal, Kailash Chandra Ray
2016 J jnl
Cardiac arrhythmia beat classification using DOST and PSO tuned SVM.
Comput. Methods Programs Biomed.
Sandeep Raj, Kailash Chandra Ray, Om Shankar
2016 J jnl
Dynamic Hash key-based stream cipher for secure transmission of real time ECG signal.
Secur. Commun. Networks
K. K. Soundra Pandian, Kailash Chandra Ray
2016 J jnl
Efficient methodology for electrocardiogram beat classification.
IET Signal Process.
Piyush Sharma, Kailash Chandra Ray
2015 J jnl
ARM-based arrhythmia beat monitoring system.
Microprocess. Microsystems
Sandeep Raj, G. S. S. Praveen Chand, Kailash Chandra Ray
2015 — conf
Design and Implementation of Quadruple Floating-Point CORDIC.
iNIS
Arun Kumar Singh, Madhav Kumar Singh, Kailash Chandra Ray
2015 — conf
FPGA Prototype of Low Latency BBS PRNG.
iNIS
Amit Kumar Panda, Kailash Chandra Ray
2015 J jnl
Five decade evolution of feedback shift register: algorithms, architectures and applications.
Int. J. Commun. Networks Distributed Syst.
K. K. Soundra Pandian, Kailash Chandra Ray
2015 J jnl
Non-singular sequence folding-based pseudorandom key generation algorithm for cryptographic processor.
Secur. Commun. Networks
K. K. Soundra Pandian, Kailash Chandra Ray
2014 J jnl
CORDIC-Based VLSI Architecture for Implementing Kaiser-Bessel Window in Real Time Spectral Analysis.
J. Signal Process. Syst.
Kailash Chandra Ray, Anindya Sundar Dhar
2014 J jnl
CORDIC-based VLSI architecture for real time implementation of flat top window.
Microprocess. Microsystems
Vikas Kumar, Kailash Chandra Ray, Preetam Kumar
2014 — conf
FPGA implementation of stream cipher using Toeplitz Hash function.
ICACCI
Saptadeep Pal, K. K. Soundra Pandian, Kailash Chandra Ray
2014 J jnl
Low Latency Hybrid CORDIC Algorithm.
IEEE Trans. Computers
Rohit Shukla, Kailash Chandra Ray
2011 C conf
Hardware efficient design of Variable Length FFT Processor.
DDECS
Vinay Gautam, Kailash Chandra Ray, Pauline C. Haddow
2008 J jnl
High Throughput VLSI Architecture for Blackman Windowing in Real Time Spectral Analysis.
J. Comput.
Kailash Chandra Ray, A. S. Dhar