Kaijie Wei

21 papers Journal 5Unranked 16
YearRankTypeTitle / Venue / Authors
2025 — conf
FP-FBEMS: FPGA-Based Optimization of Forward/Backward EMS Decoding for CV-QKD.
MCSoC
Kaijie Wei, Devanshu Garg, Ryutaro Nagai, Takao Tomono, Hideharu Amano
2025 — conf
FPT-EMS: An FPGA Implementation Using NB-LDPC Code for Continuous-Variable Quantum Key Distribution.
HEART
Kaijie Wei, Devanshu Garg, Ryutaro Nagai, Takao Tomono, Hideharu Amano
2025 J jnl
Qu-Trefoil: Large-Scale Quantum Circuit Simulator Working on FPGA With SATA Storages.
IEEE Trans. Computers
Kaijie Wei, Hideharu Amano, Ryohei Niwase, Yoshiki Yamaguchi, Takefumi Miyoshi
2024 — conf
A data compressor for FPGA-based state vector quantum simulators.
HEART
Kaijie Wei, Hideharu Amano, Ryohei Niwase, Yoshiki Yamaguchi
2023 — conf
A cost/power efficient storage system with directly connected FPGA and SATA disks.
MCSoC
Ryohei Niwase, Hikaru Harasawa, Yoshiki Yamaguchi, Kaijie Wei, Hideharu Amano
2023 — conf
A state vector quantum simulator working on FPGAs with extensible SATA storage.
ICFPT
Kaijie Wei, Ryohei Niwase, Hideharu Amano, Yoshiki Yamaguchi, Takefumi Miyoshi
2023 — conf
Enormous-Scale Quantum State Vector Calculation with FPGA-accelerated SATA storages.
ICFPT
Ryohei Niwase, Hikaru Harasawa, Yoshiki Yamaguchi, Kaijie Wei, Hideharu Amano, Takefumi Miyoshi
2023 — conf
Low power implementation of Geometric High-order Decorrelation-based Source Separation on an FPGA board.
COOL CHIPS
Ziquan Qin, Kaijie Wei, Hideharu Amano, Kazuhiro Nakadai
2023 J jnl
RT-libSGM: FPGA-Oriented Real-Time Stereo Matching System with High Scalability.
IEICE Trans. Inf. Syst.
Kaijie Wei, Yuki Kuno, Masatoshi Arai, Hideharu Amano
2022 — conf
An FPGA off-loading of HARK sound source localization.
CANDARW
Zhongyang Hou, Kaijie Wei, Hideharu Amano, Kazuhiro Nakadai
2022 — conf
An Implementation of a 3D Image Filter for Motion Vector Generation on an FPGA Board.
CANDAR
Yuchen Chen, Kaijie Wei, Hiroaki Nishi, Hideharu Amano
2022 — conf
Multi-board FPGA Implementation to Solve the Satisfiability Problem for Multi-Agent Path Finding in Smart Factory.
CANDARW
Pengyu Huang, Kaijie Wei, Hideharu Amano, Kaori Ohkoda, Masashi Aono
2022 — conf
RT-libSGM: An Implementation of a Real-time Stereo Matching System on FPGA.
HEART
Kaijie Wei, Yuki Kuno, Masatoshi Arai, Hideharu Amano
2022 J jnl
Weighted Least Square Filter for Improving the Quality of Depth Map on FPGA.
Int. J. Netw. Comput.
Renzhi Mao, Kaijie Wei, Hideharu Amano, Yuki Kuno, Masatoshi Arai
2021 J jnl
An implementation methodology for Neural Network on a Low-end FPGA Board.
Int. J. Netw. Comput.
Kaijie Wei, Koki Honda, Hideharu Amano
2021 J jnl
CLAHE Implementation and Evaluation on a Low-End FPGA Board by High-Level Synthesis.
IEICE Trans. Inf. Syst.
Koki Honda, Kaijie Wei, Masatoshi Arai, Hideharu Amano
2021 — conf
Weight Least Square Filter for Improving the Quality of Depth Map on FPGA.
CANDAR (Workshops)
Renzhi Mao, Kaijie Wei, Hideharu Amano, Yuki Kuno, Masatoshi Arai
2020 — conf
An implementation methodology for Neural Network on a Low-end FPGA Board.
CANDAR
Kaijie Wei, Koki Honda, Hideharu Amano
2020 — conf
CLAHE implementation on a low-end FPGA board by high-level synthesis.
CANDAR (Workshops)
Koki Honda, Kaijie Wei, Masatoshi Arai, Hideharu Amano
2019 — conf
FPGA/Python Co-Design for Lane Line Detection on a PYNQ-Z1 Board.
MCSoC
Koki Honda, Kaijie Wei, Hideharu Amano
2018 — conf
FPGA Design for Autonomous Vehicle Driving Using Binarized Neural Networks.
FPT
Kaijie Wei, Koki Honda, Hideharu Amano