Kai Zhu - RankMe

14 papers A* 2A 5C 1Journal 5Unranked 1

Year	Rank	Type	Title / Venue / Authors
2007	A	`conf`	Post-route LUT output polarity selection for timing optimization. FPGA Kai Zhu
2003	J	`jnl`	Analysis of FPGA/FPIC switch modules. ACM Trans. Design Autom. Electr. Syst. Yao-Wen Chang, Kai Zhu, Guang-Ming Wu, D. F. Wong, C. K. Wong
2000	J	`jnl`	FPGA Partitioning with Complex Resource Constraints. VLSI Design Huiqun Liu, Kai Zhu, D. F. Wong
2000	J	`jnl`	Timing-driven routing for symmetrical array-based FPGAs. ACM Trans. Design Autom. Electr. Syst. Yao-Wen Chang, Kai Zhu, D. F. Wong
1998	A	`conf`	Circuit Partitioning with Complex Resource Constraints in FPGAs. FPGA Huiqun Liu, Kai Zhu, D. F. Wong
1998	J	`jnl`	Switch bound allocation for maximizing routability in timing-driven routing of FPGA's. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kai Zhu, Martin D. F. Wong
1998	C	`conf`	Timing-driven routing for symmetrical-array-based FPGAs. ICCD Kai Zhu, Yao-Wen Chang, D. F. Wong
1997	J	`jnl`	Clock skew minimization during FPGA placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kai Zhu, Martin D. F. Wong
1994	A	`conf`	A new global routing algorithm for FPGAs. ICCAD Yao-Wen Chang, Shashidhar Thakur, Kai Zhu, D. F. Wong
1994	A*	`conf`	Clock Skew Minimization During FPGA Placement. DAC Kai Zhu, D. F. Wong
1994	A*	`conf`	Switch Bound Allocation for Maximizing Routability in Timing-Driven Routing of FPGAs. DAC Kai Zhu, D. F. Wong
1993	—	`conf`	Fast Boolean matching for field-programmable gate arrays. EURO-DAC Kai Zhu, D. F. Wong
1993	A	`conf`	Switch module design with application to two-dimensional segmentation design. ICCAD Kai Zhu, D. F. Wong, Yao-Wen Chang
1992	A	`conf`	On channel segmentation design for row-based FPGAs. ICCAD Kai Zhu, D. F. Wong

Nicolò Altamura, Enrico Bragastini, Marco Campion, Mila Dalla Preda

Chang Liu, Noah Fleischmann, Nicolò Altamura, Edward Raff, James Holt, Kristopher Micinski