Kai Wang

11 papers A* 3A 2C 1Journal 3Unranked 2
YearRankTypeTitle / Venue / Authors
2005 — conf
Clock skew bounds estimation under power supply and process variations.
ACM Great Lakes Symposium on VLSI
Hailin Jiang, Kai Wang, Malgorzata Marek-Sadowska
2005 J jnl
General skew constrained clock network sizing based on sequential linear programming.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kai Wang, Yajun Ran, Hailin Jiang, Malgorzata Marek-Sadowska
2005 J jnl
On-chip power-supply network optimization using multigrid-based technique.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kai Wang, Malgorzata Marek-Sadowska
2004 A* conf
Buffer sizing for clock power minimization subject to general skew constraints.
DAC
Kai Wang, Malgorzata Marek-Sadowska
2004 — conf
Clock network sizing via sequential linear programming with time-domain analysis.
ISPD
Kai Wang, Malgorzata Marek-Sadowska
2004 J jnl
Fast postplacement optimization using functional symmetries.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chih-Wei Jim Chang, Ming-Fu Hsiao, Bo Hu, Kai Wang, Malgorzata Marek-Sadowska, Chung-Kuan Cheng, Sao-Jie Chen
2004 C conf
Potential Slack Budgeting with Clock Skew Optimization.
ICCD
Kai Wang, Malgorzata Marek-Sadowska
2003 A* conf
On-chip power supply network optimization using multigrid-based technique.
DAC
Kai Wang, Malgorzata Marek-Sadowska
2003 A conf
Power/Ground Mesh Area Optimization Using Multigrid-Based Technique.
DATE
Kai Wang, Malgorzata Marek-Sadowska
2002 A conf
Sizing Power/Ground Meshes for Clocking and Computing Circuit Components.
DATE
Arindam Mukherjee, Kai Wang, Lauren Hui Chen, Malgorzata Marek-Sadowska
2001 A* conf
Layout-Driven Hot-Carrier Degradation Minimization Using Logic Restructuring Techniques.
DAC
Chih-Wei Jim Chang, Kai Wang, Malgorzata Marek-Sadowska