Kai Li

23 papers A 5Misc 1Journal 11Unranked 6
YearRankTypeTitle / Venue / Authors
2025 A conf
A 20.98TOPS/W Energy-Efficient Binary BERT Model on Group Vector Systolic CIM Accelerator.
ISLPED
Dingbang Liu, Ziyi Guan, Qilong Chen, Jingyun Gu, Jiaqi Yang, Kai Li, Wei Mao, Ngai Wong, Changwen Chen, Hao Yu
2025 J jnl
A 28-nm 135.19 TOPS/W Bootstrapped-SRAM Compute-in-Memory Accelerator With Layer-Wise Precision and Sparsity.
IEEE Trans. Circuits Syst. I Regul. Pap.
Wei Mao, Dingbang Liu, Haoxiang Zhou, Fuyi Li, Kai Li, Qiuping Wu, Jiaqi Yang, Quan Cheng, Liuyang Zhang, Hao Yu
2025 J jnl
A 29.12-TOPS/W Vector Systolic Accelerator With NAS-Optimized DNNs in 28-nm CMOS.
IEEE J. Solid State Circuits
Kai Li, Mingqiang Huang, Ang Li, Shuxin Yang, Quan Cheng, Hao Yu
2025 J jnl
A Tensor-Train Decomposition based Compression of LLMs on Group Vector Systolic Accelerator.
CoRR
Sixiao Huang, Tintin Wang, Ang Li, Ao Shen, Kai Li, Keyao Jiang, Mingqiang Huang, Hao Yu
2025 — conf
An MLA-LLM Hardware Acceleration with Tensor-Train Decomposition on Group Vector Systolic Accelerator.
ASAP
Sixiao Huang, Tintin Wang, Keyao Jiang, Ao Shen, Kai Li, Ang Li, Mingqiang Huang, Hao Yu
2025 J jnl
EdgeLLM: A Highly Efficient CPU-FPGA Heterogeneous Edge Accelerator for Large Language Models.
IEEE Trans. Circuits Syst. I Regul. Pap.
Mingqiang Huang, Ao Shen, Kai Li, Haoxiang Peng, Boyu Li, Yupeng Su, Hao Yu
2024 — conf
A 29.12 TOPS/W and 1.13 TOPS/mm2 NAS-Optimized Mixed-Precision DNN Accelerator with Vector Split- and-Combination Systolic in 28nm CMOS.
CICC
Kai Li, Hantao Huang, Mingqiang Huang, Chenchen Ding, Longyang Lin, Liebing Ni, Hao Yu
2024 J jnl
A Low-Power DNN Accelerator With Mean-Error-Minimized Approximate Signed Multiplier.
IEEE Open J. Circuits Syst.
Laimin Du, Leibin Ni, Xiong Liu, Guanqi Peng, Kai Li, Wei Mao, Hao Yu
2024 J jnl
A Reconfigurable Processing Element for Multiple-Precision Floating/Fixed-Point HPC.
IEEE Trans. Circuits Syst. II Express Briefs
Boyu Li, Kai Li, Jiajun Zhou, Yuan Ren, Wei Mao, Hao Yu, Ngai Wong
2024 J jnl
EdgeLLM: A Highly Efficient CPU-FPGA Heterogeneous Edge Accelerator for Large Language Models.
CoRR
Mingqiang Huang, Ao Shen, Kai Li, Haoxiang Peng, Boyu Li, Hao Yu
2024 Misc conf
LAMPS: A Layer-wised Mixed-Precision-and-Sparsity Accelerator for NAS-Optimized CNNs on FPGA.
FCCM
Shuxin Yang, Chenchen Ding, Mingqiang Huang, Kai Li, Chenghao Li, Zikun Wei, Sixiao Huang, Jingyao Dong, Liuyang Zhang, Hao Yu
2023 A conf
Multi-bit-width CNN Accelerator with Systolic-in-Systolic Dataflow and Single DSP Multiple Multiplication Scheme.
FPGA
Mingqiang Huang, Yucen Liu, Sixiao Huang, Kai Li, Qiuping Wu, Hao Yu
2023 — conf
RISC-V based Fully-Parallel SRAM Computing-in-Memory Accelerator with High Hardware Utilization and Data Reuse Rate.
AICAS
Haoxiang Zhou, Haiqiao Hong, Dingbang Liu, Hang Liu, Yu Xia, Kai Li, Jun Liu, Shaobo Luo, Wei Mao, Hao Yu
2022 J jnl
A Configurable Floating-Point Multiple-Precision Processing Element for HPC and AI Converged Computing.
IEEE Trans. Very Large Scale Integr. Syst.
Wei Mao, Kai Li, Quan Cheng, Liuyao Dai, Boyu Li, Xinang Xie, He Li, Longyang Lin, Hao Yu
2022 J jnl
A High Performance Multi-Bit-Width Booth Vector Systolic Accelerator for NAS Optimized Deep Learning Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap.
Mingqiang Huang, Yucen Liu, Changhai Man, Kai Li, Quan Cheng, Wei Mao, Hao Yu
2022 A conf
A High Throughput Multi-bit-width 3D Systolic Accelerator for NAS Optimized Deep Neural Networks on FPGA.
FPGA
Mingqiang Huang, Yucen Liu, Quan Cheng, Shuxin Yang, Kai Li, Junyi Luo, Zhengke Yang, Qiufeng Li, Hao Yu, Changhai Man
2022 A conf
A Precision-Scalable Energy-Efficient Bit-Split-and-Combination Vector Systolic Accelerator for NAS-Optimized DNNs on Edge.
DATE
Kai Li, Junzhuo Zhou, Yuhang Wang, Junyi Luo, Zhengke Yang, Shuxin Yang, Wei Mao, Mingqiang Huang, Hao Yu
2022 — conf
A Vector Systolic Accelerator for Multi-Precision Floating-Point High-Performance Computing.
AICAS
Kai Li, Junzhuo Zhou, Boyu Li, Shuxing Yang, Sixiao Huang, Shaobo Luo, Wei Mao, Hao Yu
2022 J jnl
A Vector Systolic Accelerator for Multi-Precision Floating-Point High-Performance Computing.
IEEE Trans. Circuits Syst. II Express Briefs
Kai Li, Wei Mao, Junzhuo Zhou, Boyu Li, Zhengke Yang, Shuxing Yang, Laimin Du, Sixiao Huang, Hao Yu
2022 — conf
An Energy-Efficient Bit-Split-and-Combination Systolic Accelerator for NAS-Based Multi-Precision Convolution Neural Networks.
ASP-DAC
Liuyao Dai, Quan Cheng, Yuhang Wang, Gengbin Huang, Junzhuo Zhou, Kai Li, Wei Mao, Hao Yu
2022 J jnl
An Energy-Efficient Mixed-Bitwidth Systolic Accelerator for NAS-Optimized Deep Neural Networks.
IEEE Trans. Very Large Scale Integr. Syst.
Wei Mao, Liuyao Dai, Kai Li, Quan Cheng, Yuhang Wang, Laimin Du, Shaobo Luo, Mingqiang Huang, Hao Yu
2021 A conf
A Reconfigurable Multiple-Precision Floating-Point Dot Product Unit for High-Performance Computing.
DATE
Wei Mao, Kai Li, Xinang Xie, Shirui Zhao, He Li, Hao Yu
2021 — conf
Multiple-Precision Floating-Point Dot Product Unit for Efficient Convolution Computation.
AICAS
Kai Li, Wei Mao, Xinang Xie, Quan Cheng, Huan Xie, Zhenjiang Dong, Hao Yu