Kai-Yuan Chao

45 papers A* 3A 9C 3Journal 12Unranked 18
YearRankTypeTitle / Venue / Authors
2026 J jnl
Multilayer Package Power/Ground Planes Synthesis With Balanced DC IR Drops: A Game-Theoretic Optimization Approach.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Siyuan Liang, Zhen Zhuang, Kai-Yuan Chao, Bei Yu, Tsung-Yi Ho
2025 J jnl
Hierarchical Partitioning-Based Interchip Redistribution Layer Routing for Fan-Out Wafer-Level Packaging.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Haoyang Xu, Xing Huang, Zhen Zhuang, Zhiwen Yu, Bin Guo, Kai-Yuan Chao, Bei Yu, Tsung-Yi Ho, Martin D. F. Wong
2024 A* conf
Lesyn: Placement-aware Logic Resynthesis for Non-Integer Multiple-Cell-Height Designs.
DAC
Yuan Pu, Fangzhou Liu, Yu Zhang, Zhuolun He, Yibo Lin, Kai-Yuan Chao, Bei Yu
2024 — conf
Multi-Electrostatics Based Placement for Non-Integer Multiple-Height Cells.
ISPD
Yu Zhang, Yuan Pu, Fangzhou Liu, Peiyu Liao, Kai-Yuan Chao, Keren Zhu, Yibo Lin, Bei Yu
2023 A conf
Multi-Product Optimization for 3D Heterogeneous Integration with D2W Bonding.
ICCAD
Zhen Zhuang, Kai-Yuan Chao, Bei Yu, Tsung-Yi Ho, Martin D. F. Wong
2022 A conf
Multi-Package Co-Design for Chiplet Integration.
ICCAD
Zhen Zhuang, Bei Yu, Kai-Yuan Chao, Tsung-Yi Ho
2022 J jnl
Timing-Aware Layer Assignment for Advanced Process Technologies Considering via Pillars.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Genggeng Liu, Xinghai Zhang, Wenzhong Guo, Xing Huang, Wen-Hao Liu, Kai-Yuan Chao, Ting-Chi Wang
2017 — conf
Delay-driven layer assignment for advanced technology nodes.
ASP-DAC
Szu-Yuan Han, Wen-Hao Liu, Rickard Ewetz, Cheng-Kok Koh, Kai-Yuan Chao, Ting-Chi Wang
2014 — conf
A study on the use of parallel wiring techniques for sub-20nm designs.
ACM Great Lakes Symposium on VLSI
Rickard Ewetz, Wen-Hao Liu, Kai-Yuan Chao, Ting-Chi Wang, Cheng-Kok Koh
2013 J jnl
NCTU-GR 2.0: Multithreaded Collision-Aware Global Routing With Bounded-Length Maze Routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wen-Hao Liu, Wei-Chun Kao, Yih-Lang Li, Kai-Yuan Chao
2013 — conf
Symmetrical buffered clock-tree synthesis with supply-voltage alignment.
ASP-DAC
Xin-Wei Shih, Tzu-Hsuan Hsu, Hsu-Chieh Lee, Yao-Wen Chang, Kai-Yuan Chao
2012 J jnl
A Practical Low-Power Nonregular Interconnect Design With Manufacturing for Design Approach.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Hongbo Zhang, Martin D. F. Wong, Kai-Yuan Chao, Liang Deng
2012 — conf
Hybrid lithography optimization with E-Beam and immersion processes for 16nm 1D gridded design.
ASP-DAC
Yuelin Du, Hongbo Zhang, Martin D. F. Wong, Kai-Yuan Chao
2012 A conf
Scaling the "Memory Wall": Designer track.
ICCAD
Shih-Lien Lu, Tanay Karnik, Ganapati Srinivasa, Kai-Yuan Chao, Doug Carmean, Jim Held
2011 A conf
High-quality global routing for multiple dynamic supply voltage designs.
ICCAD
Wen-Hao Liu, Yih-Lang Li, Kai-Yuan Chao
2011 — conf
Lithography-aware layout modification considering performance impact.
ISQED
Hongbo Zhang, Yuelin Du, Martin D. F. Wong, Kai-Yuan Chao
2011 — conf
Mask cost reduction with circuit performance consideration for self-aligned double patterning.
ASP-DAC
Hongbo Zhang, Yuelin Du, Martin D. F. Wong, Kai-Yuan Chao
2011 — conf
Simultaneous redundant via insertion and line end extension for yield optimization.
ASP-DAC
Shing-Tung Lin, Kuang-Yao Lee, Ting-Chi Wang, Cheng-Kok Koh, Kai-Yuan Chao
2010 — conf
Configurable multi-product floorplanning.
ASP-DAC
Qiang Ma, Martin D. F. Wong, Kai-Yuan Chao
2010 A* conf
Multi-threaded collision-aware global routing with bounded-length maze routing.
DAC
Wen-Hao Liu, Wei-Chun Kao, Yih-Lang Li, Kai-Yuan Chao
2010 — conf
On process-aware 1-D standard cell design.
ASP-DAC
Hongbo Zhang, Martin D. F. Wong, Kai-Yuan Chao
2010 J jnl
Optimal Double Via Insertion With On-Track Preference.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kuang-Yao Lee, Ting-Chi Wang, Cheng-Kok Koh, Kai-Yuan Chao
2009 A* conf
Spare-cell-aware multilevel analytical placement.
DAC
Zhe-Wei Jiang, Meng-Kai Hsu, Yao-Wen Chang, Kai-Yuan Chao
2009 — conf
Wire shaping is practical.
ISPD
Hongbo Zhang, Martin D. F. Wong, Kai-Yuan Chao, Liang Deng
2008 J jnl
Fast Dummy-Fill Density Analysis With Coupling Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hua Xiang, Liang Deng, Ruchir Puri, Kai-Yuan Chao, Martin D. F. Wong
2008 J jnl
Fast and Optimal Redundant Via Insertion.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kuang-Yao Lee, Cheng-Kok Koh, Ting-Chi Wang, Kai-Yuan Chao
2008 J jnl
Is Your Layout-Density Verification Exact? - A Fast Exact Deep Submicrometer Density Calculation Algorithm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hua Xiang, Kai-Yuan Chao, Ruchir Puri, Martin D. F. Wong
2008 — conf
Optimal post-routing redundant via insertion.
ISPD
Kuang-Yao Lee, Cheng-Kok Koh, Ting-Chi Wang, Kai-Yuan Chao
2007 — conf
Coupling-aware Dummy Metal Insertion for Lithography.
ASP-DAC
Liang Deng, Martin D. F. Wong, Kai-Yuan Chao, Hua Xiang
2007 — conf
Dummy fill density analysis with coupling constraints.
ISPD
Hua Xiang, Liang Deng, Ruchir Puri, Kai-Yuan Chao, Martin D. F. Wong
2007 — conf
Is your layout density verification exact?: a fast exact algorithm for density calculation.
ISPD
Hua Xiang, Kai-Yuan Chao, Ruchir Puri, Martin D. F. Wong
2006 J jnl
An ECO routing algorithm for eliminating coupling-capacitance violations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hua Xiang, Kai-Yuan Chao, Martin D. F. Wong
2006 A conf
Post-routing redundant via insertion and line end extension with via density consideration.
ICCAD
Kuang-Yao Lee, Ting-Chi Wang, Kai-Yuan Chao
2005 — conf
Exact Algorithms for Coupling Capacitance Minimization by Adding One Metal Layer.
ISQED
Hua Xiang, Kai-Yuan Chao, Martin D. F. Wong
2004 — conf
An ECO algorithm for eliminating crosstalk violations.
ISPD
Hua Xiang, Kai-Yuan Chao, D. F. Wong
2004 J jnl
Simultaneous floor plan and buffer-block optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, Kai-Yuan Chao
2003 — conf
Simultaneous floorplanning and buffer block planning.
ASP-DAC
Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, Kai-Yuan Chao
2002 A conf
ECO algorithms for removing overlaps between power rails and signal wires.
ICCAD
Hua Xiang, Kai-Yuan Chao, D. F. Wong
2002 A conf
Flip-Flop and Repeater Insertion for Early Interconnect Planning.
DATE
Ruibing Lu, Guoan Zhong, Cheng-Kok Koh, Kai-Yuan Chao
1998 J jnl
Minimum Crosstalk Vertical Layer Assignment for Three-Layer VHV Channel Routing.
VLSI Design
Shashidhar Thakur, Kai-Yuan Chao, D. F. Wong
1995 C conf
An Optimal Layer Assignment Algorithm for Minimizing Crosstalk for Three Layer VHV Channel Routing.
ISCAS
Shashidhar Thakur, Kai-Yuan Chao, D. F. Wong
1995 C conf
Floorplanning for Low Power Designs.
ISCAS
Kai-Yuan Chao, D. F. Wong
1995 A conf
Signal integrity optimization on the pad assignment for high-speed VLSI design.
ICCAD
Kai-Yuan Chao, D. F. Wong
1995 C conf
Thermal placement for high-performance multichip modules.
ICCD
Kai-Yuan Chao, D. F. Wong
1994 A conf
Layer assignment for high-performance multi-chip modules.
ICCAD
Kai-Yuan Chao, D. F. Wong