Kai-Pui Lam

27 papers B 5C 4Misc 1Journal 8Unranked 9
YearRankTypeTitle / Venue / Authors
2013 J jnl
Dynamic On-Chip Thermal Optimization for Three-Dimensional Networks-On-Chip.
Comput. J.
Ra'ed Al-Dujaily, Terrence S. T. Mak, Kai-Pui Lam, Fei Xia, Alex Yakovlev, Chi-Sang Poon
2011 J jnl
Adaptive Routing in Network-on-Chips Using a Dynamic-Programming Network.
IEEE Trans. Ind. Electron.
Terrence S. T. Mak, Peter Y. K. Cheung, Kai-Pui Lam, Wayne Luk
2011 C conf
Comparative ODE benchmarking of unidirectional and bidirectional DP networks for 3D-IC.
VLSI-SoC
Kai-Pui Lam, Terrence S. T. Mak, Chi-Sang Poon
2011 C conf
Cycle avoidance in 2D/3D bidirectional graphs using shortest-path dynamic programming network.
VLSI-SoC
Kai-Pui Lam, Terrence S. T. Mak, Chi-Sang Poon
2011 — conf
On-chip dynamic programming networks using 3D-TSV integration.
ICSAMOS
Ra'ed Al-Dujaily, Terrence S. T. Mak, Kuan Zhou, Kai-Pui Lam, Yicong Meng, Alexandre Yakovlev, Chi-Sang Poon
2010 J jnl
A CMOS Current-Mode Dynamic Programming Circuit.
IEEE Trans. Circuits Syst. I Regul. Pap.
Terrence S. T. Mak, Kai-Pui Lam, H. S. Ng, Guy Rachmuth, Chi-Sang Poon
2009 Misc conf
A DP-network for optimal dynamic routing in network-on-chip.
CODES+ISSS
Terrence S. T. Mak, Peter Y. K. Cheung, Wayne Luk, Kai-Pui Lam
2009 J jnl
Intra-daily information of range-based volatility for MEM-GARCH.
Math. Comput. Simul.
Kai-Pui Lam, H. S. Ng
2007 C conf
A Current-Mode Analog Circuit for Reinforcement Learning Problems.
ISCAS
Terrence S. T. Mak, Kai-Pui Lam, H. S. Ng, Guy Rachmuth, Chi-Sang Poon
2007 — conf
A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing.
NOCS
Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk, Kai-Pui Lam
2006 — conf
How Does Sample Size Affect GARCH Models?
JCIS
H. S. Ng, Kai-Pui Lam
2004 B conf
An ICA design of intraday stock prediction models with automatic variable selection.
IJCNN
P. Y. Mok, Kai-Pui Lam, H. S. Ng
2004 — conf
Embedded Computation of Maximum-Likelihood Phylogeny Inference Using Platform FPGA.
CSB
Terrence S. T. Mak, Kai-Pui Lam
2004 B conf
FPGA-Based Computation for Maximum Likelihood Phylogenetic Tree Evaluation.
FPL
Terrence S. T. Mak, Kai-Pui Lam
2004 B conf
On Computing Maximum Likelihood Phylogeny Using FPGA p.
FPL
Terrence S. T. Mak, Kai-Pui Lam
2003 — conf
An FPGA-based eigenfilter using fast Hebbian learning.
ICASSP (2)
Kai-Pui Lam, Sui-Tung Mak
2003 J jnl
Analog and digital FPGA implementation of BRIN for optimization problems.
IEEE Trans. Neural Networks
H. S. Ng, Kai-Pui Lam
2003 — conf
Field programmable gate arrays and analog implementation of BRIN for optimization problems.
ISCAS (5)
H. S. Ng, Sui-Tung Mak, Kai-Pui Lam
2003 — conf
High Speed GAML-based Phylogenetic Tree Reconstruction Using HW/SW Codesign.
CSB
Terrence S. T. Mak, Kai-Pui Lam
2002 B conf
Extracting Causation Knowledge from Natural Language Texts.
PAKDD
Ki Chan, Boon Toh Low, Wai Lam, Kai-Pui Lam
2002 B conf
On Computing Transitive-Closure Equivalence Sets Using a Hybrid GA-DP Approach.
FPL
Kai-Pui Lam, Sui-Tung Mak
2002 — conf
Serial-parallel tradeoff analysis of all-pairs shortest path algorithms in reconfigurable computing.
FPT
Sui-Tung Mak, Kai-Pui Lam
1996 J jnl
A binary relation inference network Part 1. General concepts.
Int. J. Syst. Sci.
Kai-Pui Lam, Crystal J. Su
1996 J jnl
A binary relation inference network Part 2. State-space techniques.
Int. J. Syst. Sci.
Kai-Pui Lam
1996 J jnl
A continuous-time inference network and its hybrid implementations.
Int. J. Syst. Sci.
Kai-Pui Lam
1993 C conf
Digital Circuit Implementation of a Continuous-time Inference Network for the Transitive Closure Problem.
ISCAS
Crystal J. Su, Kai-Pui Lam
1991 — conf
On a Binary Relation Inference Network.
IPPS
Kai-Pui Lam, Crystal J. Su