Kai-Hui Chang - RankMe

39 papers A* 3A 7B 1C 3Journal 10Unranked 13

Year	Rank	Type	Title / Venue / Authors
2019	—	`conf`	Path controllability analysis for high quality designs. ASP-DAC Li-Jie Chen, Hong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo, Chi-Lai Huang
2016	J	`jnl`	Handling Nondeterminism in Logic Simulation so That Your Waveform Can Be Trusted Again. IEEE Des. Test Kai-Hui Chang, Hong-Zu Chou, Haiqian Yu, Dylan Dobbyn, Sy-Yen Kuo
2015	A*	`conf`	Scalable sequence-constrained retention register minimization in power gating design. DAC Ting-Wei Chiang, Kai-Hui Chang, Yen-Ting Liu, Jie-Hong R. Jiang
2014	—	`conf`	Automated methods for eliminating X bugs. ISQED Kai-Hui Chang, Yen-Ting Liu, Chris Browy
2012	C	`conf`	Improving design verifiability by early RTL coverability analysis. MEMOCODE Kai-Hui Chang, Chia-Wei Chang, Jie-Hong Roland Jiang, Chien-Nan Jimmy Liu
2012	A*	`conf`	Improving gate-level simulation accuracy when unknowns exist. DAC Kai-Hui Chang, Chris Browy
2012	J	`jnl`	Parallel Logic Simulation: Myth or Reality? Computer Kai-Hui Chang, Chris Browy
2012	A	`conf`	RTL analysis and modifications for improving at-speed test. DATE Kai-Hui Chang, Hong-Zu Chou, Igor L. Markov
2012	—	`conf`	Reducing test point overhead with don't-cares. MWSCAS Kai-Hui Chang, Chia-Wei Chang, Jie-Hong Roland Jiang, Chien-Nan Jimmy Liu
2011	C	`conf`	Applying verification intention for design customization via property mining under constrained testbenches. ICCD Chih-Neng Chung, Chia-Wei Chang, Kai-Hui Chang, Sy-Yen Kuo
2011	—	`conf`	Constraint generation for software-based post-silicon bug masking with scalable resynthesis technique for constraint optimization. ISQED Chia-Wei Chang, Hong-Zu Chou, Kai-Hui Chang, Jie-Hong Roland Jiang, Chien-Nan Jimmy Liu, Chiu-Han Hsiao, Sy-Yen Kuo
2011	—	`conf`	Facilitating unreachable code diagnosis and debugging. ASP-DAC Hong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo
2011	A	`conf`	Formal reset recovery slack calculation at the register transfer level. DATE Chih-Neng Chung, Chia-Wei Chang, Kai-Hui Chang, Sy-Yen Kuo
2010	J	`jnl`	Accurately Handle Don't-Care Conditions in High-Level Designs and Application for Reducing Initialized Registers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo
2010	A	`conf`	Finding reset nondeterminism in RTL designs - scalable X-analysis methodology and case study. DATE Hong-Zu Chou, Haiqian Yu, Kai-Hui Chang, Dylan Dobbyn, Sy-Yen Kuo
2010	J	`jnl`	Logic synthesis and circuit customization using extensive external don't-cares. ACM Trans. Design Autom. Electr. Syst. Kai-Hui Chang, Valeria Bertacco, Igor L. Markov, Alan Mishchenko
2010	—	`conf`	Optimizing blocks in an SoC using symbolic code-statement reachability analysis. ASP-DAC Hong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo
2009	A	`conf`	Customizing IP cores for system-on-chip designs using extensive external don't-cares. DATE Kai-Hui Chang, Valeria Bertacco, Igor L. Markov
2009	—	`conf`	Enhancing bug hunting using high-level symbolic simulation. ACM Great Lakes Symposium on VLSI Hong-Zu Chou, I-Hui Lin, Ching-Sung Yang, Kai-Hui Chang, Sy-Yen Kuo
2009	—	`book`	Functional Design Errors in Digital Circuits - Diagnosis, Correction and Repair Kai-Hui Chang, Igor L. Markov, Valeria Bertacco
2009	A*	`conf`	Handling don't-care conditions in high-level synthesis and application for reducing initialized registers. DAC Hong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo
2009	J	`jnl`	Incremental Verification with Error Detection, Diagnosis, and Visualization. IEEE Des. Test Comput. Kai-Hui Chang, David A. Papa, Igor L. Markov, Valeria Bertacco
2008	J	`jnl`	Automating Postsilicon Debugging and Repair. Computer Kai-Hui Chang, Igor L. Markov, Valeria Bertacco
2008	J	`jnl`	Fixing Design Errors With Counterexamples and Resynthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kai-Hui Chang, Igor L. Markov, Valeria Bertacco
2008	—	`conf`	Reap what you sow: spare cells for post-silicon metal fix. ISPD Kai-Hui Chang, Igor L. Markov, Valeria Bertacco
2008	J	`jnl`	SafeResynth: A new technique for physical synthesis. Integr. Kai-Hui Chang, Igor L. Markov, Valeria Bertacco
2007	—	`conf`	Automatic error diagnosis and correction for RTL designs. HLDVT Kai-Hui Chang, Ilya Wagner, Valeria Bertacco, Igor L. Markov
2007	A	`conf`	Automating post-silicon debugging and repair. ICCAD Kai-Hui Chang, Igor L. Markov, Valeria Bertacco
2007	—	`conf`	Fixing Design Errors with Counterexamples and Resynthesis. ASP-DAC Kai-Hui Chang, Igor L. Markov, Valeria Bertacco
2007	—	`—`	Functional design error diagnosis, correction and layout repair of digital circuits. Kai-Hui Chang
2007	—	`conf`	InVerS: An Incremental Verification System with Circuit Similarity Metrics and Error Visualization. ISQED Kai-Hui Chang, David A. Papa, Igor L. Markov, Valeria Bertacco
2007	—	`conf`	Node Mergers in the Presence of Don't Cares. ASP-DAC Stephen Plaza, Kai-Hui Chang, Igor L. Markov, Valeria Bertacco
2007	J	`jnl`	Postplacement rewiring by exhaustive search for functional symmetries. ACM Trans. Design Autom. Electr. Syst. Kai-Hui Chang, Igor L. Markov, Valeria Bertacco
2007	—	`conf`	Safe Delay Optimization for Physical Synthesis. ASP-DAC Kai-Hui Chang, Igor L. Markov, Valeria Bertacco
2007	J	`jnl`	Simulation-Based Bug Trace Minimization With BMC-Based Refinement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kai-Hui Chang, Valeria Bertacco, Igor L. Markov
2005	C	`conf`	Automatic Partitioner for Behavior Level Distributed Logic Simulation. FORTE Kai-Hui Chang, Jeh-Yen Kang, Han-Wei Wang, Wei-Ting Tu, Yi-Jong Yeh, Sy-Yen Kuo
2005	A	`conf`	Post-placement rewiring and rebuffering by exhaustive search for functional symmetries. ICCAD Kai-Hui Chang, Igor L. Markov, Valeria Bertacco
2005	A	`conf`	Simulation-based bug trace minimization with BMC-based refinement. ICCAD Kai-Hui Chang, Valeria Bertacco, Igor L. Markov
2004	B	`conf`	A Temporal Assertion Extension to Verilog. ATVA Kai-Hui Chang, Wei-Ting Tu, Yi-Jong Yeh, Sy-Yen Kuo