Ka-Fai Un

43 papers C 3Journal 28Unranked 12
YearRankTypeTitle / Venue / Authors
2026 J jnl
A 3.51 TOPS/mm
IEEE Trans. Circuits Syst. I Regul. Pap.
Zhongyu Zhao, Rujian Cao, Ka-Fai Un, Wei-Han Yu, Rui Paulo Martins, Pui-In Mak
2025 J jnl
A 1.8% FAR, 2 ms Decision Latency, 1.73 nJ/Decision Keywords-Spotting (KWS) Chip Incorporating Transfer-Computing Speaker Verification, Hybrid-IF-Domain Computing and Scalable 5T-SRAM.
IEEE J. Solid State Circuits
Fei Tan, Wei-Han Yu, Jinhai Lin, Ka-Fai Un, Rui Paulo Martins, Pui-In Mak
2025 J jnl
A 28-nm MFCC-Free Keyword Switchable Keyword Spotting (KWS) System With Transferred Training Algorithm.
IEEE Trans. Circuits Syst. II Express Briefs
Fei Tan, Yujia Wang, Wei-Han Yu, Ka-Fai Un, Rui Paulo Martins, Pui-In Mak
2025 J jnl
A 362-TOPS/W Mixed-Signal MAC Macro With Sampling-Weight-Nonlinearity Cancellation and Dynamic-Amplified Accumulation.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ran Zhang, Xueru Cen, Ka-Fai Un, Mingqiang Guo, Liang Qi, Rui Paulo Martins, Sai-Weng Sin
2025 J jnl
A 90.7-nW Vibration-Based Condition Monitoring Chip Featuring a Digital Compute-in-Memory- Based DNN Accelerator Using an Ultra-Low-Power 13T-SRAM Cell.
IEEE J. Solid State Circuits
Haochen Zhang, Wei-Han Yu, Zhizhan Yang, Ka-Fai Un, Jun Yin, Rui Paulo Martins, Pui-In Mak
2025 — conf
A 94.8nW Battery-Free Intelligent Silicon Platform Enabling Distributed, Adaptive, and Event-Driven Multimodal Sensing at the Edge.
ISSCC
Haochen Zhang, Wei-Han Yu, Zhongyu Zhao, Zhizhan Yang, Ka-Fai Un, Jun Yin, Rui Paulo Martins, Pui-In Mak
2025 J jnl
A 97.8 GOPS/W FPGA-Based Residual-Block-Aware CNN Accelerator Featuring Multi-Clock PW
IEEE Trans. Circuits Syst. I Regul. Pap.
Jixuan Li, Ke Li, Ka-Fai Un, Wei-Han Yu, Rui Paulo Martins, Pui-In Mak
2025 — conf
A Keyword-Spotting(KWS) Chip Featuring a Bio-Inspired Neuron Model in 65-nm CMOS.
CNIOT
Yantong Liu, Fei Tan, Ka-Fai Un, Wei-Han Yu, Rui Paulo Martins, Pui-In Mak
2025 J jnl
An 800-MHz 8.17-TOPS/W 0.63-TOPS/mm
IEEE J. Solid State Circuits
Jixuan Li, Ke Li, Ka-Fai Un, Wei-Han Yu, Rui Paulo Martins, Pui-In Mak
2025 J jnl
GSLP-CIM: A 28-nm Globally Systolic and Locally Parallel CNN/Transformer Accelerator With Scalable and Reconfigurable eDRAM Compute-in-Memory Macro for Flexible Dataflow.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yi Zhan, Wei-Han Yu, Ka-Fai Un, Rui Paulo Martins, Pui-In Mak
2024 — conf
17.9 A 1.8% FAR, 2ms Decision Latency, 1.73nJ/Decision Keywords Spotting (KWS) Chip Incorporating Transfer-Computing Speaker Verification, Hybrid-Domain Computing and Scalable 5T-SRAM.
ISSCC
Fei Tan, Wei-Han Yu, Jinhai Lin, Ka-Fai Un, Rui Paulo Martins, Pui-In Mak
2024 J jnl
A 0.05-mm
IEEE J. Solid State Circuits
Fei Tan, Wei-Han Yu, Ka-Fai Un, Rui Paulo Martins, Pui-In Mak
2024 J jnl
A 119.64 GOPs/W FPGA-Based ResNet50 Mixed-Precision Accelerator Using the Dynamic DSP Packing.
IEEE Trans. Circuits Syst. II Express Briefs
Yaozhong Ou, Wei-Han Yu, Ka-Fai Un, Chi-Hang Chan, Yan Zhu
2024 J jnl
A 28-nm 18.7 TOPS/mm² 89.4-to-234.6 TOPS/W 8b Single-Finger eDRAM Compute-in-Memory Macro With Bit-Wise Sparsity Aware and Kernel-Wise Weight Update/Refresh.
IEEE J. Solid State Circuits
Yi Zhan, Wei-Han Yu, Ka-Fai Un, Rui Paulo Martins, Pui-In Mak
2024 J jnl
A 512-nW 0.003-mm² Forward-Forward Closed Box Trainer for an Analog Voice Activity Detector in 28-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
Junde Li, Guoqiang Xin, Wei-Han Yu, Ka-Fai Un, Rui Paulo Martins, Pui-In Mak
2024 — conf
A 5T-SRAM Based Computing-in-Memory Macro Featuring Partial Sum Boosting and Analog Non-Uniform Quantization.
MWSCAS
Guoqiang Xin, Fei Tan, Junde Li, Junren Chen, Wei-Han Yu, Ka-Fai Un, Rui Paulo Martins, Pui-In Mak
2024 C conf
A Delta-Sigma-Based Computing-In-Memory Macro Targeting Edge Computation.
ISCAS
Ran Zhang, Ka-Fai Un, Mingqiang Guo, Liang Qi, Dengke Xu, Weibing Zhao, Rui Paulo Martins, Franco Maloberti, Sai-Weng Sin
2024 J jnl
An FPGA-Based Transformer Accelerator With Parallel Unstructured Sparsity Handling for Question-Answering Applications.
IEEE Trans. Circuits Syst. II Express Briefs
Rujian Cao, Zhongyu Zhao, Ka-Fai Un, Wei-Han Yu, Rui Paulo Martins, Pui-In Mak
2024 J jnl
CLUT-CIM: A Capacitance Lookup Table-Based Analog Compute-in-Memory Macro With Signed-Channel Training and Weight Updating for Nonuniform Quantization.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yuzhao Fu, Jixuan Li, Wei-Han Yu, Ka-Fai Un, Chi-Hang Chan, Yan Zhu, Rui Paulo Martins, Pui-In Mak
2024 J jnl
FLEX-CIM: A Flexible Kernel Size 1-GHz 181.6-TOPS/W 25.63-TOPS/mm
IEEE J. Solid State Circuits
Yuzhao Fu, Wei-Han Yu, Ka-Fai Un, Chi-Hang Chan, Yan Zhu, Minglei Zhang, Rui Paulo Martins, Pui-In Mak
2024 — conf
Invited Paper: A Ping-Pong Analog Delta Generator for Delt-Sigma Computing-In-Memory SRAM Macro for Edge AI Processing.
ICTA
Ran Zhang, Ka-Fai Un, Zhensheng Li, Mingqiang Guo, Liang Qi, Rui Paulo Martins, Sai-Weng Sin
2023 J jnl
A 47-nW Voice Activity Detector (VAD) Featuring a Short-Time CNN Feature Extractor and an RNN-Based Classifier With a Non-Volatile CAP-ROM.
IEEE J. Solid State Circuits
Jinhai Lin, Ka-Fai Un, Wei-Han Yu, Rui Paulo Martins, Pui-In Mak
2023 — conf
A 47nW Mixed-Signal Voice Activity Detector (VAD) Featuring a Non-Volatile Capacitor-ROM, a Short-Time CNN Feature Extractor and an RNN Classifier.
ISSCC
Jinhai Lin, Ka-Fai Un, Wei-Han Yu, Pui-In Mak, Rui Paulo Martins
2023 J jnl
An FPGA-Based Transformer Accelerator Using Output Block Stationary Dataflow for Object Recognition Applications.
IEEE Trans. Circuits Syst. II Express Briefs
Zhongyu Zhao, Rujian Cao, Ka-Fai Un, Wei-Han Yu, Pui-In Mak, Rui Paulo Martins
2022 J jnl
A 108-nW 0.8-mm
IEEE J. Solid State Circuits
Feifei Chen, Ka-Fai Un, Wei-Han Yu, Pui-In Mak, Rui Paulo Martins
2022 — conf
A 108nW 0.8mm
ISSCC
Feifei Chen, Ka-Fai Un, Wei-Han Yu, Pui-In Mak, Rui Paulo Martins
2022 J jnl
An FPGA-Based Energy-Efficient Reconfigurable Depthwise Separable Convolution Accelerator for Image Recognition.
IEEE Trans. Circuits Syst. II Express Briefs
Lei Xuan, Ka-Fai Un, Chi-Seng Lam, Rui Paulo Martins
2022 — conf
Design and Implementation of a Low Power Switched-Capacitor-Based Analog Feature Extractor for Voice Keyword Spotting.
APCCAS
Feifei Chen, Ka-Fai Un, Wei-Han Yu, Pui-In Mak, Rui Paulo Martins
2021 — conf
A 50.4 GOPs/W FPGA-Based MobileNetV2 Accelerator using the Double-Layer MAC and DSP Efficiency Enhancement.
A-SSCC
Jixuan Li, Jiabao Chen, Ka-Fai Un, Wei-Han Yu, Pui-In Mak, Rui Paulo Martins
2021 J jnl
An FPGA-Based Energy-Efficient Reconfigurable Convolutional Neural Network Accelerator for Object Recognition Applications.
IEEE Trans. Circuits Syst. II Express Briefs
Jixuan Li, Ka-Fai Un, Wei-Han Yu, Pui-In Mak, Rui Paulo Martins
2020 J jnl
Design Considerations of the Interpolative Digital Transmitter for Quantization Noise and Replicas Rejection.
IEEE Trans. Circuits Syst. II Express Briefs
Ka-Fai Un, Feifei Zhang, Pui-In Mak, Rui Paulo Martins, Anding Zhu, Robert Bogdan Staszewski
2019 J jnl
A 0.12-mm
IEEE Trans. Circuits Syst. I Regul. Pap.
Ka-Fai Un, Gengzhen Qi, Jun Yin, Shiheng Yang, Shupeng Yu, Chio-In Ieong, Pui-In Mak, Rui Paulo Martins
2018 J jnl
A 0.7-2.5 GHz, 61% EIRP System Efficiency, Four-Element MIMO TX System Exploiting Integrated Power-Relaxed Power Amplifiers and an Analog Spatial De-Interleaver.
IEEE Trans. Circuits Syst. I Regul. Pap.
Wei-Han Yu, Ka-Fai Un, Pui-In Mak, Rui Paulo Martins
2018 J jnl
Overview of Recent Development on Wireless Sensing Circuits and Systems for Healthcare and Biomedical Applications.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Changzhi Li, Ka-Fai Un, Pui-In Mak, Ying Chen, José Maria Muñoz-Ferreras, Zhi Yang, Roberto Gómez-García
2016 — conf
Time-domain I/Q-LOFT compensator using a simple envelope detector for a sub-GHz IEEE 802.11af WLAN transmitter.
ASP-DAC
Chak-Fong Cheang, Ka-Fai Un, Pui-In Mak, Rui Paulo Martins
2015 J jnl
A Combinatorial Impairment-Compensation Digital Predistorter for a Sub-GHz IEEE 802.11af-WLAN CMOS Transmitter Covering a 10x-Wide RF Bandwidth.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chak-Fong Cheang, Ka-Fai Un, Wei-Han Yu, Pui-In Mak, Rui Paulo Martins
2013 J jnl
A 53-to-75-mW, 59.3-dB HRR, TV-Band White-Space Transmitter Using a Low-Frequency Reference LO in 65-nm CMOS.
IEEE J. Solid State Circuits
Ka-Fai Un, Pui-In Mak, Rui Paulo Martins
2013 J jnl
A Nonrecursive Digital Calibration Technique for Joint Elimination of Transmitter and Receiver I/Q Imbalances With Minimized Add-On Hardware.
IEEE Trans. Circuits Syst. II Express Briefs
Wei-Han Yu, Chak-Fong Cheang, Pui-In Mak, Weng-Fai Cheng, Ka-Fai Un, U-Wai Lok, Rui Paulo Martins
2011 — conf
A highly-linear ultra-wideband balun-LNA for cognitive radios.
EUROCON
Weng-Fai Cheng, Ka-Fai Un, Pui-In Mak, Rui Paulo Martins
2010 J jnl
Analysis and Design of Open-Loop Multiphase Local-Oscillator Generator for Wireless Applications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ka-Fai Un, Pui-In Mak, Rui Paulo Martins
2010 C conf
SC biquad filter with hybrid utilization of OpAmp and comparator-based circuit.
ISCAS
Miguel A. Martins, Ka-Fai Un, Pui-In Mak, Rui Paulo Martins
2009 C conf
An Open-loop Octave-phase Local-oscillator Generator with High-precision Correlated Phases for VHF/UHF Mobile-TV Tuners.
ISCAS
Ka-Fai Un, Pui-In Mak, Rui Paulo Martins
2008 — conf
A DC-offset-compensated, CT/DT hybrid filter with process-insensitive cutoff and low in-band group-delay variation for WLAN receivers.
APCCAS
Ka-Fai Un, Pui-In Mak, Rui Paulo da Silva Martins