K. Wayne Current

40 papers A* 1A 1C 1Misc 5Journal 16Unranked 16
YearRankTypeTitle / Venue / Authors
2008 J jnl
Jitter Analysis of Nonautonomous MOS Current-Mode Logic Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap.
Marko Aleksic, Nikola Nedovic, K. Wayne Current, Vojin G. Oklobdzija
2007 J jnl
A High-Voltage SOI CMOS Exciter Chip for a Programmable Fluidic Processor System.
IEEE Trans. Biomed. Circuits Syst.
K. Wayne Current, Kelvin Yuk, Charles McConaghy, Peter R. C. Gascoyne, Jon A. Schwartz, Jody V. Vykoukal, Craig Andrews
2005 — conf
A High-Voltage Integrated Circuit Engine for a Dielectrophoresis-based Programmable Micro-Fluidic Processor.
ICMENS
K. Wayne Current, Kelvin Yuk, Charles McConaghy, Peter R. C. Gascoyne, Jon A. Schwartz, Jody V. Vykoukal, Craig Andrews
2005 — conf
A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency Dividers.
PATMOS
Marko Aleksic, Nikola Nedovic, K. Wayne Current, Vojin G. Oklobdzija
2004 J jnl
Low-Power Voltage Comparator Circuit for CMOS Quaternary Logic.
J. Multiple Valued Log. Soft Comput.
Yongjian Brandon Guo, K. Wayne Current
2002 — conf
Voltage Comparator Circuits for Multiple-Valued CMOS Logic.
ISMVL
Yongjian Brandon Guo, K. Wayne Current
2000 J jnl
Clocked CMOS adiabatic logic with integrated single-phase power-clock supply.
IEEE Trans. Very Large Scale Integr. Syst.
Dragan Maksimovic, Vojin G. Oklobdzija, Borivoje Nikolic, K. Wayne Current
2000 — conf
Design of a Quaternary Latch Circuit Using a Binary CMOS RS Latch.
ISMVL
K. Wayne Current
2000 — conf
Hardware Implementation of "Supplementary Symmetrical Logic Circuit Structure" Concepts.
ISMVL
Dan Olson, K. Wayne Current
2000 — conf
Partitioned Branch Condition Resolution Logic.
SBCCI
Aamir A. Farooqui, K. Wayne Current, Vojin G. Oklobdzija
1998 — conf
CMOS implementation of low-power oscillators based on the modified Fabre-Normand current conveyor.
ICECS
Jelena Popovic, Borivoje Nikolic, K. Wayne Current, Aleksandra Pavasovic, Dragan Vasiljevic
1997 A conf
Clocked CMOS adiabatic logic with integrated single-phase power-clock supply: experimental results.
ISLPED
Dragan Maksimovic, Vojin G. Oklobdzija, Borivoje Nikolic, K. Wayne Current
1996 — conf
Low-Energy Logic Circuit Techniques for Multiple-Valued Logic.
ISMVL
K. Wayne Current, Vojin G. Oklobdzija, Dragan Maksimovic
1995 J jnl
A CMOS continuous-time NTSC-to-color-difference decoder.
IEEE J. Solid State Circuits
James F. Parker, K. Wayne Current, Stephen H. Lewis
1995 — conf
Memory Circuits for Multiple-Valued Logic Voltage Signals.
ISMVL
K. Wayne Current
1994 J jnl
Current-mode CMOS multiple-valued logic circuits.
IEEE J. Solid State Circuits
K. Wayne Current
1994 — conf
Quaternary Multiplier Circuit.
ISMVL
Wei-Shang Chu, K. Wayne Current
1993 J jnl
An image processing IC for backprojection and spatial histogramming in a pipelined array.
IEEE J. Solid State Circuits
Iikender Agi, Paul J. Hurst, K. Wayne Current
1993 C conf
Block-Diagram-Level Design Capture, Functional Simulation, and Layout Assembly of Analog CMOS ICs.
ISCAS
K. Wayne Current, James F. Parker, Wes Hardaker
1993 — conf
Multiple Valued Logic: Current-Mode CMOS Circuits.
ISMVL
K. Wayne Current
1992 — conf
A Current-Mode CMOS Algorithmic Analog-to-Quaternary Converter Circuit.
ISMVL
K. Wayne Current
1992 J jnl
High-speed computation of the Radon transform and backprojection using an expandable multiprocessor architecture.
IEEE Trans. Circuits Syst. Video Technol.
Eric Shieh, K. Wayne Current, Paul J. Hurst, Iskender Agi
1991 — conf
A Bi-Directional Current-Mode CMOS Multiple-Valued Logic Memory Circuit.
ISMVL
K. Wayne Current, M. E. Hurlston
1991 A* conf
A new VLSI architecture for real-time control of robot manipulators.
ICRA
J. Liu, Ziqiang Mao, G. Z. Lu, W. H. Han, Tien C. Hsia, K. Wayne Current, Wei-Shang Chu
1990 — conf
A CMOS Quaternary Threshold Logic Full Adder Circuit with Transparent Latch.
ISMVL
K. Wayne Current
1990 Misc conf
A VLSI architecture for two-dimensional Radon transform computations.
ICASSP
Paul J. Hurst, K. Wayne Current, Iskender Agi, Eric Shieh
1990 J jnl
An evaluation of Radon transform computations using DSP chips.
Mach. Vis. Appl.
K. Wayne Current, Paul J. Hurst, Eric Shieh, Iskender Agi
1989 Misc conf
A Radon transform computer for multidimensional signal processing.
ICASSP
Stephen G. Azevedo, James M. Brase, Harry E. Martz, Anil K. Jain, K. Wayne Current, Paul J. Hurst
1989 J jnl
An architecture for region boundary extraction in raster scan images suitable for VLSI implementation.
Mach. Vis. Appl.
James M. Apffel, K. Wayne Current, Jorge L. C. Sanz, Anil K. Jain
1988 Misc conf
A unified DCT/IDCT architecture for VLSI implementation.
ICASSP
J. R. Parkhurst, K. Wayne Current, Anil K. Jain, J. E. Grishaw
1986 J jnl
Characteristics of Prototype CMOS Quaternary Logic Encoder-Decoder Circuits.
IEEE Trans. Computers
James L. Mangin, K. Wayne Current
1985 J jnl
Response change in linearized circuits and systems: Computational algorithms and applications.
Proc. IEEE
Stephen B. Haley, K. Wayne Current
1980 J jnl
A High Data-Rate Digital Output Correlator Design.
IEEE Trans. Computers
K. Wayne Current
1980 J jnl
High Density Integrated Computing Circuitry with Multiple Valued Logic.
IEEE Trans. Computers
K. Wayne Current
1980 J jnl
Pipelined Binary Parallel Counters Employing Latched Quaternary Logic Full Adders.
IEEE Trans. Computers
K. Wayne Current
1979 Misc conf
A high data rate, low power all-digital correlation circuit design.
ICASSP
K. Wayne Current, Douglas A. Mow, S. Youssef-Digaleh
1979 J jnl
Implementing Parallel Counters with Four-Valued Threshold Logic.
IEEE Trans. Computers
K. Wayne Current, Douglas A. Mow
1978 — conf
Applications of multivalued threshold logic in large-scale-intergrated, digital signal processing circuits.
MVL
K. Wayne Current, Douglas A. Mow
1978 — conf
Four-valued threshold logic full adder circuit implementations.
MVL
K. Wayne Current, Douglas A. Mow
1978 Misc conf
Parallel counter design using four-valued threshold logic.
ICASSP
K. Wayne Current, Douglas A. Mow