K. Sridharan

54 papers A* 2B 2C 4Misc 2Journal 39Unranked 3
YearRankTypeTitle / Venue / Authors
2025 J jnl
Low Complexity Three's Complement Parallel Multiplier Using Special Operators of Ternary Logic.
IEEE Trans. Circuits Syst. II Express Briefs
L. Hemanth Krishna, B. Srinivasu, K. Sridharan
2024 J jnl
Design and Implementation of a Magnetic Coupling Based Segmented Bend Angle Sensor for a Soft Robotic Gripper.
IEEE Trans. Instrum. Meas.
Debasrita Kar, Boby George, K. Sridharan
2022 B conf
A Bending Angle Sensor Based on Magnetic Coupling Suitable for Soft Robotic Finger.
SAS
Debasrita Kar, Boby George, K. Sridharan
2021 J jnl
A High-Performance VLSI Architecture for a Self-Feedback Convolutional Neural Network.
IEEE Trans. Circuits Syst. II Express Briefs
Yashrajsinh Parmar, K. Sridharan
2020 J jnl
A Resource-Efficient Multiplierless Systolic Array Architecture for Convolutions in Deep Networks.
IEEE Trans. Circuits Syst. II Express Briefs
Yashrajsinh Parmar, K. Sridharan
2020 J jnl
Interval Analysis Technique for Versatile and Parallel Multi-Agent Collision Detection and Avoidance.
J. Intell. Robotic Syst.
Pranjal Vyas, Leena Vachhani, K. Sridharan
2020 J jnl
Protecting an Autonomous Delivery Agent Against a Vision-Guided Adversary: Algorithms and Experimental Results.
IEEE Trans. Ind. Informatics
Bhaskar Vundurthy, K. Sridharan
2019 C conf
Analysing interactions between a trio of differential drive robots via a differential game formulation.
ACC
Sharad Kumar Singh, Puduru Viswanadha Reddy, K. Sridharan
2019 J jnl
Multiagent Gathering With Collision Avoidance and a Minimax Distance Criterion - Efficient Algorithms and Hardware Realization.
IEEE Trans. Ind. Informatics
Bhaskar Vundurthy, K. Sridharan
2018 C conf
Hardware-Efficient Velocity Estimation of Dynamic Obstacles Based on a Novel Radix-4 CORDIC and FPGA Implementation.
IECON
Yashrajsinh Parmar, K. Sridharan
2018 C conf
Time Optimal Rendezvous for Multi-Agent Systems Amidst Obstacles - Theory and Experiments.
IECON
Bhaskar Vundurthy, K. Sridharan
2017 J jnl
A Synthesis Methodology for Ternary Logic Circuits in Emerging Device Technologies.
IEEE Trans. Circuits Syst. I Regul. Pap.
B. Srinivasu, K. Sridharan
2017 J jnl
A Transistor-Level Probabilistic Approach for Reliability Analysis of Arithmetic Circuits With Applications to Emerging Technologies.
IEEE Trans. Reliab.
Bodapati Srinivasu, K. Sridharan
2017 J jnl
Carbon nanotube FET-based low-delay and low-power multi-digit adder designs.
IET Circuits Devices Syst.
Bodapati Srinivasu, K. Sridharan
2017 J jnl
Majority Logic Formulations for Parallel Adder Designs at Reduced Delay and Circuit Complexity.
IEEE Trans. Computers
Vikramkumar Pudi, K. Sridharan, Fabrizio Lombardi
2016 J jnl
Low-Complexity Multiternary Digit Multiplier Design in CNTFET Technology.
IEEE Trans. Circuits Syst. II Express Briefs
Bodapati Srinivasu, K. Sridharan
2016 J jnl
Real-Time SURF-Based Video Stabilization System for an FPGA-Driven Mobile Robot.
IEEE Trans. Ind. Electron.
Tahiyah Nou Shene, K. Sridharan, N. Sudha
2015 J jnl
A Bit-Serial Pipelined Architecture for High-Performance DHT Computation in Quantum-Dot Cellular Automata.
IEEE Trans. Very Large Scale Integr. Syst.
Vikramkumar Pudi, K. Sridharan
2015 — book
Design of Arithmetic Circuits in Quantum Dot Cellular Automata Nanotechnology
K. Sridharan, Vikram Pudi
2015 J jnl
Very large-scale integration architecture for video stabilisation and implementation on a field programmable gate array-based autonomous vehicle.
IET Comput. Vis.
Tahiyah Nou Shene, Vikramkumar Pudi, K. Sridharan, Vineetha Thomas, J. Arthi
2014 — conf
A pipelined architecture for motion tracking on a multicore environment.
ISIC
Natarajan Sudha, K. Sridharan, Dan Wilkinson
2012 J jnl
New Decomposition Theorems on Majority Logic for Low-Delay Adder Designs in Quantum Dot Cellular Automata.
IEEE Trans. Circuits Syst. II Express Briefs
Vikram Pudi, K. Sridharan
2011 J jnl
Efficient Design of a Hybrid Adder in Quantum-Dot Cellular Automata.
IEEE Trans. Very Large Scale Integr. Syst.
Vikram Pudi, K. Sridharan
2011 — conf
Efficient VLSI Architectures for the Hadamard Transform Based on Offset-Binary Coding and ROM Decomposition.
ISVLSI
B. Sandeep Kumar, Vikram Pudi, K. Sridharan
2010 C conf
Robotic mapping with simple sensing and processing hardware - Algorithm and architecture.
ICARCV
Leena Vachhani, K. Sridharan
2009 J jnl
50 Years of CORDIC: Algorithms, Architectures, and Applications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Pramod Kumar Meher, Javier Valls, Tso-Bing Juang, K. Sridharan, Koushik Maharatna
2009 J jnl
Efficient CORDIC Algorithms and Architectures for Low Area and High Throughput Implementation.
IEEE Trans. Circuits Syst. II Express Briefs
Leena Vachhani, K. Sridharan, Pramod Kumar Meher
2009 J jnl
Efficient FPGA Realization of CORDIC With Application to Robotic Exploration.
IEEE Trans. Ind. Electron.
Leena Vachhani, K. Sridharan, Pramod Kumar Meher
2008 J jnl
Hardware-Efficient Prediction-Correction-Based Generalized-Voronoi-Diagram Construction and FPGA Implementation.
IEEE Trans. Ind. Electron.
Leena Vachhani, K. Sridharan
2008 — book
Robotic Exploration and Landmark Determination: Hardware-Efficient Algorithms and FPGA Implementations.
K. Sridharan, Panakala Rajesh Kumar
2007 J jnl
A Hardware Accelerator and FPGA Realization for Reduced Visibility Graph Construction Using Efficient Bit Representations.
IEEE Trans. Ind. Electron.
K. Sridharan, T. K. Priya
2007 J jnl
VLSI-Efficient Scheme and FPGA Realization for Robotic Mapping in a Dynamic Environment.
IEEE Trans. Very Large Scale Integr. Syst.
P. Rajesh Kumar, K. Sridharan
2006 J jnl
A hardware-efficient scheme and FPGA realization for computation of single pair shortest path for a mobile automaton.
Microprocess. Microsystems
T. K. Priya, P. Rajesh Kumar, K. Sridharan
2006 J jnl
A parallel algorithm, architecture and FPGA realization for high speed determination of the complete visibility graph for convex objects.
Microprocess. Microsystems
T. K. Priya, K. Sridharan
2006 J jnl
A parallel algorithm, architecture and FPGA realization for landmark determination and map construction in a planar unknown environment.
Parallel Comput.
P. Rajesh Kumar, K. Sridharan, S. Srinivasan
2005 J jnl
The Design of a Hardware Accelerator for Real-Time Complete Visibility Graph Construction and Efficient FPGA Implementation.
IEEE Trans. Ind. Electron.
K. Sridharan, T. K. Priya
2005 J jnl
VLSI-efficient schemes for high-speed construction of tangent graph.
Robotics Auton. Syst.
Siew Kei Lam, K. Sridharan, Thambipillai Srikanthan
2004 J jnl
A course on web languages and web-based applications.
IEEE Trans. Educ.
K. Sridharan
2004 J jnl
A high-speed VLSI design and ASIC implementation for constructing Euclidean distance-based discrete Voronoi diagram.
IEEE Trans. Robotics Autom.
Natarajan Sudha, K. Sridharan
2004 J jnl
A parallel algorithm for constructing reduced visibility graph and its FPGA implementation.
J. Syst. Archit.
K. Sridharan, T. K. Priya
2004 Misc conf
An Efficient Algorithm to Construct Reduced Visibility Graph and Its FPGA Implementation.
VLSI Design
T. K. Priya, K. Sridharan
2004 J jnl
Hardware-efficient schemes for logarithmic approximation and binary search with application to visibility graph construction.
IEEE Trans. Ind. Electron.
Siew Kei Lam, K. Sridharan, Thambipillai Srikanthan
2002 J jnl
Efficient computation of a measure of depth between convex objects for graphics applications.
Comput. Graph.
K. Sridharan
2002 J jnl
The design and development of a web-based data acquisition system.
IEEE Trans. Instrum. Meas.
B. Rajesh Kumar, K. Sridharan, K. Srinivasan
2001 J jnl
Computation of a penetration measure between 3D convex polyhedral objects for collision detection.
J. Field Robotics
K. Sridharan, S. Sathiya Keerthi
2000 J jnl
Teaching computer graphics and robotics using symbolic computation software.
Comput. Appl. Eng. Educ.
K. Sridharan
1999 A* conf
A Parallel Algorithm to Construct Voronoi Diagram and Its VLSI Architecture.
ICRA
N. Sudha, Sukumar Nandi, K. Sridharan
1999 J jnl
Computing two penetration measures for curved 2D objects.
Inf. Process. Lett.
K. Sridharan
1999 J jnl
Fuzzy distances for proximity characterization under uncertainty.
Fuzzy Sets Syst.
K. Sridharan, Harry E. Stephanou
1998 Misc conf
Computation of penetration measures for convex polygons and polyhedra for graphics applications.
HiPC
K. Sridharan
1994 A* conf
Algorithms for Rapid Computation of Some Distance Functions Between Objects for Path Planning.
ICRA
K. Sridharan, Harry E. Stephanou
1994 J jnl
Distance Measures on Intersecting Objects and Their Applications.
Inf. Process. Lett.
K. Sridharan, Harry E. Stephanou, K. C. Craig, S. Sathiya Keerthi
1993 — conf
On Computing a Distance Measure for Path Planning.
ICRA (1)
K. Sridharan, Harry E. Stephanou, S. Sathiya Keerthi
1992 B conf
Fuzzy Distance Functions for Motion Planning.
ICTAI
K. Sridharan, Harry E. Stephanou