K. S. Gurumurthy

12 papers Journal 4Unranked 8
YearRankTypeTitle / Venue / Authors
2013 — conf
Instruction Level Power Analysis for Low Power VLSI Applications.
ICETET
Prashant V. Joshi, N. Prameela Kumari, K. S. Gurumurthy
2013 — conf
Realization of Basic Gates Using Universal Logic Blocks in Quantum Dot Cellular Automata.
ICETET
N. Prameela Kumari, Prashant V. Joshi, K. S. Gurumurthy
2012 J jnl
Deploying Health Monitoring ECU Towards Enhancing the Performance of In-Vehicle Network
CoRR
Geetishree Mishra, Rajeshwari Hegde, K. S. Gurumurthy
2012 — conf
Implementation of Gating Technique with Modified Scan Flip-Flop for Low Power Testing of VLSI Chips.
VDAT
R. Jayagowri, K. S. Gurumurthy
2011 — conf
Design of High Performance Quaternary Adders.
ISMVL
K. S. Vasundara Patel, K. S. Gurumurthy
2010 J jnl
Arithmetic Operations in Multi-Valued Logic
CoRR
K. S. Vasundara Patel, K. S. Gurumurthy
2010 J jnl
New Improved Echo Canceller Based on Normalized LMS Adaptive Filter for Single Talk and Double Talk Detection, Subband Echo Cancellation, Acoustic Echo Cancellation.
J. Next Gener. Inf. Technol.
Suma S. A., K. S. Gurumurthy
2010 J jnl
Sub Band Speech Analysis Using Gammatone Filter Banks and Optimal Pitch Extraction Methods for Each Sub Band Using Average Magnitude Difference Function (AMDF) for LPC Speech Coders in Noisy Environments.
J. Next Gener. Inf. Technol.
Suma S. A., K. S. Gurumurthy
2009 — conf
Load Balancing in Multi ECU Configuration.
ARTCom
Rajeshwari Hegde, K. S. Gurumurthy
2009 — conf
Load Balancing towards ECU Integration.
ARTCom
Rajeshwari Hegde, K. S. Gurumurthy
2009 — conf
Moving From Binary Towards Multi-valued logic.
CDES
K. S. Vasundara Patel, K. S. Gurumurthy
2003 — conf
Artificial neural networks as building blocks of mixed signal FPGA.
FPT
R. Manjunath, K. S. Gurumurthy