Jürgen Teich - RankMe

734 papers A* 19A 70B 54C 69Misc 42Journal 173Unranked 274

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	Dynamically Adaptable Ensemble Proxies for Training-Free Neural Architecture Search. EuroMLSys@EuroSys Christian Heidorn, Tina Herderich, Jürgen Teich
2026	J	`jnl`	Exploration of Energy and Throughput Tradeoffs for Dataflow Networks. CoRR Abrarul Karim, Joachim Falk, Jürgen Teich
2026	J	`jnl`	Loop Control Management in Tightly Coupled Processor Arrays (TCPAs). CoRR Dominik Walter, Frank Hannig, Jürgen Teich
2025	—	`conf`	A SIMD MAC RISC-V Extension with Approximate Multipliers for Accelerating CNN Inference in Tiny Embedded Devices. ARCS José Juan Hernández Morales, Frank Hannig, Jürgen Teich
2025	J	`jnl`	Beyond BNNs: Design and Acceleration of Sub-Bit Neural Networks Using RISC-V Custom Functional Units. IEEE Embed. Syst. Lett. Muhammad Sabih, Mohamed Abdo, Frank Hannig, Jürgen Teich
2025	—	`conf`	Breaking Confidentiality of XTS-AES Encrypted Data at Rest on Microprocessors Using Electromagnetic Side-Channel Attacks. HOST Paul Krüger, Stefan Wildermann, Jürgen Teich
2025	—	`conf`	CHaOS: A Persistent Lightweight Cache Hybridization-Aware OS. ARCS Nils Wilbert, Matthias Szymanski, Stefan Wildermann, Henriette Herzog, Timo Hönig, Jürgen Teich
2025	A	`conf`	Co-Design of Sustainable Embedded Systems-on-Chip. DATE Jan Spieck, Dominik Walter, Jan Waschkeit, Jürgen Teich
2025	—	`conf`	Co-Design of Systems-On-Chip for Sustainability. NG-RES@HiPEAC Jan Spieck, Dominik Walter, Jan Waschkeit, Jürgen Teich
2025	J	`jnl`	Combining Multi-Objective Bayesian Optimization with Reinforcement Learning for TinyML. ACM Trans. Evol. Learn. Optim. Mark Deutel, Georgios D. Kontes, Christopher Mutschler, Jürgen Teich
2025	A	`conf`	Design of Machine Learning Accelerators as RISC-V Extensions using an Open Source Tool Flow. ICCAD Batuhan Sesli, Muhammad Sabih, Frank Hannig, Jürgen Teich
2025	—	`conf`	Early-Exit Neural Architecture Search for Energy-Harvesting Edge Computing. MCSoC Pierre-Louis Sixdenier, Mark Deutel, Jürgen Teich
2025	J	`jnl`	Evaluation of CGRA Toolchains. CoRR Dominik Walter, Marita Halm, Daniel Seidel, Indrayudh Ghosh, Christian Heidorn, Frank Hannig, Jürgen Teich
2025	—	`conf`	FSST Compression of JSON Data on FPGAs. ARCS Tobias Hahn, Jan Hofmann, Stefan Wildermann, Jürgen Teich
2025	J	`jnl`	Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs. CoRR Muhammad Sabih, Abrarul Karim, Jakob Wittmann, Frank Hannig, Jürgen Teich
2025	J	`jnl`	Mapping and Execution of Nested Loops on Processor Arrays: CGRAs vs. TCPAs. CoRR Dominik Walter, Marita Halm, Daniel Seidel, Indrayudh Ghosh, Christian Heidorn, Frank Hannig, Jürgen Teich
2025	J	`jnl`	Modeling and Simulating Emerging Memory Technologies: A Tutorial. CoRR Yun-Chih Chen, Tristan Taylan Seidl, Nils Hölscher, Christian Hakert, Minh Duy Truong, Jian-Jia Chen, João Paulo C. de Lima, Asif Ali Khan, Jerónimo Castrillón, Ali Nezhadi, Lokesh Siddhu, Hassan Nassar, Mahta Mayahinia, Mehdi Baradaran Tahoori, Jörg Henkel, Nils Wilbert, Stefan Wildermann, Jürgen Teich
2025	—	`conf`	Multi-Objective Bayesian Optimization with Reinforcement Learning for Edge Deployment of DNNs on Microcontrollers. GECCO Companion Mark Deutel, Georgios D. Kontes, Christopher Mutschler, Jürgen Teich
2025	A	`conf`	Multi-Partner Project: Open-Source Design Tools for Co-Development of AI Algorithms and AI Chips: (Initial Stage). DATE Mehdi B. Tahoori, Jürgen Becker, Jörg Henkel, Wolfgang Kunz, Ulf Schlichtmann, Georg Sigl, Jürgen Teich, Norbert Wehn
2025	J	`jnl`	On-Device Training of Fully Quantized Deep Neural Networks on Cortex-M Microcontrollers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mark Deutel, Frank Hannig, Christopher Mutschler, Jürgen Teich
2025	Misc	`conf`	ReProVide: Query Optimisation and Near-Data Processing on Reconfigurable SoCs for Big Data Analysis. BTW Tobias Hahn, Maximilian S. Langohr, Stefan Meißner, Benedikt Döring, Stefan Wildermann, Klaus Meyer-Wegener, Jürgen Teich
2025	—	`conf`	Response Range Optimization for Run-Time Requirement Enforcement on MPSoCs. ASP-DAC Khalil Esper, Stefan Wildermann, Jürgen Teich
2025	—	`conf`	Run-Time Requirement Enforcement of Safety Requirements of Human-Robot Interactions. ICARA Khalil Esper, Stefan Wildermann, Jürgen Teich
2025	—	`conf`	Self-powered Embedded Systems: The Role of Non-volatile Memory Technology in IoT Devices. Go Where the Bugs Are Stefan Wildermann, Nils Wilbert, Tobias Häberlein, Jürgen Teich
2025	Misc	`conf`	Special Session - Hardware-Software Co-Design for Machine Learning Systems Made Open-Source. CODES+ISSS Mehdi B. Tahoori, Vincent Meyers, Mahboobe Sadeghipour Roodsari, Huashuangyang Xu, Jürgen Becker, Tanja Harbaum, Felix Frombach, Julian Höfer, Georgios Sotiropoulos, Jörg Henkel, Zeynep Demirdag, Heba Khdr, Hassan Nassar, Ulf Schlichtmann, Johannes Geier, Philipp van Kempen, Georg Sigl, Stefan Koegler, Matthias Probst, Jürgen Teich, Frank Hannig, Muhammad Sabih, Batuhan Sesli, Norbert Wehn, Lukas Steiner, Wolfgang Kunz, Mohamed Shelkamy Ali
2025	—	`conf`	Special Session Paper: FeMFET-Based High Performance, Ultra-Low Power Memory Cells for Reliable State Retention of Dataflow Networks. DFT Basile Darne, Abrarul Karim, Paul-Antoine Matrangolo, Joachim Falk, Ian O'Connor, Cédric Marchand, Alberto Bosio, Jürgen Teich
2025	—	`conf`	Unsupervised Learning of Variational Autoencoders on Cortex-M Microcontrollers. MCSoC Mark Deutel, Axel Plinge, Dominik Seuß, Christopher Mutschler, Frank Hannig, Jürgen Teich
2024	J	`jnl`	A Scenario-Based DVFS-Aware Hybrid Application Mapping Methodology for MPSoCs. ACM Trans. Design Autom. Electr. Syst. Jan Spieck, Stefan Wildermann, Jürgen Teich
2024	C	`conf`	ABACUS: ASIP-Based Avro Schema-Customizable Parser Acceleration on FPGAs. DDECS Tobias Hahn, Daniel Schüll, Stefan Wildermann, Jürgen Teich
2024	C	`conf`	ALPACA: An Accelerator Chip for Nested Loop Programs. ISCAS Dominik Walter, Marcel Brand, Christian Heidorn, Michael Witterauf, Frank Hannig, Jürgen Teich
2024	A	`conf`	Accelerating DNNs Using Weight Clustering on RISC-V Custom Functional Units. DATE Muhammad Sabih, Batuhan Sesli, Frank Hannig, Jürgen Teich
2024	—	`conf`	Analysis and Optimization of Block LU Decomposition for Execution on Tightly Coupled Processor Arrays. ASAP Dominik Walter, Thomas Adamtschuk, Frank Hannig, Jürgen Teich
2024	—	`conf`	CRESTS: Chronology-based Reconstruction for Side-Channel Trace Segmentation for XTS-AES on Complex Targets. EuroSec@EUROSYS Paul Krüger, Stefan Wildermann, Jürgen Teich
2024	C	`conf`	DSL-Based SNN Accelerator Design Using Chisel. DSD Patrick Plagwitz, Frank Hannig, Jürgen Teich, Oliver Keszöcze
2024	J	`jnl`	Design, Calibration, and Evaluation of Real-time Waveform Matching on an FPGA-based Digitizer at 10 GS/s. ACM Trans. Reconfigurable Technol. Syst. Jens Trautmann, Paul Krüger, Andreas Becher, Stefan Wildermann, Jürgen Teich
2024	C	`conf`	Efficient Deployment of Neural Networks for Thermal Monitoring on AURIX TC3xx Microcontrollers. VEHITS Christian Heidorn, Frank Hannig, Dominik Riedelbauch, Christoph Strohmeyer, Jürgen Teich
2024	J	`jnl`	Exploring Multi-Reader Buffers and Channel Placement During Dataflow Network Mapping to Heterogeneous Many-Core Systems. IEEE Access Martín Letras, Joachim Falk, Jürgen Teich
2024	—	`conf`	GRES: Guaranteed Remaining Energy Scheduling of Energy-harvesting Sensors by Quality Adaptation. MECO Pierre-Louis Sixdenier, Stefan Wildermann, Jürgen Teich
2024	J	`jnl`	Hardware-Aware Evolutionary Explainable Filter Pruning for Convolutional Neural Networks. Int. J. Parallel Program. Christian Heidorn, Muhammad Sabih, Nicolai Meyerhöfer, Christian Schinabeck, Jürgen Teich, Frank Hannig
2024	—	`conf`	Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs. ICFPT Muhammad Sabih, Abrarul Karim, Jakob Wittmann, Frank Hannig, Jürgen Teich
2024	—	`conf`	History-Based Run-Time Requirement Enforcement of Non-Functional Properties on MPSoCs. NG-RES@HiPEAC Khalil Esper, Jürgen Teich
2024	—	`conf`	Hybrid Cache Design Under Varying Power Supply Stability - A Comparative Study. MEMSYS Nils Wilbert, Stefan Wildermann, Jürgen Teich
2024	B	`conf`	JSON-CooP: A JSON Decompression/Parsing Co-Design for FPGAs. FPL Tobias Hahn, Stefan Wildermann, Jürgen Teich
2024	J	`jnl`	On-Device Training of Fully Quantized Deep Neural Networks on Cortex-M Microcontrollers. CoRR Mark Deutel, Frank Hannig, Christopher Mutschler, Jürgen Teich
2024	J	`jnl`	OpTC - A Toolchain for Deployment of Neural Networks on AURIX TC3xx Microcontrollers. CoRR Christian Heidorn, Frank Hannig, Dominik Riedelbauch, Christoph Strohmeyer, Jürgen Teich
2024	A	`conf`	Range-Based Run-time Requirement Enforcement of Non-Functional Properties on MPSoCs. DATE Khalil Esper, Stefan Wildermann, Jürgen Teich
2024	—	`conf`	SNN vs. CNN Implementations on FPGAs: An Empirical Evaluation. ARC Patrick Plagwitz, Frank Hannig, Jürgen Teich, Oliver Keszöcze
2024	C	`conf`	Self-Powering Dataflow Networks - Concepts and Implementation. MEMOCODE Abrarul Karim, Joachim Falk, Dennis Schmidt, Jürgen Teich
2024	—	`conf`	To Keep or Not to Keep - The Volatility of Replacement Policy Metadata in Hybrid Caches. DIMES@SOSP Nils Wilbert, Stefan Wildermann, Jürgen Teich
2024	J	`jnl`	microYOLO: Towards Single-Shot Object Detection on Microcontrollers. CoRR Mark Deutel, Christopher Mutschler, Jürgen Teich
2023	J	`jnl`	A Learning-based Methodology for Scenario-aware Mapping of Soft Real-time Applications onto Heterogeneous MPSoCs. ACM Trans. Design Autom. Electr. Syst. Jan Spieck, Stefan Wildermann, Jürgen Teich
2023	Misc	`conf`	An FPGA Avro Parser Generator for Accelerated Data Stream Processing. BTW Tobias Hahn, Daniel Schüll, Stefan Wildermann, Jürgen Teich
2023	J	`jnl`	Augmented Random Search for Multi-Objective Bayesian Optimization of Neural Networks. CoRR Mark Deutel, Georgios D. Kontes, Christopher Mutschler, Jürgen Teich
2023	J	`jnl`	Automatic Synthesis of FSMs for Enforcing Non-functional Requirements on MPSoCs Using Multi-objective Evolutionary Algorithms. ACM Trans. Design Autom. Electr. Syst. Khalil Esper, Stefan Wildermann, Jürgen Teich
2023	J	`jnl`	Efficient Table-based Function Approximation on FPGAs Using Interval Splitting and BRAM Instantiation. ACM Trans. Embed. Comput. Syst. Chetana Pradhan, Martín Letras, Jürgen Teich
2023	—	`conf`	Energy-efficient Deployment of Deep Learning Applications on Cortex-M based Microcontrollers using Deep Compression. MBMV Mark Deutel, Philipp Woller, Christopher Mutschler, Jürgen Teich
2023	J	`jnl`	Exploring Multi-Reader Buffers and Channel Placement during Dataflow Network Mapping to Heterogeneous Many-core Systems. CoRR Martín Letras, Joachim Falk, Jürgen Teich
2023	C	`conf`	Hybrid Genetic Reinforcement Learning for Generating Run-Time Requirement Enforcers. MEMOCODE Jan Spieck, Pierre-Louis Sixdenier, Khalil Esper, Stefan Wildermann, Jürgen Teich
2023	—	`conf`	RAVEN: Reinforcement Learning for Generating Verifiable Run-Time Requirement Enforcers for MPSoCs. NG-RES@HiPEAC Khalil Esper, Jan Spieck, Pierre-Louis Sixdenier, Stefan Wildermann, Jürgen Teich
2023	—	`conf`	Robust and Tiny Binary Neural Networks using Gradient-based Explainability Methods. EuroMLSys@EuroSys Muhammad Sabih, Mikail Yayla, Frank Hannig, Jürgen Teich, Jian-Jia Chen
2023	B	`conf`	SPEAR-JSON: Selective Parsing of JSON to Enable Accelerated Stream Processing on FPGAs. FPL Tobias Hahn, Stefan Wildermann, Jürgen Teich
2023	—	`conf`	Seque: Lean and Energy-aware Data Management for IoT Gateways. EDGE Pierre-Louis Sixdenier, Stefan Wildermann, Martin Ottens, Jürgen Teich
2023	J	`jnl`	Special Issue on Approximate Computing: Challenges, Methodologies, Algorithms, and Architectures for Dependable and Secure Systems. IEEE Des. Test Alberto Bosio, Mario Barbareschi, Alessandro Savino, Jie Han, Jürgen Teich
2023	Misc	`conf`	Special Session - Non-Volatile Memories: Challenges and Opportunities for Embedded System Architectures with Focus on Machine Learning Applications. CASES Jörg Henkel, Lokesh Siddhu, Lars Bauer, Jürgen Teich, Stefan Wildermann, Mehdi B. Tahoori, Mahta Mayahinia, Jerónimo Castrillón, Asif Ali Khan, Hamid Farzaneh, João Paulo C. de Lima, Jian-Jia Chen, Christian Hakert, Kuan-Hsun Chen, Chia-Lin Yang, Hsiang-Yun Cheng
2023	—	`conf`	Throughput and Memory Optimization for Parallel Implementations of Dataflow Networks Using Multi-Reader Buffers. NG-RES@HiPEAC Martín Letras, Joachim Falk, Jürgen Teich
2023	J	`jnl`	To Spike or Not to Spike? A Quantitative Comparison of SNN and CNN FPGA Implementations. CoRR Patrick Plagwitz, Frank Hannig, Jürgen Teich, Oliver Keszöcze
2023	—	`conf`	μYOLO: Towards Single-Shot Object Detection on Microcontrollers. PKDD/ECML Workshops (5) Mark Deutel, Christopher Mutschler, Jürgen Teich
2022	B	`conf`	Auto-Tuning of Raw Filters for FPGAs. FPL Tobias Hahn, Stefan Wildermann, Jürgen Teich
2022	Misc	`conf`	Characterization of Side Channels on FPGA-based Off-The-Shelf Boards against Automated Attacks. FCCM Jens Trautmann, Jürgen Teich, Stefan Wildermann
2022	B	`conf`	DSP-Packing: Squeezing Low-precision Arithmetic into FPGA DSP Blocks. FPL Jan Sommer, M. Akif Özkan, Oliver Keszöcze, Jürgen Teich
2022	J	`jnl`	DSP-Packing: Squeezing Low-precision Arithmetic into FPGA DSP Blocks. CoRR Jan Sommer, M. Akif Özkan, Oliver Keszöcze, Jürgen Teich
2022	J	`jnl`	Deployment of Energy-Efficient Deep Learning Models on Cortex-M based Microcontrollers using Deep Compression. CoRR Mark Deutel, Philipp Woller, Christopher Mutschler, Jürgen Teich
2022	J	`jnl`	Design and Evaluation of a Tunable PUF Architecture for FPGAs. ACM Trans. Reconfigurable Technol. Syst. Franz-Josef Streit, Paul Krüger, Andreas Becher, Stefan Wildermann, Jürgen Teich
2022	J	`jnl`	Design and error analysis of accuracy-configurable sequential multipliers via segmented carry chains. it Inf. Technol. Jorge Echavarria, Stefan Wildermann, Oliver Keszöcze, Faramarz Khosravi, Andreas Becher, Jürgen Teich
2022	—	`conf`	DyFiP: explainable AI-based dynamic filter pruning of convolutional neural networks. EuroMLSys@EuroSys Muhammad Sabih, Frank Hannig, Jürgen Teich
2022	J	`jnl`	Efficient Hardware Acceleration of Sparsely Active Convolutional Spiking Neural Networks. CoRR Jan Sommer, M. Akif Özkan, Oliver Keszöcze, Jürgen Teich
2022	J	`jnl`	Efficient Hardware Acceleration of Sparsely Active Convolutional Spiking Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jan Sommer, M. Akif Özkan, Oliver Keszöcze, Jürgen Teich
2022	J	`jnl`	Efficient Table-based Function Approximation on FPGAs using Interval Splitting and BRAM Instantiation. CoRR Chetana Pradhan, Martín Letras, Jürgen Teich
2022	B	`conf`	Grant Prediction-based Dynamic Power Management for 5G to Reduce Mobile Device Energy Consumption. IWCMC Peter Brand, Benjamin Hackenberg, Joachim Falk, Jürgen Teich
2022	—	`conf`	Hardware-Aware Evolutionary Filter Pruning. SAMOS Christian Heidorn, Nicolai Meyerhöfer, Christian Schinabeck, Frank Hannig, Jürgen Teich
2022	—	`conf`	MOSP: Multi-Objective Sensitivity Pruning of Deep Neural Networks. IGSC Muhammad Sabih, Ashutosh Mishra, Frank Hannig, Jürgen Teich
2022	—	`conf`	Multi-Requirement Enforcement of Non-Functional Properties on MPSoCs Using Enforcement FSMs - A Case Study. NG-RES@HiPEAC Khalil Esper, Stefan Wildermann, Jürgen Teich
2022	J	`jnl`	On Transferring Application Mapping Knowledge Between Differing MPSoC Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jan Spieck, Stefan Wildermann, Jürgen Teich
2022	J	`jnl`	Precision- and Accuracy-Reconfigurable Processor Architectures - An Overview. IEEE Trans. Circuits Syst. II Express Briefs Marcel Brand, Frank Hannig, Oliver Keszöcze, Jürgen Teich
2022	—	`conf`	Putting IMT to the Test: Revisiting and Expanding Interval Matching Techniques and their Calibration for SCA. ASHES@CCS Jens Trautmann, Nikolaos Patsiatzis, Andreas Becher, Stefan Wildermann, Jürgen Teich
2022	A	`conf`	Raw Filtering of JSON Data on FPGAs. DATE Tobias Hahn, Andreas Becher, Stefan Wildermann, Jürgen Teich
2022	J	`jnl`	Raw Filtering of JSON Data on FPGAs. CoRR Tobias Hahn, Andreas Becher, Stefan Wildermann, Jürgen Teich
2022	B	`conf`	Real-Time Waveform Matching with a Digitizer at 10 GS/s. FPL Jens Trautmann, Nikolaos Patsiatzis, Andreas Becher, Jürgen Teich, Stefan Wildermann
2022	J	`jnl`	Real-Time Waveform Matching with a Digitizer at 10 GS/s. CoRR Jens Trautmann, Nikolaos Patsiatzis, Andreas Becher, Jürgen Teich, Stefan Wildermann
2022	—	`conf`	SIDAM: A Design Space Exploration Framework for Multi-sensor Embedded Systems Powered by Energy Harvesting. SAMOS Pierre-Louis Sixdenier, Stefan Wildermann, Daniel Ziegler, Jürgen Teich
2022	J	`jnl`	Semi-Automatic Locating of Cryptographic Operations in Side-Channel Traces. IACR Trans. Cryptogr. Hardw. Embed. Syst. Jens Trautmann, Arthur Beckers, Lennert Wouters, Stefan Wildermann, Ingrid Verbauwhede, Jürgen Teich
2022	B	`conf`	TRAC: Compilation-Based Design of Transformer Accelerators for FPGAs. FPL Patrick Plagwitz, Frank Hannig, Jürgen Teich
2022	J	`jnl`	Task Migration Policy for Thermal-Aware Dynamic Performance Optimization in Many-Core Systems. IEEE Access Behnaz Pourmohseni, Stefan Wildermann, Fedor Smirnov, Paul E. Meyer, Jürgen Teich
2022	J	`jnl`	The HighPerMeshes framework for numerical algorithms on unstructured grids. Concurr. Comput. Pract. Exp. Samer Alhaddad, Jens Förstner, Stefan Groth, Daniel Grünewald, Yevgen Grynko, Frank Hannig, Tobias Kenter, Franz-Josef Pfreundt, Christian Plessl, Merlind Schotte, Thomas Steinke, Jürgen Teich, Martin Weiser, Florian Wende
2021	J	`jnl`	*-Predictable MPSoC execution of real-time control applications using invasive computing. Concurr. Comput. Pract. Exp. Marcel Brand, Michael Witterauf, Éricles Sousa, Alexandru Tanase, Frank Hannig, Jürgen Teich
2021	—	`conf`	A Comparative Evaluation of Latency-Aware Energy Optimization Approaches in Many-Core Systems (Invited Paper). NG-RES@HiPEAC Khalil Esper, Stefan Wildermann, Jürgen Teich
2021	Misc	`conf`	A Safari through FPGA-based Neural Network Compilation and Design Automation Flows. FCCM Patrick Plagwitz, Frank Hannig, Martin Ströbel, Christoph Strohmeyer, Jürgen Teich
2021	Misc	`conf`	Aarith: an arbitrary precision number library. SAC Oliver Keszöcze, Marcel Brand, Michael Witterauf, Christian Heidorn, Jürgen Teich
2021	J	`jnl`	Adaptive Predictive Power Management for Mobile LTE Devices. IEEE Trans. Mob. Comput. Peter Brand, Joachim Falk, Jonathan Ah Sue, Johannes Brendel, Ralph Hasholzner, Jürgen Teich
2021	—	`conf`	An Efficient Approach for Image Border Handling on GPUs via Iteration Space Partitioning. IPDPS Workshops Bo Qiao, Jürgen Teich, Frank Hannig
2021	A	`conf`	Approximate Logic Synthesis of Very Large Boolean Networks. DATE Jorge Echavarria, Stefan Wildermann, Jürgen Teich
2021	—	`conf`	CORSICA: A Framework for Conducting Real-World Side-Channel Analysis. NTMS Jens Schlumberger, Stefan Wildermann, Jürgen Teich
2021	B	`conf`	Choice - A Tunable PUF-Design for FPGAs. FPL Franz-Josef Streit, Paul Krüger, Andreas Becher, Jens Schlumberger, Stefan Wildermann, Jürgen Teich
2021	—	`conf`	Decision Tree-based Throughput Estimation to Accelerate Design Space Exploration for Multi-Core Applications. MBMV Martín Letras, Joachim Falk, Jürgen Teich
2021	A	`conf`	Design Space Exploration of Approximation-Based Quadruple Modular Redundancy Circuits. ICCAD Marcello Traiola, Jorge Echavarria, Alberto Bosio, Jürgen Teich, Ian O'Connor
2021	—	`conf`	Design Space Exploration of Time, Energy, and Error Rate Trade-offs for CNNs Using Accuracy-Programmable Instruction Set Processors. PKDD/ECML Workshops (1) Armin Schuster, Christian Heidorn, Marcel Brand, Oliver Keszöcze, Jürgen Teich
2021	—	`conf`	Domain-Adaptive Soft Real-Time Hybrid Application Mapping for MPSoCs. MLCAD Jan Spieck, Stefan Wildermann, Jürgen Teich
2021	C	`conf`	Efficient Application of Tensor Core Units for Convolving Images. SCOPES Stefan Groth, Jürgen Teich, Frank Hannig
2021	J	`jnl`	Efficient Computation of Probabilistic Dominance in Multi-objective Optimization. ACM Trans. Evol. Learn. Optim. Faramarz Khosravi, Alexander Raß, Jürgen Teich
2021	B	`conf`	Emerging Computing Devices: Challenges and Opportunities for Test and Reliability ETS Alberto Bosio, Ian O'Connor, Marcello Traiola, Jorge Echavarria, Jürgen Teich, Muhammad Abdullah Hanif, Muhammad Shafique, Said Hamdioui, Bastien Deveautour, Patrick Girard, Arnaud Virazel, Koen Bertels
2021	C	`conf`	Enforcement FSMs: specification and verification of non-functional properties of program executions on MPSoCs. MEMOCODE Khalil Esper, Stefan Wildermann, Jürgen Teich
2021	—	`conf`	Fault-Tolerant Low-Precision DNNs using Explainable AI. DSN Workshops Muhammad Sabih, Frank Hannig, Jürgen Teich
2021	B	`conf`	Hand Sign Recognition via Deep Learning on Tightly Coupled Processor Arrays. FPL Christian Heidorn, Dominik Walter, Yunus Emre Candir, Frank Hannig, Jürgen Teich
2021	J	`jnl`	HipaccVX: wedding of OpenVX and DSL-based code generation. J. Real Time Image Process. M. Akif Özkan, Burak Ok, Bo Qiao, Jürgen Teich, Frank Hannig
2021	C	`conf`	LION: real-time I/O transfer control for massively parallel processor arrays. MEMOCODE Dominik Walter, Jürgen Teich
2021	C	`conf`	Multi-Step Ahead Grant Prediction for Dynamic Power Management in Cellular Modems. ISNCC Peter Brand, Joachim Falk, Eduard Potwigin, Jürgen Teich
2021	J	`jnl`	Multi-objective Optimization of Mapping Dataflow Applications to MPSoCs Using a Hybrid Evaluation Combining Analytic Models and Measurements. ACM Trans. Design Autom. Electr. Syst. Martín Letras, Joachim Falk, Tobias Schwarzer, Jürgen Teich
2021	J	`jnl`	On the Approximation of Accuracy-configurable Sequential Multipliers via Segmented Carry Chains. CoRR Jorge Echavarria, Stefan Wildermann, Oliver Keszöcze, Faramarz Khosravi, Andreas Becher, Jürgen Teich
2021	J	`jnl`	Open Source Hardware. Computer Frank Hannig, Jürgen Teich
2021	—	`conf`	Providing Tamper-Secure SoC Updates Through Reconfigurable Hardware. ARC Franz-Josef Streit, Stefan Wildermann, Michael Pschyklenk, Jürgen Teich
2021	—	`conf`	Run-Time Enforcement of Non-functional Program Properties on MPSoCs. A Journey of Embedded and Cyber-Physical Systems Jürgen Teich, Pouya Mahmoody, Behnaz Pourmohseni, Sascha Roloff, Wolfgang Schröder-Preikschat, Stefan Wildermann
2021	—	`conf`	Simulating Realistic IoT Network Traffic Using Similarity-based DSE. CSCI Peter Brand, Joachim Falk, Tanja Maier, Jürgen Teich
2021	J	`jnl`	Speculative Dynamic Reconfiguration and Table Prefetching Using Query Look-Ahead in the ReProVide Near-Data-Processing System. Datenbank-Spektrum Lekshmi Beena Gopalakrishnan Nair, Andreas Becher, Stefan Wildermann, Klaus Meyer-Wegener, Jürgen Teich
2021	J	`jnl`	Symbolic Loop Compilation for Tightly Coupled Processor Arrays. CoRR Michael Witterauf, Dominik Walter, Frank Hannig, Jürgen Teich
2021	J	`jnl`	Symbolic Loop Compilation for Tightly Coupled Processor Arrays. ACM Trans. Embed. Comput. Syst. Michael Witterauf, Dominik Walter, Frank Hannig, Jürgen Teich
2020	J	`jnl`	A bibliometric approach for detecting the gender gap in computer science. Commun. ACM Sandra Mattauch, Katja Lohmann, Frank Hannig, Daniel Lohmann, Jürgen Teich
2020	—	`conf`	A runtime system for finite element methods in a partitioned global address space. CF Stefan Groth, Daniel Grünewald, Jürgen Teich, Frank Hannig
2020	J	`jnl`	AnyHLS: High-Level Synthesis With Partial Evaluation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. M. Akif Özkan, Arsène Pérard-Gayot, Richard Membarth, Philipp Slusallek, Roland Leißa, Sebastian Hack, Jürgen Teich, Frank Hannig
2020	J	`jnl`	AnyHLS: High-Level Synthesis with Partial Evaluation. CoRR M. Akif Özkan, Arsène Pérard-Gayot, Richard Membarth, Philipp Slusallek, Roland Leißa, Sebastian Hack, Jürgen Teich, Frank Hannig
2020	—	`conf`	Anytime Floating-Point Addition and Multiplication-Concepts and Implementations. ASAP Marcel Brand, Michael Witterauf, Alberto Bosio, Jürgen Teich
2020	B	`conf`	Clustering-Based Scenario-Aware LTE Grant Prediction. WCNC Peter Brand, Muhammad Sabih, Joachim Falk, Jonathan Ah Sue, Jürgen Teich
2020	C	`conf`	Design space exploration for layer-parallel execution of convolutional neural networks on CGRAs. SCOPES Christian Heidorn, Frank Hannig, Jürgen Teich
2020	C	`conf`	Efficient parallel reduction on GPUs with Hipacc. SCOPES Bo Qiao, Oliver Reiche, M. Akif Özkan, Jürgen Teich, Frank Hannig
2020	—	`conf`	Energy Minimization in DAG Scheduling on MPSoCs at Run-Time: Theory and Practice. NG-RES@HiPEAC Bertrand Simon, Joachim Falk, Nicole Megow, Jürgen Teich
2020	—	`ch.`	ExaStencils: Advanced Multigrid Solver Generation. Software for Exascale Computing Christian Lengauer, Sven Apel, Matthias Bolten, Shigeru Chiba, Ulrich Rüde, Jürgen Teich, Armin Größlinger, Frank Hannig, Harald Köstler, Lisa Claus, Alexander Grebhahn, Stefan Groth, Stefan Kronawitter, Sebastian Kuckuk, Hannah Rittich, Christian Schmitt, Jonas Schmitt
2020	—	`conf`	Exploration of Power Domain Partitioning with Concurrent Task Mapping and Scheduling for Application-Specific Multi-core SoCs. ARCS Bo Wang, Aneek Imtiaz, Joachim Falk, Michael Glaß, Jürgen Teich
2020	—	`conf`	Hardware Implementation of Hyperbolic Tangent Activation Function for Floating Point Formats. VDAT Arvind Thumatti K. R., Marcel Brand, Christian Heidorn, Srinivas Boppu, Frank Hannig, Jürgen Teich
2020	—	`conf`	HighPerMeshes - A Domain-Specific Language for Numerical Algorithms on Unstructured Grids. Euro-Par Workshops Samer Alhaddad, Jens Förstner, Stefan Groth, Daniel Grünewald, Yevgen Grynko, Frank Hannig, Tobias Kenter, Franz-Josef Pfreundt, Christian Plessl, Merlind Schotte, Thomas Steinke, Jürgen Teich, Martin Weiser, Florian Wende
2020	J	`jnl`	HipaccVX: Wedding of OpenVX and DSL-based Code Generation. CoRR M. Akif Özkan, Burak Ok, Bo Qiao, Jürgen Teich, Frank Hannig
2020	A*	`conf`	Probabilistic Error Propagation through Approximated Boolean Networks. DAC Jorge Echavarria, Stefan Wildermann, Oliver Keszöcze, Jürgen Teich
2020	—	`conf`	Real-Time Task Migration for Dynamic Resource Management in Many-Core Systems. NG-RES@HiPEAC Behnaz Pourmohseni, Fedor Smirnov, Stefan Wildermann, Jürgen Teich
2020	C	`conf`	Real-time Scheduling of I/O Transfers for Massively Parallel Processor Arrays. MEMOCODE Dominik Walter, Michael Witterauf, Jürgen Teich
2020	—	`conf`	Run-Time Enforcement of Non-Functional Application Requirements in Heterogeneous Many-Core Systems. ASP-DAC Jürgen Teich, Behnaz Pourmohseni, Oliver Keszöcze, Jan Spieck, Stefan Wildermann
2020	B	`conf`	SQL Query Processing Using an Integrated FPGA-based Near-Data Accelerator in ReProVide. EDBT Lekshmi B. G., Andreas Becher, Klaus Meyer-Wegener, Stefan Wildermann, Jürgen Teich
2020	A*	`conf`	Scenario-Based Soft Real-Time Hybrid Application Mapping for MPSoCs. DAC Jan Spieck, Stefan Wildermann, Jürgen Teich
2020	—	`conf`	Secure Boot from Non-Volatile Memory for Programmable SoC Architectures. HOST Franz-Josef Streit, Florian Fritz, Andreas Becher, Stefan Wildermann, Stefan Werner, Martin Schmidt-Korth, Michael Pschyklenk, Jürgen Teich
2020	J	`jnl`	Secure Boot from Non-Volatile Memory for Programmable SoC Architectures. CoRR Franz-Josef Streit, Florian Fritz, Andreas Becher, Stefan Wildermann, Stefan Werner, Martin Schmidt-Korth, Michael Pschyklenk, Jürgen Teich
2020	A*	`conf`	The Best of Both Worlds: Combining CUDA Graph with an Image Processing DSL. DAC Bo Qiao, M. Akif Özkan, Jürgen Teich, Frank Hannig
2020	—	`conf`	Unveiling kernel concurrency in multiresolution filters on GPUs with an image processing DSL. GPGPU@PPoPP Bo Qiao, Oliver Reiche, Jürgen Teich, Frank Hannig
2020	A	`conf`	Using Learning Classifier Systems for the DSE of Adaptive Embedded Systems. DATE Fedor Smirnov, Behnaz Pourmohseni, Jürgen Teich
2020	J	`jnl`	Utilizing Explainable AI for Quantization and Pruning of Deep Neural Networks. CoRR Muhammad Sabih, Frank Hannig, Jürgen Teich
2019	J	`jnl`	Adaptive Predictive Power Management for Mobile LTE Devices. CoRR Peter Brand, Joachim Falk, Jonathan Ah Sue, Johannes Brendel, Ralph Hasholzner, Jürgen Teich
2019	—	`conf`	Anytime instructions for programmable accuracy floating-point arithmetic. CF Marcel Brand, Michael Witterauf, Frank Hannig, Jürgen Teich
2019	J	`jnl`	Automatic Optimization of the VLAN Partitioning in Automotive Communication Networks. ACM Trans. Design Autom. Electr. Syst. Fedor Smirnov, Felix Reimann, Jürgen Teich, Michael Glaß
2019	J	`jnl`	Compilation of Dataflow Applications for Multi-Cores using Adaptive Multi-Objective Optimization. ACM Trans. Design Autom. Electr. Syst. Tobias Schwarzer, Joachim Falk, Simone Müller, Martín Letras, Christian Heidorn, Stefan Wildermann, Jürgen Teich
2019	—	`conf`	Compiler-Based High-Level Synthesis of Application-Specific Processors on FPGAs. ReConFig Patrick Plagwitz, Franz-Josef Streit, Andreas Becher, Stefan Wildermann, Jürgen Teich
2019	J	`jnl`	Conference Reports: Recap of DATE 2019 in Florence, Italy. IEEE Des. Test Jürgen Teich, Franco Fummi
2019	—	`conf`	DSL-Based Acceleration of Automotive Environment Perception and Mapping Algorithms for Embedded CPUs, GPUs, and FPGAs. ARCS Jörg Fickenscher, Frank Hannig, Jürgen Teich
2019	—	`conf`	Data-Driven Scenario-Based Application Mapping for Heterogeneous Many-Core Systems. MCSoC Jan Spieck, Stefan Wildermann, Tobias Schwarzer, Jürgen Teich, Michael Glaß
2019	A	`ed.`	Design, Automation & Test in Europe Conference & Exhibition, DATE 2019, Florence, Italy, March 25-29, 2019 DATE Jürgen Teich, Franco Fummi
2019	J	`jnl`	Efficient Computation of Probabilistic Dominance in Robust Multi-Objective Optimization. CoRR Faramarz Khosravi, Alexander Raß, Jürgen Teich
2019	J	`jnl`	Efficient Mapping of CNNs onto Tightly Coupled Processor Arrays. J. Comput. Christian Heidorn, Michael Witterauf, Frank Hannig, Jürgen Teich
2019	J	`jnl`	Efficient Mapping of Streaming Applications for Image Processing on Graphics Cards. Trans. High Perform. Embed. Archit. Compil. Richard Membarth, Hritam Dutta, Frank Hannig, Jürgen Teich
2019	—	`conf`	Efficient Symbolic Routing Encoding for In-vehicle Network Optimization. SMARTGREENS/VEHITS (Selected Papers) Fedor Smirnov, Behnaz Pourmohseni, Michael Glaß, Jürgen Teich
2019	A	`conf`	Efficient Treatment of Uncertainty in System Reliability Analysis using Importance Measures. DSN Hananeh Aliee, Faramarz Khosravi, Jürgen Teich
2019	J	`jnl`	Energy Minimization in DAG Scheduling on MPSoCs at Run-Time: Theory and Practice. CoRR Bertrand Simon, Joachim Falk, Nicole Megow, Jürgen Teich
2019	A	`conf`	From Loop Fusion to Kernel Fusion: A Domain-Specific Approach to Locality Optimization. CGO Bo Qiao, Oliver Reiche, Frank Hannig, Jürgen Teich
2019	J	`jnl`	Hard real-time application mapping reconfiguration for NoC-based many-core systems. Real Time Syst. Behnaz Pourmohseni, Stefan Wildermann, Michael Glaß, Jürgen Teich
2019	J	`jnl`	IGOR, Get Me the Optimum! Prioritizing Important Design Decisions During the DSE of Embedded Systems. ACM Trans. Embed. Comput. Syst. Fedor Smirnov, Behnaz Pourmohseni, Michael Glaß, Jürgen Teich
2019	C	`conf`	In situ Statistics Generation within partially reconfigurable Hardware Accelerators for Query Processing. DaMoN Andreas Becher, Jürgen Teich
2019	B	`conf`	Isolation-Aware Timing Analysis and Design Space Exploration for Predictable and Composable Many-Core Systems. ECRTS Behnaz Pourmohseni, Fedor Smirnov, Stefan Wildermann, Jürgen Teich
2019	J	`jnl`	Isolation-Aware Timing Analysis and Design Space Exploration for Predictable and Composable Many-Core Systems. CoRR Behnaz Pourmohseni, Fedor Smirnov, Stefan Wildermann, Jürgen Teich
2019	—	`book`	Modeling and Simulation of Invasive Applications and Architectures. Sascha Roloff, Frank Hannig, Jürgen Teich
2019	C	`conf`	On the Analytic Evaluation of Schedules via Max-Plus Algebra for DSE of Multi-Core Architectures. SCOPES Martín Letras, Joachim Falk, Tobias Schwarzer, Jürgen Teich
2019	—	`conf`	Optimizing Exploratory Workflows for Embedded Platform Trace Analysis and Its Application to Mobile Devices. HCI (LBP) Jonathan Ah Sue, Peter Brand, Joachim Falk, Ralph Hasholzner, Jürgen Teich
2019	C	`conf`	Polyhedral fragments: an efficient representation for symbolically generating code for processor arrays. MEMOCODE Michael Witterauf, Frank Hannig, Jürgen Teich
2019	—	`conf`	ReProVide: Towards Utilizing Heterogeneous Partially Reconfigurable Architectures for Near-Memory Data Processing. BTW (Workshops) Andreas Becher, Achim Herrmann, Stefan Wildermann, Jürgen Teich
2019	C	`conf`	SYCL Code Generation for Multigrid Methods. SCOPES Stefan Groth, Christian Schmitt, Jürgen Teich, Frank Hannig
2019	A	`conf`	Thermally Composable Hybrid Application Mapping for Real-Time Applications in Heterogeneous Many-Core Systems. RTSS Behnaz Pourmohseni, Fedor Smirnov, Heba Khdr, Stefan Wildermann, Jürgen Teich, Jörg Henkel
2019	C	`conf`	Variety-aware Routing Encoding for Efficient Design Space Exploration of Automotive Communication Networks. VEHITS Fedor Smirnov, Behnaz Pourmohseni, Michael Glaß, Jürgen Teich
2018	J	`jnl`	A Design-Time/Run-Time Application Mapping Methodology for Predictable Execution Time in MPSoCs. ACM Trans. Embed. Comput. Syst. Andreas Weichslgartner, Stefan Wildermann, Deepak Gangadharan, Michael Glaß, Jürgen Teich
2018	B	`conf`	A predictive dynamic power management for LTE-Advanced mobile devices. WCNC Jonathan Ah Sue, Peter Brand, Johannes Brendel, Ralph Hasholzner, Joachim Falk, Jürgen Teich
2018	—	`conf`	AConFPGA: A Multiple-Output Boolean Function Approximation DSE Technique Targeting FPGAs. FPT Jorge Echavarria, Stefan Wildermann, Jürgen Teich
2018	A*	`conf`	Architecture decomposition in system synthesis of heterogeneous many-core systems. DAC Valentina Richthammer, Tobias Schwarzer, Stefan Wildermann, Jürgen Teich, Michael Glaß
2018	C	`conf`	Automatic Kernel Fusion for Image Processing DSLs. SCOPES Bo Qiao, Oliver Reiche, Frank Hannig, Jürgen Teich
2018	C	`conf`	Automatic Optimization of Redundant Message Routings in Automotive Networks. SCOPES Fedor Smirnov, Felix Reimann, Jürgen Teich, Zhao Han, Michael Glaß
2018	J	`jnl`	Automating the Development of High-Performance Multigrid Solvers. Proc. IEEE Christian Schmitt, Stefan Kronawitter, Frank Hannig, Jürgen Teich, Christian Lengauer
2018	C	`conf`	Base Algorithms of Environment Maps and Efficient Occupancy Grid Mapping on Embedded GPUs. VEHITS Jörg Fickenscher, Frank Hannig, Jürgen Teich, Mohamed Essayed Bouzouraa
2018	—	`conf`	Can Approximate Computing Reduce Power Consumption on FPGAs? ICECS Jorge Echavarria, Katja Schutz, Andreas Becher, Stefan Wildermann, Jürgen Teich
2018	A	`conf`	Cell-based update algorithm for occupancy grid maps and hybrid map for ADAS on embedded GPUs. DATE Jörg Fickenscher, Jens Schlumberger, Frank Hannig, Jürgen Teich, Mohamed Essayed Bouzouraa
2018	—	`conf`	Configuration Tampering of BRAM-based AES Implementations on FPGAs. ReConFig Daniel Ziener, Jutta Pirkl, Jürgen Teich
2018	A	`conf`	Design space exploration of multi-output logic function approximations. ICCAD Jorge Echavarria, Stefan Wildermann, Jürgen Teich
2018	A	`conf`	Dynamic resource management for heterogeneous many-cores. ICCAD Jörg Henkel, Jürgen Teich, Stefan Wildermann, Hussam Amrouch
2018	J	`jnl`	Efficient Arithmetic Error Rate Calculus for Visibility Reduced Approximate Adders. IEEE Embed. Syst. Lett. Jorge Echavarria, Stefan Wildermann, Eduard Potwigin, Jürgen Teich
2018	J	`jnl`	Guest Editors' Introduction: Special Issue on Time-Critical Systems Design Part II. IEEE Des. Test Tulika Mitra, Jürgen Teich, Lothar Thiele
2018	J	`jnl`	Guest Editors' Introduction: Special Issue on Time-Critical Systems Design. IEEE Des. Test Tulika Mitra, Jürgen Teich, Lothar Thiele
2018	J	`jnl`	Integration of FPGAs in Database Management Systems: Challenges and Opportunities. Datenbank-Spektrum Andreas Becher, Lekshmi B. G., David Broneske, Tobias Drewes, Bala Gurumurthy, Klaus Meyer-Wegener, Thilo Pionteck, Gunter Saake, Jürgen Teich, Stefan Wildermann
2018	—	`book`	Invasive Computing for Mapping Parallel Programs to Many-Core Architectures. Andreas Weichslgartner, Stefan Wildermann, Michael Glaß, Jürgen Teich
2018	—	`conf`	Invasive Computing for Predictability of Multiple Non-functional Properties: A Cyber-Physical System Case Study. ASAP Éricles Sousa, Michael Witterauf, Marcel Brand, Alexandru Tanase, Frank Hannig, Jürgen Teich
2018	J	`jnl`	Loop Parallelization Techniques for FPGA Accelerator Synthesis. J. Signal Process. Syst. Oliver Reiche, M. Akif Ozkan, Frank Hannig, Jürgen Teich, Moritz Schmid
2018	—	`conf`	Model-Based Design Automation of Hardware/Software Co-Designs for Xilinx Zynq PSoCs. ReConFig Franz-Josef Streit, Martín Letras, Stefan Wildermann, Benjamin Hackenberg, Joachim Falk, Andreas Becher, Jürgen Teich
2018	—	`conf`	On the Complexity of Mapping Feasibility in Many-Core Architectures. MCSoC Tobias Schwarzer, Sascha Roloff, Valentina Richthammer, Rami Khaldi, Stefan Wildermann, Michael Glaß, Jürgen Teich
2018	C	`conf`	Optimistic regular expression matching on FPGAs for near-data processing. DaMoN Andreas Becher, Stefan Wildermann, Jürgen Teich
2018	B	`conf`	Probabilistic Dominance in Robust Multi-Objective Optimization. CEC Faramarz Khosravi, Michael Borst, Jürgen Teich
2018	J	`jnl`	Reconfigurable Hardware Generation of Multigrid Solvers with Conjugate Gradient Coarse-Grid Solution. Parallel Process. Lett. Christian Schmitt, Moritz Schmid, Sebastian Kuckuk, Harald Köstler, Jürgen Teich, Frank Hannig
2018	C	`conf`	Reinforcement Learning for Power-Efficient Grant Prediction in LTE. SCOPES Peter Brand, Joachim Falk, Jonathan Ah Sue, Johannes Brendel, Ralph Hasholzner, Jürgen Teich
2018	C	`conf`	Run-time Requirement Enforcement for Loop Programs on Processor Arrays. MEMOCODE Michael Witterauf, Jürgen Teich
2018	—	`conf`	Solving Maxwell's Equations with Modern C++ and SYCL: A Case Study. ASAP Ayesha Afzal, Christian Schmitt, Samer Alhaddad, Yevgen Grynko, Jürgen Teich, Jens Förstner, Frank Hannig
2018	J	`jnl`	Symbolic Multi-Level Loop Mapping of Loop Programs for Massively Parallel Processor Arrays. ACM Trans. Embed. Comput. Syst. Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig
2018	—	`book`	Symbolic Parallelization of Nested Loop Programs Alexandru-Petru Tanase, Frank Hannig, Jürgen Teich
2018	J	`jnl`	Symmetry-Eliminating Design Space Exploration for Hybrid Application Mapping on Many-Core Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tobias Schwarzer, Andreas Weichslgartner, Michael Glaß, Stefan Wildermann, Peter Brand, Jürgen Teich
2018	J	`jnl`	Time-Critical Systems Design: A Survey. IEEE Des. Test Tulika Mitra, Jürgen Teich, Lothar Thiele
2017	J	`jnl`	A Design-Time/Run-Time Application Mapping Methodology for Predictable Execution Time in MPSoCs. CoRR Andreas Weichslgartner, Stefan Wildermann, Deepak Gangadharan, Michael Glaß, Jürgen Teich
2017	J	`jnl`	A Novel Image Impulse Noise Removal Algorithm Optimized for Hardware Accelerators. J. Signal Process. Syst. Vivek Singh Bhadouria, Alexandru Tanase, Moritz Schmid, Frank Hannig, Jürgen Teich, Dibyendu Ghoshal
2017	J	`jnl`	A Scala prototype to generate multigrid solver implementations for different problems and target multi-core platforms. Int. J. Comput. Sci. Eng. Harald Köstler, Christian Schmitt, Sebastian Kuckuk, Stefan Kronawitter, Frank Hannig, Jürgen Teich, Ulrich Rüde, Christian Lengauer
2017	—	`conf`	A reconfigurable memory architecture for system integration of coarse-grained reconfigurable arrays. ReConFig Éricles Sousa, Alexandru Tanase, Frank Hannig, Jürgen Teich
2017	B	`conf`	Auto-vectorization for image processing DSLs. LCTES Oliver Reiche, Christof Kobylko, Frank Hannig, Jürgen Teich
2017	C	`conf`	Automatic Conversion of Simulink Models to SysteMoC Actor Networks. SCOPES Martín Letras, Joachim Falk, Stefan Wildermann, Jürgen Teich
2017	J	`jnl`	Automatic Reliability Analysis in the Presence of Probabilistic Common Cause Failures. IEEE Trans. Reliab. Faramarz Khosravi, Michael Glaß, Jürgen Teich
2017	A	`conf`	Automatic operating point distillation for hybrid mapping methodologies. DATE Behnaz Pourmohseni, Michael Glaß, Jürgen Teich
2017	C	`conf`	Constructing fast and cycle-accurate simulators for configurable accelerators using C++ templates. RSP Michael Witterauf, Frank Hannig, Jürgen Teich
2017	B	`conf`	Convoy tracking for ADAS on embedded GPUs. Intelligent Vehicles Symposium Jörg Fickenscher, Sebastian Reinhart, Frank Hannig, Jürgen Teich, Mohamed Essayed Bouzouraa
2017	—	`conf`	Efficiency in ILP processing by using orthogonality. ASAP Marcel Brand, Frank Hannig, Alexandru Tanase, Jürgen Teich
2017	J	`jnl`	Efficient task spawning for shared memory and message passing in many-core architectures. J. Syst. Archit. Aurang Zaib, Thomas Wild, Andreas Herkersdorf, Jan Heisswolf, Jürgen Becker, Andreas Weichslgartner, Jürgen Teich
2017	C	`conf`	Exploiting Predictability in Dynamic Network Communication for Power-Efficient Data Transmission in LTE Radio Systems. SCOPES Peter Brand, Jonathan Ah Sue, Johannes Brendel, Joachim Falk, Ralph Hasholzner, Jürgen Teich, Stefan Wildermann
2017	A	`conf`	Formal timing analysis of non-scheduled traffic in automotive scheduled TSN networks. DATE Fedor Smirnov, Michael Glaß, Felix Reimann, Jürgen Teich
2017	A	`conf`	Generating FPGA-based image processing accelerators with Hipacc: (Invited paper). ICCAD Oliver Reiche, M. Akif Ozkan, Richard Membarth, Jürgen Teich, Frank Hannig
2017	—	`book`	Handbook of Hardware/Software Codesign. Handbook of Hardware/Software Codesign Soonhoi Ha, Jürgen Teich
2017	—	`conf`	Hardware design and analysis of efficient loop coarsening and border handling for image processing. ASAP M. Akif Ozkan, Oliver Reiche, Frank Hannig, Jürgen Teich
2017	—	`conf`	High performance network-on-chip simulation by interval-based timing predictions. ESTIMedia Sascha Roloff, Frank Hannig, Jürgen Teich
2017	—	`conf`	High-Level Synthesis for Hardware/Software Co-Design of Distributed Smart Camera Systems. ICDSC Franz-Josef Streit, Martín Letras, Matthias Schid, Joachim Falk, Stefan Wildermann, Jürgen Teich
2017	—	`ch.`	Hybrid Optimization Techniques for System-Level Design Space Exploration. Handbook of Hardware/Software Codesign Michael Glaß, Jürgen Teich, Martin Lukasiewycz, Felix Reimann
2017	—	`ch.`	Introduction to Hardware/Software Codesign. Handbook of Hardware/Software Codesign Soonhoi Ha, Jürgen Teich, Christian Haubelt, Michael Glaß, Tulika Mitra, Rainer Dömer, Petru Eles, Aviral Shrivastava, Andreas Gerstlauer, Shuvra S. Bhattacharyya
2017	J	`jnl`	Noc-HMP: A Heterogeneous Multicore Processor for Embedded Systems Designed in SystemJ. ACM Trans. Design Autom. Electr. Syst. Zoran Salcic, HeeJong Park, Jürgen Teich, Avinash Malik, Muhammad Nadeem
2017	J	`jnl`	On the Boolean extension of the Birnbaum importance to non-coherent systems. Reliab. Eng. Syst. Saf. Hananeh Aliee, Emanuele Borgonovo, Michael Glaß, Jürgen Teich
2017	A*	`conf`	Optimizing Message Routing and Scheduling in Automotive Mixed-Criticality Time-Triggered Networks. DAC Fedor Smirnov, Michael Glaß, Felix Reimann, Jürgen Teich
2017	J	`jnl`	Optimizing Scrubbing by Netlist Analysis for FPGA Configuration Bit Classification and Floorplanning. CoRR Bernhard Schmidt, Daniel Ziener, Jürgen Teich, Christian Zöllner
2017	J	`jnl`	Optimizing scrubbing by netlist analysis for FPGA configuration bit classification and floorplanning. Integr. Bernhard Schmidt, Daniel Ziener, Jürgen Teich, Christian Zöllner
2017	—	`conf`	Orthogonal Instruction Processing: An Alternative to Lightweight VLIW Processors. MCSoC Marcel Brand, Frank Hannig, Alexandru Tanase, Jürgen Teich
2017	J	`jnl`	Power Density-Aware Resource Management for Heterogeneous Tiled Multicores. IEEE Trans. Computers Heba Khdr, Santiago Pagani, Éricles Sousa, Vahid Lari, Anuj Pathania, Frank Hannig, Muhammad Shafique, Jürgen Teich, Jörg Henkel
2017	Misc	`conf`	Predictable run-time mapping reconfiguration for real-time applications on many-core systems. RTNS Behnaz Pourmohseni, Stefan Wildermann, Michael Glaß, Jürgen Teich
2017	—	`conf`	Redundancy-aware Design Space Exploration for Memory Reliability in Many-cores. MBMV Hananeh Aliee, Abbas BanaiyanMofrad, Michael Glaß, Jürgen Teich, Nikil D. Dutt
2017	C	`conf`	Self-Adaptive FPGA-Based Image Processing Filters Using Approximate Arithmetics. SCOPES Jutta Pirkl, Andreas Becher, Jorge Echavarria, Jürgen Teich, Stefan Wildermann
2017	—	`ch.`	SysteMoC: A Data-Flow Programming Language for Codesign. Handbook of Hardware/Software Codesign Joachim Falk, Christian Haubelt, Jürgen Teich, Christian Zebelein
2017	—	`conf`	System-level reliability analysis considering imperfect fault coverage. ESTIMedia Faramarz Khosravi, Hananeh Aliee, Jürgen Teich
2017	—	`conf`	TCPA editor: A design automation environment for a class of coarse-grained reconfigurable arrays. ReConFig Éricles Sousa, Arindam Chakraborty, Alexandru Tanase, Frank Hannig, Jürgen Teich
2017	J	`jnl`	Towards the co-evolution of industrial products and its production systems by combining models from development and hardware/software deployment in cyber-physical systems. Prod. Eng. Birgit Vogel-Heuser, Stefan Wildermann, Jürgen Teich
2017	J	`jnl`	Using design space exploration for finding schedules with guaranteed reaction times of synchronous programs on multi-core architecture. J. Syst. Archit. Zhenmin Li, HeeJong Park, Avinash Malik, Kevin I-Kai Wang, Zoran Salcic, Boris Kuzmin, Michael Glaß, Jürgen Teich
2016	A	`ed.`	2016 Design, Automation & Test in Europe Conference & Exhibition, DATE 2016, Dresden, Germany, March 14-18, 2016 DATE Luca Fanucci, Jürgen Teich
2016	—	`conf`	A Binary Time Series Model of LTE Scheduling for Machine Learning Prediction. FAS*W@SASO/ICCAC Jonathan Ah Sue, Ralph Hasholzner, Johannes Brendel, Martin Kleinsteuber, Jürgen Teich
2016	Misc	`conf`	A LUT-Based Approximate Adder. FCCM Andreas Becher, Jorge Echavarria, Daniel Ziener, Stefan Wildermann, Jürgen Teich
2016	C	`conf`	A heterogeneous multi-core SoC for mixed criticality industrial automation systems. ETFA Zoran A. Salcic, Muhammad Nadeem, HeeJong Park, Jürgen Teich
2016	J	`jnl`	A new time-independent reliability importance measure. Eur. J. Oper. Res. Emanuele Borgonovo, Hananeh Aliee, Michael Glaß, Jürgen Teich
2016	—	`conf`	ActorX10: an actor library for X10. X10@PLDI Sascha Roloff, Alexander Pöppl, Tobias Schwarzer, Stefan Wildermann, Michael Bader, Michael Glaß, Frank Hannig, Jürgen Teich
2016	J	`jnl`	Adaptive Isolation for Predictability and Security (Dagstuhl Seminar 16441). Dagstuhl Reports Tulika Mitra, Jürgen Teich, Lothar Thiele
2016	—	`conf`	Analysis and Exploitation of CTU-Level Parallelism in the HEVC Mode Decision Process Using Actor-Based Modeling. ARCS Rafael Rosales, Christian Herglotz, Michael Glaß, André Kaup, Jürgen Teich
2016	—	`ed.`	Architecture of Computing Systems - ARCS 2016 - 29th International Conference, Nuremberg, Germany, April 4-7, 2016, Proceedings ARCS Frank Hannig, João M. P. Cardoso, Thilo Pionteck, Dietmar Fey, Wolfgang Schröder-Preikschat, Jürgen Teich
2016	C	`conf`	Design-Time/Run-Time Mapping of Security-Critical Applications in Heterogeneous MPSoCs. SCOPES Andreas Weichslgartner, Stefan Wildermann, Johannes Götzfried, Felix C. Freiling, Michael Glaß, Jürgen Teich
2016	—	`conf`	Exploration of Power Domain Partitioning for Application-Specific SoCs in System-Level Design. MBMV Bo Wang, Yang Xu, Ralph Hasholzner, Christian Drewes, Rafael Rosales, Sebastian Graf, Joachim Falk, Michael Glaß, Jürgen Teich
2016	—	`conf`	FAU: Fast and error-optimized approximate adder units on LUT-Based FPGAs. FPT Jorge Echavarria, Stefan Wildermann, Andreas Becher, Jürgen Teich, Daniel Ziener
2016	J	`jnl`	FPGA-Based Dynamically Reconfigurable SQL Query Processing. ACM Trans. Reconfigurable Technol. Syst. Daniel Ziener, Florian Bauer, Andreas Becher, Christopher Dennl, Klaus Meyer-Wegener, Ute Schürfeld, Jürgen Teich, Jörg-Stephan Vogt, Helmut Weber
2016	B	`conf`	FPGA-based accelerator design from a domain-specific language. FPL M. Akif Ozkan, Oliver Reiche, Frank Hannig, Jürgen Teich
2016	A*	`conf`	Formal reliability analysis of switched ethernet automotive networks under transient transmission errors. DAC Fedor Smirnov, Michael Glaß, Felix Reimann, Jürgen Teich
2016	—	`conf`	Guiding Genetic Algorithms using importance measures for reliable design of embedded systems. DFT Hananeh Aliee, Stefan Vitzethum, Michael Glaß, Jürgen Teich, Emanuele Borgonovo
2016	—	`ch.`	HIPA FPGAs for Software Programmers Moritz Schmid, Oliver Reiche, Frank Hannig, Jürgen Teich
2016	J	`jnl`	HIPA IEEE Trans. Parallel Distributed Syst. Richard Membarth, Oliver Reiche, Frank Hannig, Jürgen Teich, Mario Körner, Wieland Eckert
2016	J	`jnl`	Hierarchical Statistical Leakage Analysis and Its Application. ACM Trans. Design Autom. Electr. Syst. Yang Xu, Jürgen Teich
2016	—	`conf`	Hybrid code description for developing fast and resource efficient image processing architectures. SAMOS Konrad Häublein, Marc Reichenbach, Oliver Reiche, M. Akif Ozkan, Dietmar Fey, Frank Hannig, Jürgen Teich
2016	—	`conf`	Hybrid energy-aware reconfiguration management on Xilinx Zynq SoCs. ReConFig Andreas Becher, Jutta Pirkl, Achim Herrmann, Jürgen Teich, Stefan Wildermann
2016	J	`jnl`	Invasive computing for timing-predictable stream processing on MPSoCs. it Inf. Technol. Stefan Wildermann, Michael Bader, Lars Bauer, Marvin Damschen, Dirk Gabriel, Michael Gerndt, Michael Glaß, Jörg Henkel, Johny Paul, Alexander Pöppl, Sascha Roloff, Tobias Schwarzer, Gregor Snelting, Walter Stechele, Jürgen Teich, Andreas Weichslgartner, Andreas Zwinkau
2016	J	`jnl`	Invasive computing. it Inf. Technol. Jürgen Teich
2016	—	`conf`	Language and Compilation of Parallel Programs for *-Predictable MPSoC Execution Using Invasive Computing. MCSoC Jürgen Teich, Michael Glaß, Sascha Roloff, Wolfgang Schröder-Preikschat, Gregor Snelting, Andreas Weichslgartner, Stefan Wildermann
2016	—	`conf`	Modeling, programming and performance analysis of automotive environment map representations on embedded GPUs. HLDVT Jörg Fickenscher, Oliver Reiche, Jens Schlumberger, Frank Hannig, Jürgen Teich
2016	—	`conf`	Modulo scheduling of symbolically tiled loops for tightly coupled processor arrays. ASAP Michael Witterauf, Alexandru Tanase, Frank Hannig, Jürgen Teich
2016	C	`conf`	Multi-objective design space exploration for the optimization of the HEVC mode decision process. PCS Christian Herglotz, Rafael Rosales, Michael Glaß, Jürgen Teich, André Kaup
2016	—	`conf`	Optimizing Latencies and Customizing NoC of Time-Predictable Heterogeneous Multi-core Processor. MCSoC Zoran A. Salcic, Muhammad Nadeem, HeeJong Park, Jürgen Teich
2016	J	`jnl`	Providing fault tolerance through invasive computing. it Inf. Technol. Vahid Lari, Andreas Weichslgartner, Alexandru Tanase, Michael Witterauf, Faramarz Khosravi, Jürgen Teich, Jan Heißwolf, Stephanie Friederich, Jürgen Becker
2016	—	`conf`	ReOrder: Runtime datapath generation for high-throughput multi-stream processing. ReConFig Andreas Becher, Stefan Wildermann, Moritz Mühlenthaler, Jürgen Teich
2016	J	`jnl`	Recap of the 2016 DATE Conference & Exhibition. IEEE Des. Test Luca Fanucci, Jürgen Teich
2016	—	`ch.`	Systems of Partial Differential Equations in ExaSlang. Software for Exascale Computing Christian Schmitt, Sebastian Kuckuk, Frank Hannig, Jürgen Teich, Harald Köstler, Ulrich Rüde, Christian Lengauer
2015	—	`conf`	A co-design approach for accelerated SQL query processing via FPGA-based data filtering. FPT Andreas Becher, Daniel Ziener, Klaus Meyer-Wegener, Jürgen Teich
2015	—	`conf`	A co-design approach for fault-tolerant loop execution on Coarse-Grained Reconfigurable Arrays. AHS Vahid Lari, Alexandru Tanase, Jürgen Teich, Michael Witterauf, Faramarz Khosravi, Frank Hannig, Brett H. Meyer
2015	C	`conf`	Adaptive Isolation for Predictable MPSoC Stream Processing. SCOPES Jürgen Teich
2015	—	`conf`	Adaptive fault tolerance through invasive computing. AHS Michael Witterauf, Alexandru Tanase, Jürgen Teich, Vahid Lari, Andreas Zwinkau, Gregor Snelting
2015	J	`jnl`	Application-aware cross-layer reliability analysis and optimization. it Inf. Technol. Michael Glaß, Hananeh Aliee, Liang Chen, Mojtaba Ebrahimi, Faramarz Khosravi, Veit B. Kleeberger, Alexandra Listl, Daniel Müller-Gritschneder, Fabian Oboril, Ulf Schlichtmann, Mehdi Baradaran Tahoori, Jürgen Teich, Norbert Wehn, Christian Weis
2015	J	`jnl`	Automatic Optimization of Hardware Accelerators for Image Processing. CoRR Oliver Reiche, Konrad Häublein, Marc Reichenbach, Frank Hannig, Jürgen Teich, Dietmar Fey
2015	J	`jnl`	Automatic communication-driven virtual prototyping and design for networked embedded systems. Microprocess. Microsystems Joachim Falk, Tobias Schwarzer, Liyuan Zhang, Michael Glaß, Jürgen Teich
2015	—	`conf`	Design Methodology and Run-Time Management for Predictable Many-Core Systems. ISORC Workshops Stefan Wildermann, Andreas Weichslgartner, Jürgen Teich
2015	A*	`conf`	Execution-driven parallel simulation of PGAS applications on heterogeneous tiled architectures. DAC Sascha Roloff, David Schafhauser, Frank Hannig, Jürgen Teich
2015	—	`conf`	Fault-tolerant communication in invasive networks on chip. AHS Jan Heisswolf, Andreas Weichslgartner, Aurang Zaib, Stephanie Friederich, Leonard Masing, Carsten Stein, Marco Duden, Roman Klopfer, Jürgen Teich, Thomas Wild, Andreas Herkersdorf, Jürgen Becker
2015	A	`conf`	Formal analysis of the startup delay of SOME/IP service discovery. DATE Jan R. Seyler, Thilo Streichert, Michael Glaß, Nicolas Navet, Jürgen Teich
2015	—	`conf`	Invasive computing for predictable stream processing: a simulation-based case study. ESTIMedia Sascha Roloff, Stefan Wildermann, Frank Hannig, Jürgen Teich
2015	—	`conf`	Loop coarsening in C-based High-Level Synthesis. ASAP Moritz Schmid, Oliver Reiche, Frank Hannig, Jürgen Teich
2015	—	`conf`	Network Interface with Task Spawning Support for NoC-Based DSM Architectures. ARCS Aurang Zaib, Jan Heißwolf, Andreas Weichslgartner, Thomas Wild, Jürgen Teich, Jürgen Becker, Andreas Herkersdorf
2015	—	`conf`	On-demand fault-tolerant loop processing on massively parallel processor arrays. ASAP Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig, Vahid Lari
2015	—	`conf`	Quasi-static scheduling of data flow graphs in the presence of limited channel capacities. ESTIMedia Joachim Falk, Tobias Schwarzer, Michael Glaß, Jürgen Teich, Christian Zebelein, Christian Haubelt
2015	—	`conf`	Reconfigurable Buffer Structures for Coarse-Grained Reconfigurable Arrays. IESS Éricles Sousa, Frank Hannig, Jürgen Teich
2015	—	`conf`	Reliability of space-grade vs. COTS SRAM-based FPGA in N-modular redundancy. AHS Robért Glein, Florian Rittner, Andreas Becher, Daniel Ziener, Jürgen Frickel, Jürgen Teich, Albert Heuberger
2015	J	`jnl`	Resource-awareness on heterogeneous MPSoCs for image processing. J. Syst. Archit. Johny Paul, Walter Stechele, Benjamin Oechslein, Christoph Erhardt, Jens Schedel, Daniel Lohmann, Wolfgang Schröder-Preikschat, Manfred Kröhnert, Tamim Asfour, Éricles Sousa, Vahid Lari, Frank Hannig, Jürgen Teich, Artjom Grudnitsky, Lars Bauer, Jörg Henkel
2015	A*	`conf`	Robust design of E/E architecture component platforms. DAC Sebastian Graf, Sebastian Reinhart, Michael Glaß, Jürgen Teich, Daniel Platte
2015	C	`conf`	Runtime Adaptation of Application Execution under Thermal and Power Constraints in Massively Parallel Processor Arrays. SCOPES Éricles Sousa, Frank Hannig, Jürgen Teich, Qingqing Chen, Ulf Schlichtmann
2015	—	`conf`	Symbolic Message Routing for Multi-Objective Optimization of Automotive E/E Architecture Component Platforms. MBMV Sebastian Graf, Michael Glaß, Jürgen Teich
2015	C	`conf`	Symbolic loop parallelization for balancing I/O and memory accesses on processor arrays. MEMOCODE Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig
2015	J	`jnl`	Synthesis and optimization of image processing accelerators using domain knowledge. J. Syst. Archit. Oliver Reiche, Konrad Häublein, Marc Reichenbach, Moritz Schmid, Frank Hannig, Jürgen Teich, Dietmar Fey
2015	J	`jnl`	Techniques for on-demand structural redundancy for massively parallel processor arrays. J. Syst. Archit. Vahid Lari, Jürgen Teich, Alexandru Tanase, Michael Witterauf, Faramarz Khosravi, Brett H. Meyer
2015	C	`conf`	Throughput-optimizing Compilation of Dataflow Applications for Multi-Cores using Quasi-Static Scheduling. SCOPES Tobias Schwarzer, Joachim Falk, Michael Glaß, Jürgen Teich, Christian Zebelein, Christian Haubelt
2015	A	`conf`	Uncertainty-aware reliability analysis and optimization. DATE Faramarz Khosravi, Malte Müller, Michael Glaß, Jürgen Teich
2014	J	`jnl`	A Scala Prototype to Generate Multigrid Solver Implementations for Different Problems and Target Multi-Core Platforms. CoRR Harald Köstler, Christian Schmitt, Sebastian Kuckuk, Frank Hannig, Jürgen Teich, Ulrich Rüde
2014	Misc	`conf`	A Self-Adaptive SEU Mitigation System for FPGAs with an Internal Block RAM Radiation Particle Sensor. FCCM Robért Glein, Bernhard Schmidt, Florian Rittner, Jürgen Teich, Daniel Ziener
2014	A	`conf`	A self-propagating wakeup mechanism for point-to-point networks with partial network support. DATE Jan R. Seyler, Thilo Streichert, Juri Warkentin, Matthias Spagele, Michael Glaß, Jürgen Teich
2014	A*	`conf`	Advanced Diagnosis: SBST and BIST Integration in Automotive E/E Architectures. DAC Felix Reimann, Michael Glaß, Jürgen Teich, Alejandro Cook, Laura Rodríguez Gómez, Dominik Ull, Hans-Joachim Wunderlich, Piet Engelke, Ulrich Abelein
2014	—	`conf`	An Evaluation of Domain-Specific Language Technologies for Code Generation. ICCSA (Workshops/Short Papers/Posters) Christian Schmitt, Sebastian Kuckuk, Harald Köstler, Frank Hannig, Jürgen Teich
2014	A	`conf`	An automatic netlist and floorplanning approach to improve the MTTR of scrubbing techniques (abstract only). FPGA Bernhard Schmidt, Daniel Ziener, Jürgen Teich
2014	Misc	`conf`	An efficient technique for computing importance measures in automatic design of dependable embedded systems. CODES+ISSS Hananeh Aliee, Michael Glaß, Faramarz Khosravi, Jürgen Teich
2014	B	`conf`	An image processing library for C-based high-level synthesis. FPL Moritz Schmid, Nicolas Apelt, Frank Hannig, Jürgen Teich
2014	Misc	`conf`	Application-driven reconfiguration of shared resources for timing predictability of MPSoC platforms. ACSSC Deepak Gangadharan, Éricles Sousa, Vahid Lari, Frank Hannig, Jürgen Teich
2014	A*	`conf`	CAP: Communication Aware Programming. DAC Jan Heisswolf, Aurang Zaib, Andreas Zwinkau, Sebastian Kobbe, Andreas Weichslgartner, Jürgen Teich, Jörg Henkel, Gregor Snelting, Andreas Herkersdorf, Jürgen Becker
2014	J	`jnl`	Code Generation for High-Level Synthesis of Multiresolution Applications on FPGAs. CoRR Moritz Schmid, Oliver Reiche, Christian Schmitt, Frank Hannig, Jürgen Teich
2014	A	`conf`	Code generation for embedded heterogeneous architectures on android. DATE Richard Membarth, Oliver Reiche, Frank Hannig, Jürgen Teich
2014	Misc	`conf`	Code generation from a domain-specific language for C-based HLS of hardware accelerators. CODES+ISSS Oliver Reiche, Moritz Schmid, Frank Hannig, Richard Membarth, Jürgen Teich
2014	C	`conf`	Communication-Driven Automatic Virtual Prototyping for Networked Embedded Systems. DSD Liyuan Zhang, Joachim Falk, Tobias Schwarzer, Michael Glaß, Jürgen Teich
2014	J	`jnl`	Compact Code Generation for Tightly-Coupled Processor Arrays. J. Signal Process. Syst. Srinivas Boppu, Frank Hannig, Jürgen Teich
2014	Misc	`conf`	DAARM: Design-time application analysis and run-time mapping for predictable execution in many-core systems. CODES+ISSS Andreas Weichslgartner, Deepak Gangadharan, Stefan Wildermann, Michael Glaß, Jürgen Teich
2014	—	`conf`	DPSK modulated wakeup mechanism for point-to-point networks with partial network support. SIES Jan R. Seyler, Shurat Rahimov, Thilo Streichert, Michael Glaß, Jürgen Teich
2014	C	`conf`	Design Space Exploration for Automotive E/E Architecture Component Platforms. DSD Sebastian Graf, Michael Glaß, Jürgen Teich, Christoph Lauer
2014	—	`ch.`	Design and Evaluation of Future Ethernet AVB-Based ECU Networks. Embedded Systems Development, From Functional Models to Implementations Michael Glaß, Sebastian Graf, Felix Reimann, Jürgen Teich
2014	—	`conf`	Domain-specific augmentations for High-Level Synthesis. ASAP Moritz Schmid, Alexandru Tanase, Frank Hannig, Jürgen Teich, Vivek Singh Bhadouria, Dibyendu Ghoshal
2014	—	`conf`	End-to-end power estimation for heterogeneous cellular LTE SoCs in early design phases. PATMOS Bo Wang, Yang Xu, Ralph Hasholzner, Rafael Rosales, Michael Glaß, Jürgen Teich
2014	B	`conf`	Energy-aware SQL query acceleration through FPGA-based dynamic partial reconfiguration. FPL Andreas Becher, Florian Bauer, Daniel Ziener, Jürgen Teich
2014	—	`conf`	ExaSlang: a domain-specific language for highly scalable multigrid solvers. WOLFHPC@SC Christian Schmitt, Sebastian Kuckuk, Frank Hannig, Harald Köstler, Jürgen Teich
2014	—	`conf`	ExaStencils: Advanced Stencil-Code Engineering. Euro-Par Workshops (2) Christian Lengauer, Sven Apel, Matthias Bolten, Armin Größlinger, Frank Hannig, Harald Köstler, Ulrich Rüde, Jürgen Teich, Alexander Grebhahn, Stefan Kronawitter, Sebastian Kuckuk, Hannah Rittich, Christian Schmitt
2014	J	`jnl`	Experiments on Optimizing the Performance of Stencil Codes with SPL Conqueror. Parallel Process. Lett. Alexander Grebhahn, Sebastian Kuckuk, Christian Schmitt, Harald Köstler, Norbert Siegmund, Sven Apel, Frank Hannig, Jürgen Teich
2014	—	`ch.`	Exploration of Distributed Automotive Systems Using Compositional Timing Analysis. Embedded Systems Development, From Functional Models to Implementations Martin Lukasiewycz, Michael Glaß, Jürgen Teich, Samarjit Chakraborty
2014	J	`jnl`	Introduction to the Special Issue on Domain-Specific Multicore Computing. ACM Trans. Embed. Comput. Syst. Vijaykrishnan Narayanan, Jürgen Teich
2014	J	`jnl`	MAESTRO - Holistic Actor-Oriented Modeling of Nonfunctional Properties and Firmware Behavior for MPSoCs. ACM Trans. Design Autom. Electr. Syst. Rafael Rosales, Michael Glaß, Jürgen Teich, Bo Wang, Yang Xu, Ralph Hasholzner
2014	—	`conf`	Mahler: Sketch-Based Model-Driven Virtual Prototyping. ARCS Rafael Rosales, Michael Glaß, Jürgen Teich
2014	J	`jnl`	Massively Parallel Processor Architectures for Resource-aware Computing. CoRR Vahid Lari, Alexandru Tanase, Frank Hannig, Jürgen Teich
2014	—	`conf`	Minimizing Scrubbing Effort through Automatic Netlist Partitioning and Floorplanning. IPDPS Workshops Bernhard Schmidt, Daniel Ziener, Jürgen Teich
2014	A	`conf`	Model-based actor multiplexing with application to complex communication protocols. DATE Christian Zebelein, Christian Haubelt, Joachim Falk, Tobias Schwarzer, Jürgen Teich
2014	A*	`conf`	Multi-Objective Local-Search Optimization using Reliability Importance Measuring. DAC Faramarz Khosravi, Felix Reimann, Michael Glaß, Jürgen Teich
2014	A	`conf`	Multi-objective distributed run-time resource management for many-cores. DATE Stefan Wildermann, Michael Glaß, Jürgen Teich
2014	A	`conf`	Multi-variant-based design space exploration for automotive embedded systems. DATE Sebastian Graf, Michael Glaß, Jürgen Teich, Christoph Lauer
2014	A	`conf`	Non-intrusive integration of advanced diagnosis features in automotive E/E-architectures. DATE Ulrich Abelein, Alejandro Cook, Piet Engelke, Michael Glaß, Felix Reimann, Laura Rodríguez Gómez, Thomas Russ, Jürgen Teich, Dominik Ull, Hans-Joachim Wunderlich
2014	—	`conf`	Parametric yield optimization using leakage-yield-driven floorplanning. PATMOS Yang Xu, Bo Wang, Jürgen Teich
2014	J	`jnl`	Proceedings of the First Workshop on Resource Awareness and Adaptivity in Multi-Core Computing (Racing 2014). CoRR Frank Hannig, Jürgen Teich
2014	—	`conf`	Quality-aware video decoding on thermally-constrained MPSoC platforms. ASAP Deepak Gangadharan, Jürgen Teich, Samarjit Chakraborty
2014	J	`jnl`	Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience. Microelectron. Reliab. Andreas Herkersdorf, Hananeh Aliee, Michael Engel, Michael Glaß, Christina Gimmler-Dumont, Jörg Henkel, Veit Kleeberger, Michael A. Kochte, Johannes Maximilian Kühn, Daniel Mueller-Gritschneder, Sani R. Nassif, Holm Rauchfuss, Wolfgang Rosenstiel, Ulf Schlichtmann, Muhammad Shafique, Mehdi Baradaran Tahoori, Jürgen Teich, Norbert Wehn, Christian Weis, Hans-Joachim Wunderlich
2014	C	`conf`	Runtime Reconfigurable Bus Arbitration for Concurrent Applications on Heterogeneous MPSoC Architectures. DSD Éricles Sousa, Deepak Gangadharan, Frank Hannig, Jürgen Teich
2014	—	`conf`	Self-Integration for Virtualization of Embedded Many-Core Systems. SASO Workshops Stefan Wildermann, Jürgen Teich
2014	—	`conf`	Self-adaptive harris corner detector on heterogeneous many-core processor. DASIP Johny Paul, Walter Stechele, Éricles Sousa, Vahid Lari, Frank Hannig, Jürgen Teich, Manfred Kröhnert, Tamim Asfour
2014	J	`jnl`	Symbolic Mapping of Loop Programs onto Processor Arrays. J. Signal Process. Syst. Jürgen Teich, Alexandru Tanase, Frank Hannig
2014	C	`conf`	Symbolic inner loop parallelisation for massively parallel processor arrays. MEMOCODE Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig
2014	—	`conf`	The Invasive Network on Chip - A Multi-Objective Many-Core Communication Infrastructure. ARCS Workshops Jan Heisswolf, Aurang Zaib, Andreas Weichslgartner, Martin Karle, Maximilian Singh, Thomas Wild, Jürgen Teich, Andreas Herkersdorf, Jürgen Becker
2014	—	`conf`	Towards Actor-oriented Programming on PGAS-based Multicore Architectures. ARCS Workshops Sascha Roloff, Frank Hannig, Jürgen Teich
2014	J	`jnl`	Towards a performance-portable description of geometric multigrid algorithms using a domain-specific language. J. Parallel Distributed Comput. Richard Membarth, Oliver Reiche, Christian Schmitt, Frank Hannig, Jürgen Teich, Markus Stürmer, Harald Köstler
2014	Misc	`conf`	Towards scalable symbolic routing for multi-objective networked embedded system design and optimization. CODES+ISSS Sebastian Graf, Felix Reimann, Michael Glaß, Jürgen Teich
2013	—	`conf`	A prototype of an adaptive computer vision algorithm on MPSoC architecture. DASIP Éricles Rodrigues Sousa, Alexandru Tanase, Frank Hannig, Jürgen Teich
2013	J	`jnl`	A rule-based quasi-static scheduling approach for static islands in dynamic dataflow graphs. ACM Trans. Embed. Comput. Syst. Joachim Falk, Christian Zebelein, Christian Haubelt, Jürgen Teich
2013	C	`conf`	AUTO-GS: Self-Optimization of NoC Traffic through Hardware Managed Virtual Connections. DSD Aurang Zaib, Jan Heisswolf, Andreas Weichslgartner, Thomas Wild, Jürgen Teich, Jürgen Becker, Andreas Herkersdorf
2013	Misc	`conf`	Acceleration of SQL Restrictions and Aggregations through FPGA-Based Dynamic Partial Reconfiguration. FCCM Christopher Dennl, Daniel Ziener, Jürgen Teich
2013	—	`conf`	Accuracy and performance analysis of Harris Corner computation on tightly-coupled processor arrays. DASIP Éricles Rodrigues Sousa, Alexandru Tanase, Frank Hannig, Jürgen Teich
2013	A	`conf`	Automatic success tree-based reliability analysis for the consideration of transient and permanent faults. DATE Hananeh Aliee, Michael Glaß, Felix Reimann, Jürgen Teich
2013	C	`conf`	Bridging algorithm and ESL design: Matlab/Simulink model transformation and validation. FDL Liyuan Zhang, Michael Glaß, Nils Ballmann, Jürgen Teich
2013	—	`conf`	Exploitation of Quality/Throughput Tradeoffs in Image Processing through Invasive Computing. PARCO Alexandru Tanase, Vahid Lari, Frank Hannig, Jürgen Teich
2013	A	`conf`	Game-theoretic analysis of decentralized core allocation schemes on many-core systems. DATE Stefan Wildermann, Tobias Ziermann, Jürgen Teich
2013	—	`conf`	HW/SW Tradeoffs for Dynamic Message Scheduling in Controller Area Network (CAN). ARCS Tobias Ziermann, Zoran Salcic, Jürgen Teich
2013	—	`conf`	Hardware Supported Adaptive Data Collection for Networks on Chip. IPDPS Workshops Jan Heisswolf, Andreas Weichslgartner, Aurang Zaib, Ralf König, Thomas Wild, Andreas Herkersdorf, Jürgen Teich, Jürgen Becker
2013	—	`conf`	High-Level Synthesis Revised - Generation of FPGA Accelerators from a Domain-Specific Language using the Polyhedron Model. PARCO Moritz Schmid, Frank Hannig, Alexandru Tanase, Jürgen Teich
2013	Misc	`conf`	IVaM: Implicit variant modeling and management for automotive embedded systems. CODES+ISSS Sebastian Graf, Michael Glaß, Dominic Wintermann, Jürgen Teich, Christoph Lauer
2013	—	`ch.`	Integrated Modeling Using Finite State Machines and Dataflow Graphs. Handbook of Signal Processing Systems Joachim Falk, Christian Haubelt, Christian Zebelein, Jürgen Teich
2013	J	`jnl`	Invasive Computing - Common Terms and Granularity of Invasion CoRR Jürgen Teich, Wolfgang Schröder-Preikschat, Andreas Herkersdorf
2013	—	`conf`	Investigating the Impact of Energy-Efficient Ethernet on Automotive Applications via High-level Modeling. MBMV Sebastian Graf, Michael Glaß, Jürgen Teich
2013	—	`conf`	Loop program mapping and compact code generation for programmable hardware accelerators. ASAP Srinivas Boppu, Frank Hannig, Jürgen Teich
2013	—	`conf`	Model-Based Representation of Schedules for Dataflow Graphs. MBMV Christian Zebelein, Christian Haubelt, Joachim Falk, Jürgen Teich
2013	—	`conf`	NoC simulation in heterogeneous architectures for PGAS programming model. M-SCOPES Sascha Roloff, Andreas Weichslgartner, Jan Heißwolf, Frank Hannig, Jürgen Teich
2013	—	`conf`	On Confident Task-Accurate Performance Estimation. ARCS Yang Xu, Bo Wang, Rafael Rosales, Ralph Hasholzner, Jürgen Teich
2013	A*	`conf`	On robust task-accurate performance estimation. DAC Yang Xu, Bo Wang, Ralph Hasholzner, Rafael Rosales, Jürgen Teich
2013	—	`conf`	Real-timerange image preprocessing on FPGAs. ReConFig Moritz Schmid, Markus Blocherer, Frank Hannig, Jürgen Teich
2013	C	`conf`	Representing mapping and scheduling decisions within dataflow graphs. FDL Christian Zebelein, Christian Haubelt, Joachim Falk, Tobias Schwarzer, Jürgen Teich
2013	Misc	`conf`	Run-time adaption for highly-complex multi-core systems. CODES+ISSS Jörg Henkel, Vijaykrishnan Narayanan, Sri Parameswaran, Jürgen Teich
2013	—	`conf`	Symbolic parallelization of loop programs for massively parallel processor arrays. ASAP Jürgen Teich, Alexandru Tanase, Frank Hannig
2013	J	`jnl`	Symbolic system-level design methodology for multi-mode reconfigurable systems. Des. Autom. Embed. Syst. Stefan Wildermann, Felix Reimann, Daniel Ziener, Jürgen Teich
2013	—	`conf`	System integration of tightly-coupled processor arrays using reconfigurable buffer structures. Conf. Computing Frontiers Frank Hannig, Moritz Schmid, Vahid Lari, Srinivas Boppu, Jürgen Teich
2013	C	`conf`	Timing analysis of Ethernet AVB-based automotive E/E architectures. ETFA Felix Reimann, Sebastian Graf, Fabian Streit, Michael Glaß, Jürgen Teich
2013	J	`jnl`	Virtual networks - distributed communication resource management. ACM Trans. Reconfigurable Technol. Syst. Jan Heisswolf, Aurang Zaib, Andreas Weichslgartner, Ralf König, Thomas Wild, Jürgen Teich, Andreas Herkersdorf, Jürgen Becker
2012	—	`conf`	A Very Fast and Quasi-accurate Power-State-Based System-Level Power Modeling Methodology. ARCS Yang Xu, Rafael Rosales, Bo Wang, Martin Streubühr, Ralph Hasholzner, Christian Haubelt, Jürgen Teich
2012	—	`conf`	A co-simulation approach for system-level analysis of embedded control systems. ICSAMOS Michael Glaß, Jürgen Teich, Liyuan Zhang
2012	—	`conf`	A prototype of an invasive tightly-coupled processor array. DASIP Shravan Muddasani, Srinivas Boppu, Frank Hannig, Boris Kuzmin, Vahid Lari, Jürgen Teich
2012	—	`conf`	Actor-oriented Modeling und Simulation of Cut-through Communication in Network Controllers. MBMV Liyuan Zhang, Michael Glaß, Martin Streubühr, Jürgen Teich, Andreas von Schwerin, Kai Liu
2012	—	`conf`	Approximate time functional simulation of resource-aware programming concepts for heterogeneous MPSoCs. ASP-DAC Sascha Roloff, Frank Hannig, Jürgen Teich
2012	C	`conf`	Automatic Optimization of In-Flight Memory Transactions for GPU Accelerators Based on a Domain-Specific Language for Medical Imaging. ISPDC Richard Membarth, Frank Hannig, Jürgen Teich, Mario Körner, Wieland Eckert
2012	A*	`conf`	Considering diagnosis functionality during automatic system-level design of automotive networks. DAC Michael Eberl, Michael Glaß, Jürgen Teich, Ulrich Abelein
2012	B	`conf`	Cross-Level Compositional Reliability Analysis for Embedded Systems. SAFECOMP Michael Glaß, Heng Yu, Felix Reimann, Jürgen Teich
2012	—	`conf`	Design of Low Power On-chip Processor Arrays. ASAP Vahid Lari, Shravan Muddasani, Srinivas Boppu, Frank Hannig, Jürgen Teich
2012	A	`conf`	Designing FlexRay-based automotive architectures: A holistic OEM approach. DATE Paul Milbredt, Michael Glaß, Martin Lukasiewycz, Andreas Steininger, Jürgen Teich
2012	J	`jnl`	Distributed self-organizing bandwidth allocation for priority-based bus communication. Concurr. Comput. Pract. Exp. Tobias Ziermann, Stefan Wildermann, Nina Mühleis, Jürgen Teich
2012	J	`jnl`	Dynamic Defragmentation of Reconfigurable Devices. ACM Trans. Reconfigurable Technol. Syst. Sándor P. Fekete, Tom Kamphans, Nils Schweer, Christopher Tessars, Jan van der Veen, Josef Angermeier, Dirk Koch, Jürgen Teich
2012	—	`conf`	Dynamic Task-Scheduling and Resource Management for GPU Accelerators in Medical Imaging. ARCS Richard Membarth, Jan-Hugo Lupp, Frank Hannig, Jürgen Teich, Mario Körner, Wieland Eckert
2012	—	`conf`	Exploiting Model-Knowledge in High-Level Synthesis. MBMV Christian Zebelein, Christian Haubelt, Joachim Falk, Jürgen Teich
2012	—	`conf`	FPGA-based testbed for timing behavior evaluation of the Controller Area Network (CAN). ReConFig Tobias Ziermann, Alexander Butiu, Jürgen Teich, Daniel Ziener
2012	—	`conf`	Fast architecture evaluation of heterogeneous MPSoCs by host-compiled simulation. Map2MPSoC/SCOPES Sascha Roloff, Frank Hannig, Jürgen Teich
2012	—	`conf`	FlexRay Static Segment Scheduling. Advances in Real-Time Systems Martin Lukasiewycz, Michael Glaß, Jürgen Teich, Paul Milbredt
2012	A	`conf`	Generating Device-specific GPU Code for Local Operators in Medical Imaging. IPDPS Richard Membarth, Frank Hannig, Jürgen Teich, Mario Körner, Wieland Eckert
2012	—	`conf`	Hardware-assisted Decentralized Resource Management for Networks on Chip with QoS. IPDPS Workshops Jan Heisswolf, Aurang Zaib, Andreas Weichslgartner, Ralf König, Thomas Wild, Jürgen Teich, Andreas Herkersdorf, Jürgen Becker
2012	J	`jnl`	Hardware/Software Codesign: The Past, the Present, and Predicting the Future. Proc. IEEE Jürgen Teich
2012	J	`jnl`	Hierarchical power management for adaptive tightly-coupled processor arrays. ACM Trans. Design Autom. Electr. Syst. Vahid Lari, Shravan Muddasani, Srinivas Boppu, Frank Hannig, Moritz Schmid, Jürgen Teich
2012	C	`conf`	Invasive computing - Concepts and overheads. FDL Jürgen Teich, Andreas Weichslgartner, Benjamin Oechslein, Wolfgang Schröder-Preikschat
2012	—	`conf`	Keynote address II: Exploiting dynamic hardware reconfigurability for efficiency, performance, and reliability. AHS Jürgen Teich
2012	—	`conf`	Mastering Software Variant Explosion for GPU Accelerators. Euro-Par Workshops Richard Membarth, Frank Hannig, Jürgen Teich, Mario Körner, Wieland Eckert
2012	J	`jnl`	Model-Based Virtual Prototype Acceleration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jens Gladigau, Christian Haubelt, Jürgen Teich
2012	Misc	`conf`	On-the-fly Composition of FPGA-Based SQL Query Accelerators Using a Partially Reconfigurable Module Library. FCCM Christopher Dennl, Daniel Ziener, Jürgen Teich
2012	—	`conf`	Partial Reconfiguration on FPGAs in Practice - Tools and Applications. ARCS Workshops Dirk Koch, Jim Tørresen, Christian Beckhoff, Daniel Ziener, Christopher Dennl, Volker Breuer, Jürgen Teich, Michael Feilen, Walter Stechele
2012	J	`jnl`	Placing Multimode Streaming Applications on Dynamically Partially Reconfigurable Architectures. Int. J. Reconfigurable Comput. Stefan Wildermann, Josef Angermeier, Eugen Sibirko, Jürgen Teich
2012	Misc	`conf`	Power Management Strategies for Serial RapidIO Endpoints in FPGAs. FCCM Moritz Schmid, Frank Hannig, Jürgen Teich
2012	—	`conf`	Towards Domain-Specific Computing for Stencil Codes in HPC. SC Companion Richard Membarth, Frank Hannig, Jürgen Teich, Harald Köstler
2012	—	`conf`	Unreliable Data Transmissions und Limited Hardware Communication Buffers in Automotive E/E Virtual Prototypes. MBMV Sebastian Graf, Michael Glaß, Jürgen Teich
2012	A	`conf`	Variation-aware leakage power model extraction for system-level hierarchical power analysis. DATE Yang Xu, Bing Li, Ralph Hasholzner, Bernhard Rohfleisch, Christian Haubelt, Jürgen Teich
2012	—	`conf`	Virtual prototyping for efficient multi-core ECU development of driver assistance systems. ICSAMOS Rainer Kiesel, Martin Streubühr, Christian Haubelt, Anestis Terzis, Jürgen Teich
2011	J	`jnl`	A co-simulation approach for control performance analysis during design space exploration of cyber-physical systems. SIGBED Rev. Nina Mühleis, Michael Glaß, Liyuan Zhang, Jürgen Teich
2011	A	`conf`	A rule-based static dataflow clustering algorithm for efficient embedded software synthesis. DATE Joachim Falk, Christian Zebelein, Christian Haubelt, Jürgen Teich
2011	A*	`conf`	Accuracy of ethernet AVB time synchronization under varying temperature conditions for automotive networks. DAC Andreas Kern, Helge Zinner, Thilo Streichert, Josef Nöbauer, Jürgen Teich
2011	—	`conf`	An FPGA implementation of a threat-based strategy for Connect6. FPT Tobias Ziermann, Bernhard Schmidt, Moritz Mühlenthaler, Daniel Ziener, Josef Angermeier, Jürgen Teich
2011	A	`conf`	An automated data structure migration concept - From CAN to Ethernet/IP in automotive embedded systems (CANoverIP). DATE Andreas Kern, Thilo Streichert, Jürgen Teich
2011	C	`conf`	Automatic generation of system-level virtual prototypes from streaming application models. International Symposium on Rapid System Prototyping Philipp Kutzer, Jens Gladigau, Christian Haubelt, Jürgen Teich
2011	—	`conf`	Bitonic Sorting on Dynamically Reconfigurable Architectures. IPDPS Workshops Josef Angermeier, Eugen Sibirko, Rolf Wanka, Jürgen Teich
2011	—	`conf`	Calibration and validation of software performance models for pedestrian detection systems. ICSAMOS Rainer Kiesel, Martin Streubühr, Christian Haubelt, Otto Löhlein, Jürgen Teich
2011	—	`conf`	Decentralized dynamic resource management support for massively parallel processor arrays. ASAP Vahid Lari, Andriy Narovlyanskyy, Frank Hannig, Jürgen Teich
2011	Misc	`conf`	Design and architectures for dependable embedded systems. CODES+ISSS Jörg Henkel, Lars Bauer, Joachim Becker, Oliver Bringmann, Uwe Brinkschulte, Samarjit Chakraborty, Michael Engel, Rolf Ernst, Hermann Härtig, Lars Hedrich, Andreas Herkersdorf, Rüdiger Kapitza, Daniel Lohmann, Peter Marwedel, Marco Platzner, Wolfgang Rosenstiel, Ulf Schlichtmann, Olaf Spinczyk, Mehdi Baradaran Tahoori, Jürgen Teich, Norbert Wehn, Hans-Joachim Wunderlich
2011	—	`book`	Design of Image Processing Embedded Systems Using Multidimensional Data Flow Joachim Keinert, Jürgen Teich
2011	B	`conf`	Detector defect correction of medical images on graphics processors. Image Processing Richard Membarth, Frank Hannig, Jürgen Teich, Gerhard Litz, Heinz Hornegger
2011	—	`conf`	Distributed Resource Reservation in Massively Parallel Processor Arrays. IPDPS Workshops Vahid Lari, Frank Hannig, Jürgen Teich
2011	A	`conf`	DynOAA - Dynamic offset adaptation algorithm for improving response times of CAN systems. DATE Tobias Ziermann, Jürgen Teich, Zoran Salcic
2011	—	`conf`	Dynamic decentralized mapping of tree-structured applications on NoC architectures. NOCS Andreas Weichslgartner, Stefan Wildermann, Jürgen Teich
2011	C	`conf`	ESL power and performance estimation for heterogeneous MPSOCS using SystemC. FDL Martin Streubühr, Rafael Rosales, Ralph Hasholzner, Christian Haubelt, Jürgen Teich
2011	J	`jnl`	Efficient Evaluation of Power/Area/Latency Design Trade-Offs for Coarse-Grained Reconfigurable Processor Arrays. J. Low Power Electron. Dmitrij Kissler, Frank Hannig, Jürgen Teich
2011	—	`conf`	Frameworks for GPU Accelerators: A comprehensive evaluation using 2D/3D image registration. SASP Richard Membarth, Frank Hannig, Jürgen Teich, Mario Körner, Wieland Eckert
2011	—	`conf`	Frameworks for Multi-core Architectures: A Comprehensive Evaluation Using 2D/3D Image Registration. ARCS Richard Membarth, Frank Hannig, Jürgen Teich, Mario Körner, Wieland Eckert
2011	—	`conf`	Gateway Strategies for Embedding of Automotive CAN-Frames into Ethernet-Packets and Vice Versa. ARCS Andreas Kern, Dominik Reinhard, Thilo Streichert, Jürgen Teich
2011	—	`ch.`	Invasive Computing: An Overview. Multiprocessor System-on-Chip Jürgen Teich, Jörg Henkel, Andreas Herkersdorf, Doris Schmitt-Landsiedel, Wolfgang Schröder-Preikschat, Gregor Snelting
2011	Misc	`conf`	Mapping of applications to MPSoCs. CODES+ISSS Peter Marwedel, Jürgen Teich, Georgia Kouveli, Iuliana Bacivarov, Lothar Thiele, Soonhoi Ha, Chanhee Lee, Qiang Xu, Lin Huang
2011	—	`conf`	Operational mode exploration for reconfigurable systems with multiple applications. FPT Stefan Wildermann, Felix Reimann, Jürgen Teich, Zoran Salcic
2011	A	`conf`	Opt4J: a modular framework for meta-heuristic optimization. GECCO Martin Lukasiewycz, Michael Glaß, Felix Reimann, Jürgen Teich
2011	—	`ch.`	OrganicBus: Organic Self-organising Bus-Based Communication Systems. Organic Computing Tobias Ziermann, Stefan Wildermann, Jürgen Teich
2011	C	`conf`	Resource-aware programming and simulation of MPSoC architectures through extension of X10. SCOPES Frank Hannig, Sascha Roloff, Gregor Snelting, Jürgen Teich, Andreas Zwinkau
2011	—	`conf`	Runtime stress-aware replica placement on reconfigurable devices under safety constraints. FPT Josef Angermeier, Daniel Ziener, Michael Glaß, Jürgen Teich
2011	J	`jnl`	Scalable Many-Domain Power Gating in Coarse-Grained Reconfigurable Processor Arrays. IEEE Embed. Syst. Lett. Dmitrij Kissler, D. Gran, Zoran Salcic, Frank Hannig, Jürgen Teich
2011	C	`conf`	Self-organized Message Scheduling for Asynchronous Distributed Embedded Systems. ATC Tobias Ziermann, Zoran Salcic, Jürgen Teich
2011	B	`conf`	Stress-Aware Module Placement on Reconfigurable Devices. FPL Josef Angermeier, Daniel Ziener, Michael Glaß, Jürgen Teich
2011	Misc	`conf`	Symbolic design space exploration for multi-mode reconfigurable systems. CODES+ISSS Stefan Wildermann, Felix Reimann, Daniel Ziener, Jürgen Teich
2011	A*	`conf`	Symbolic system synthesis in the presence of stringent real-time constraints. DAC Felix Reimann, Martin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich
2011	—	`conf`	Testing switched Ethernet networks in automotive embedded systems. SIES Andreas Kern, Hongyan Zhang, Thilo Streichert, Jürgen Teich
2011	—	`conf`	Towards Resource Aware Programming on Intel's Single-Chip Cloud Computer Processor. MARC Symposium Georgia Kouveli, Frank Hannig, Jan-Hugo Lupp, Jürgen Teich
2011	—	`conf`	Towards Symbolic Run-Time Reconfiguration in Tightly-Coupled Processor Arrays. ReConFig Srinivas Boppu, Frank Hannig, Jürgen Teich, Roberto Perez-Andrade
2011	B	`conf`	Unifying Partitioning and Placement for SAT-Based Exploration of Heterogeneous Reconfigurable SoCs. FPL Stefan Wildermann, Jürgen Teich, Daniel Ziener
2010	—	`conf`	10281 Abstracts Collection - Dynamically Reconfigurable Architectures. Dynamically Reconfigurable Architectures Peter M. Athanas, Jürgen Becker, Jürgen Teich, Ingrid Verbauwhede
2010	—	`conf`	10281 Summary - Dynamically Reconfigurable Architectures. Dynamically Reconfigurable Architectures Peter M. Athanas, Jürgen Becker, Jürgen Teich, Ingrid Verbauwhede
2010	—	`ed.`	21st IEEE International Conference on Application-specific Systems Architectures and Processors, ASAP 2010, Rennes, France, 7-9 July 2010 ASAP François Charot, Frank Hannig, Jürgen Teich, Christophe Wolinski
2010	B	`conf`	A Bus-Based SoC Architecture for Flexible Module Placement on Reconfigurable FPGAs. FPL Andreas Oetken, Stefan Wildermann, Jürgen Teich, Dirk Koch
2010	—	`conf`	A Self-Organizing Distributed Reinforcement Learning Algorithm to Achieve Fair Bandwidth Allocation for Priority-Based Bus Communication. ISORC Workshops Tobias Ziermann, Nina Mühleis, Stefan Wildermann, Jürgen Teich
2010	—	`conf`	A deeply pipelined and parallel architecture for denoising medical images. FPT Frank Hannig, Moritz Schmid, Jürgen Teich, Heinz Hornegger
2010	A	`conf`	A rapid prototyping system for error-resilient multi-processor systems-on-chip. DATE Matthias May, Norbert Wehn, Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf, Daniel Ziener, Jürgen Teich
2010	—	`conf`	A system-level synthesis approach from formal application models to generic bus-based MPSoCs. ICSAMOS Jens Gladigau, Andreas Gerstlauer, Christian Haubelt, Martin Streubühr, Jürgen Teich
2010	—	`conf`	Actor-oriented Modeling of Driver Assistance Systems for Efficient Multi-Core ECU Implementation. MBMV Rainer Kiesel, Otto Löhlein, Anestis Terzis, Martin Streubühr, Christian Haubelt, Jürgen Teich
2010	—	`conf`	Adaptive traffic scheduling techniques for mixed real-time and streaming applications on reconfigurable hardware. IPDPS Workshops Tobias Ziermann, Jürgen Teich
2010	J	`jnl`	Analysis of SystemC actor networks for efficient synthesis. ACM Trans. Embed. Comput. Syst. Joachim Falk, Christian Zebelein, Joachim Keinert, Christian Haubelt, Jürgen Teich, Shuvra S. Bhattacharyya
2010	—	`book`	Digitale Hardware/Software-Systeme: Spezifikation und Verifikation Christian Haubelt, Jürgen Teich
2010	—	`ed.`	Dynamically Reconfigurable Architectures, 11.07. - 16.07.2010 Dynamically Reconfigurable Architectures Peter M. Athanas, Jürgen Becker, Jürgen Teich, Ingrid Verbauwhede
2010	—	`book`	Dynamically Reconfigurable Systems - Architectures, Design Methods and Applications. Dynamically Reconfigurable Systems Marco Platzner, Jürgen Teich, Norbert Wehn
2010	A	`conf`	Efficient High-Level modeling in the networking domain. DATE Christian Zebelein, Joachim Falk, Christian Haubelt, Jürgen Teich, Rainer Dorsch
2010	—	`ch.`	Erlangen Slot Machine: An FPGA-Based Dynamically Reconfigurable Computing Platform. Dynamically Reconfigurable Systems Josef Angermeier, Christophe Bobda, Mateusz Majer, Jürgen Teich
2010	—	`conf`	Generating GPU Code from a High-Level Representation for Image Processing Kernels. Euro-Par Workshops (1) Richard Membarth, Anton Lokhmotov, Jürgen Teich
2010	Misc	`conf`	Improving platform-based system synthesis by satisfiability modulo theories solving. CODES+ISSS Felix Reimann, Michael Glaß, Christian Haubelt, Michael Eberl, Jürgen Teich
2010	—	`ch.`	Integrated Modeling using Finite State Machines and Dataflow Graphs. Handbook of Signal Processing Systems Joachim Falk, Joachim Keinert, Christian Haubelt, Jürgen Teich, Christian Zebelein
2010	—	`conf`	Integrating Hardware/Firmware Verification Efforts Using SystemC High-Level Models. MBMV Joachim Falk, Christian Zebelein, Christian Haubelt, Jürgen Teich, Rainer Dorsch
2010	Misc	`conf`	Interprocedural Placement-Aware Configuration Prefetching for FPGA-Based Systems. FCCM Joon Edward Sim, Weng-Fai Wong, Gregor Walla, Tobias Ziermann, Jürgen Teich
2010	J	`jnl`	Maintaining Virtual Areas on FPGAs using Strip Packing with Delays CoRR Josef Angermeier, Sándor P. Fekete, Tom Kamphans, Nils Schweer, Jürgen Teich
2010	Misc	`conf`	Model-based analysis, synthesis and testing of automotive hardware/software architectures. EMSOFT Samarjit Chakraborty, S. Ramesh, Jürgen Teich
2010	—	`conf`	Multiplexing Methods for Power Watermarking. HOST Daniel Ziener, Florian Baueregger, Jürgen Teich
2010	B	`conf`	Network Bandwidth Optimization of Ethernet-Based Streaming Applications in Automotive Embedded Systems. ICCCN Andreas Kern, Christoph Schmutzler, Thilo Streichert, Michael Hübner, Jürgen Teich
2010	—	`conf`	New Directions for IP Core Watermarking and Identification. Dynamically Reconfigurable Architectures Daniel Ziener, Jürgen Teich
2010	J	`jnl`	No-Break Dynamic Defragmentation of Reconfigurable CoRR Sándor P. Fekete, Tom Kamphans, Nils Schweer, Christopher Tessars, Jan van der Veen, Josef Angermeier, Dirk Koch, Jürgen Teich
2010	—	`conf`	Placing Streaming Applications with Similarities on Dynamically Partially Reconfigurable Architectures. ReConFig Josef Angermeier, Stefan Wildermann, Eugen Sibirko, Jürgen Teich
2010	—	`ch.`	ReCoNets - Design Methodology for Embedded Systems Consisting of Small Networks of Reconfigurable Nodes and Connections. Dynamically Reconfigurable Systems Christian Haubelt, Dirk Koch, Felix Reimann, Thilo Streichert, Jürgen Teich
2010	—	`ch.`	ReCoNodes - Optimization Methods for Module Scheduling and Placement on Reconfigurable Hardware Devices. Dynamically Reconfigurable Systems Ali Ahmadinia, Josef Angermeier, Sándor P. Fekete, Tom Kamphans, Dirk Koch, Mateusz Majer, Nils Schweer, Jürgen Teich, Christopher Tessars, Jan van der Veen
2010	A	`conf`	Robust design of embedded systems. DATE Martin Lukasiewycz, Michael Glaß, Jürgen Teich
2010	J	`jnl`	Selected papers from the 18 IET Comput. Digit. Tech. Udo Kebschull, Marco Platzner, Jürgen Teich
2010	C	`conf`	Self-organizing Computer Vision for Robust Object Tracking in Smart Cameras. ATC Stefan Wildermann, Andreas Oetken, Jürgen Teich, Zoran A. Salcic
2010	A	`conf`	Symbolic system level reliability analysis. ICCAD Michael Glaß, Martin Lukasiewycz, Felix Reimann, Christian Haubelt, Jürgen Teich
2010	A*	`conf`	Towards scalable system-level reliability analysis. DAC Michael Glaß, Martin Lukasiewycz, Christian Haubelt, Jürgen Teich
2010	Misc	`conf`	Using the Power Side Channel of FPGAs for Communication. FCCM Daniel Ziener, Florian Baueregger, Jürgen Teich
2010	—	`conf`	Virtual area management: Multitasking on dynamically partially reconfigurable devices. IPDPS Workshops Josef Angermeier, Sándor P. Fekete, Tom Kamphans, Nils Schweer, Jürgen Teich
2009	A	`conf`	A communication architecture for complex runtime reconfigurable systems and its implementation on spartan-3 FPGAs. FPGA Dirk Koch, Christian Beckhoff, Jürgen Teich
2009	J	`jnl`	A holistic approach for tightly coupled reconfigurable parallel processors. Microprocess. Microsystems Hritam Dutta, Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich, Bernard Pottier
2009	—	`conf`	Acceleration of Multiresolution Imaging Algorithms: A Comparative Study. ASAP Richard Membarth, Philipp Kutzer, Hritam Dutta, Frank Hannig, Jürgen Teich
2009	A	`conf`	CAN+: A new backward-compatible Controller Area Network (CAN) protocol with up to 16× higher data rates. DATE Tobias Ziermann, Stefan Wildermann, Jürgen Teich
2009	J	`jnl`	CODES+ISSS 2007 guest editors' introduction. Des. Autom. Embed. Syst. Nikil D. Dutt, Jürgen Teich
2009	A	`conf`	Combined system synthesis and communication architecture exploration for MPSoCs. DATE Martin Lukasiewycz, Martin Streubühr, Michael Glaß, Christian Haubelt, Jürgen Teich
2009	J	`jnl`	Concepts for run-time and error-resilient control flow checking of embedded RISC CPUs. Int. J. Auton. Adapt. Commun. Syst. Daniel Ziener, Jürgen Teich
2009	A*	`conf`	Designing heterogeneous ECU networks via compact architecture encoding and hybrid timing analysis. DAC Michael Glaß, Martin Lukasiewycz, Jürgen Teich, Unmesh D. Bordoloi, Samarjit Chakraborty
2009	—	`conf`	Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors. SAMOS Richard Membarth, Frank Hannig, Hritam Dutta, Jürgen Teich
2009	C	`conf`	Efficient approximately-timed performance modeling for architectural exploration of MPSoCs. FDL Martin Streubühr, Jens Gladigau, Christian Haubelt, Jürgen Teich
2009	J	`jnl`	Electronic System-Level Synthesis Methodologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andreas Gerstlauer, Christian Haubelt, Andy D. Pimentel, Todor P. Stefanov, Daniel D. Gajski, Jürgen Teich
2009	Misc	`conf`	Exploiting data-redundancy in reliability-aware networked embedded system design. CODES+ISSS Martin Lukasiewycz, Michael Glaß, Jürgen Teich
2009	—	`conf`	FPGA implementation of an invasive computing architecture. FPT Abdulazim Amouri, Farhadur Arifin, Frank Hannig, Jürgen Teich
2009	Misc	`conf`	FlexRay schedule optimization of the static segment. CODES+ISSS Martin Lukasiewycz, Michael Glaß, Jürgen Teich, Paul Milbredt
2009	—	`conf`	From dynamic reconfiguration to self-reconfiguration: Invasive algorithms and architectures. FPT Jürgen Teich
2009	B	`conf`	General methodology for mapping iterative approximation algorithms to adaptive dynamically partially reconfigurable systems. FPL Josef Angermeier, Abdulazim Amouri, Jürgen Teich
2009	J	`jnl`	Hardware Decompression Techniques for FPGA-Based Embedded Systems. ACM Trans. Reconfigurable Technol. Syst. Dirk Koch, Christian Beckhoff, Jürgen Teich
2009	—	`conf`	Impact of Loop Tiling on the Controller Logic of Acceleration Engines. ASAP Hritam Dutta, Jiali Zhai, Frank Hannig, Jürgen Teich
2009	A	`conf`	Incorporating graceful degradation into embedded system design. DATE Michael Glaß, Martin Lukasiewycz, Christian Haubelt, Jürgen Teich
2009	Misc	`conf`	Minimizing Internal Fragmentation by Fine-Grained Two-Dimensional Module Placement for Runtime Reconfiguralble Systems. FCCM Dirk Koch, Christian Beckhoff, Jürgen Teich
2009	A	`conf`	Model-based synthesis and optimization of static multi-rate image processing algorithms. DATE Joachim Keinert, Hritam Dutta, Frank Hannig, Christian Haubelt, Jürgen Teich
2009	Misc	`conf`	Optimal Placement-aware Trace-Based Scheduling of Hardware Reconfigurations for FPGA Accelerators. FCCM Joon Edward Sim, Weng-Fai Wong, Jürgen Teich
2009	—	`conf`	Parallelization Approaches for Hardware Accelerators - Loop Unrolling Versus Loop Partitioning. ARCS Frank Hannig, Hritam Dutta, Jürgen Teich
2009	—	`conf`	Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC Using Modular Performance Analysis. ARCS Hritam Dutta, Frank Hannig, Jürgen Teich
2009	J	`jnl`	Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures. J. Low Power Electron. Dmitrij Kissler, Andreas Strawetz, Frank Hannig, Jürgen Teich
2009	—	`conf`	Self-organizing Bandwidth Sharing in Priority-Based Medium Access. SASO Stefan Wildermann, Tobias Ziermann, Jürgen Teich
2009	B	`conf`	Self-organizing multi-cue fusion for FPGA-based embedded imaging. FPL Stefan Wildermann, Gregor Walla, Tobias Ziermann, Jürgen Teich
2009	—	`conf`	System Integration of Tightly-Coupled Reconfigurable Processor Arrays and Evaluation of Buffer Size Effects on Their Performance. ICPP Workshops Vahid Lari, Frank Hannig, Jürgen Teich
2009	J	`jnl`	SystemCoDesigner - an automatic ESL synthesis approach by design space exploration and behavioral synthesis for streaming applications. ACM Trans. Design Autom. Electr. Syst. Joachim Keinert, Martin Streubühr, Thomas Schlichter, Joachim Falk, Jens Gladigau, Christian Haubelt, Jürgen Teich, Michael Meredith
2009	—	`conf`	Testfallgenerierung für SystemC-Designs mit abstrakten Modellbeschreibungen. MBMV Jens Gladigau, Christian Haubelt, Martin Streubühr, Jürgen Teich, Axel Schneider, Joachim Knäblein, Michael Lindig
2008	—	`conf`	3D Person Tracking with a Color-Based Particle Filter. RobVis Stefan Wildermann, Jürgen Teich
2008	A	`conf`	A Feasibility-Preserving Crossover and Mutation Operator for Constrained Combinatorial Problems. PPSN Martin Lukasiewycz, Michael Glaß, Jürgen Teich
2008	C	`conf`	A Sequential Learning Resource Allocation Network for Image Processing Applications. HIS Stefan Wildermann, Jürgen Teich
2008	B	`conf`	A comparison of embedded reconfigurable video-processing architectures. FPL Christopher Claus, Walter Stechele, Matthias Kovatsch, Josef Angermeier, Jürgen Teich
2008	B	`conf`	A feasibility-preserving local search operator for constrained discrete optimization problems. IEEE Congress on Evolutionary Computation Martin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich
2008	Misc	`conf`	A generalized static data flow clustering algorithm for mpsoc scheduling of multimedia applications. EMSOFT Joachim Falk, Joachim Keinert, Christian Haubelt, Jürgen Teich, Shuvra S. Bhattacharyya
2008	B	`conf`	Area and reconfiguration time minimization of the communication network in regular 2D reconfigurable architectures. FPL Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig
2008	C	`conf`	Classification of General Data Flow Actors into Known Models of Computation. MEMOCODE Christian Zebelein, Joachim Falk, Christian Haubelt, Jürgen Teich
2008	C	`conf`	Co-design Architecture and Implementation for Point-Based Rendering on FPGAs. IEEE International Workshop on Rapid System Prototyping Mateusz Majer, Stefan Wildermann, Josef Angermeier, Stefan Hanke, Jürgen Teich
2008	B	`conf`	Coarse-grained reconfiguration. FPL Sven Eisenhardt, Thomas Schweizer, Julio A. de Oliveira Filho, Tobias Oppold, Wolfgang Rosenstiel, Alexander Thomas, Jürgen Becker, Frank Hannig, Dmitrij Kissler, Hritam Dutta, Jürgen Teich, Heiko Hinkelmann, Peter Zipf, Manfred Glesner
2008	C	`conf`	Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures. DSD Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig
2008	C	`conf`	Concepts for Autonomous Control Flow Checking for Embedded CPUs. ATC Daniel Ziener, Jürgen Teich
2008	—	`ch.`	Concepts for Self-Adaptive and Self-Healing Networked Embedded Systems. Organic Computing Thilo Streichert, Christian Haubelt, Dirk Koch, Jürgen Teich
2008	A*	`conf`	Concurrent topology and routing optimization in automotive network integration. DAC Martin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich, Richard Regler, Bardo Lang
2008	—	`conf`	Dynamic Reconfiguration of FlexRay Schedules for Response Time Reduction in Asynchronous Fault-Tolerant Networks. ARCS Robert Brendle, Thilo Streichert, Dirk Koch, Christian Haubelt, Jürgen Teich
2008	Misc	`conf`	Efficient Reconfigurable On-Chip Buses for FPGAs. FCCM Dirk Koch, Christian Haubelt, Jürgen Teich
2008	—	`conf`	Efficient symbolic multi-objective design space exploration. ASP-DAC Martin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich
2008	B	`conf`	Fine grain reconfigurable architectures. FPL Josef Angermeier, Mateusz Majer, Jürgen Teich, Lars Braun, Tobias Schwalb, Philipp Graf, Michael Hübner, Jürgen Becker, Enno Lübbers, Marco Platzner, Christopher Claus, Walter Stechele, Andreas Herkersdorf, Markus Rullmann, Renate Merker
2008	A	`conf`	Heuristics for scheduling reconfigurable devices with consideration of reconfiguration overheads. IPDPS Josef Angermeier, Jürgen Teich
2008	J	`jnl`	Invasive Algorithms and Architectures (Invasive Algorithmen und Architekturen). it Inf. Technol. Jürgen Teich
2008	—	`conf`	Multi-objective routing and topology optimization in networked embedded systems. ICSAMOS Michael Glaß, Martin Lukasiewycz, Rolf Wanka, Christian Haubelt, Jürgen Teich
2008	—	`conf`	Netlist-level IP protection by watermarking for LUT-based FPGAs. FPT Moritz Schmid, Daniel Ziener, Jürgen Teich
2008	B	`conf`	No-break dynamic defragmentation of reconfigurable devices. FPL Sándor P. Fekete, Tom Kamphans, Nils Schweer, Christopher Tessars, Jan van der Veen, Josef Angermeier, Dirk Koch, Jürgen Teich
2008	J	`jnl`	Offline and Online Aspects of Defragmenting the Module Layout of a Partially Reconfigurable Device. IEEE Trans. Very Large Scale Integr. Syst. Sándor P. Fekete, Jan van der Veen, Ali Ahmadinia, Diana Göhringer, Mateusz Majer, Jürgen Teich
2008	Misc	`conf`	Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array Architectures. FCCM Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig
2008	—	`conf`	PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications. ARC Frank Hannig, Holger Ruckdeschel, Hritam Dutta, Jürgen Teich
2008	J	`jnl`	Power Signature Watermarking of IP Cores for FPGAs. J. Signal Process. Syst. Daniel Ziener, Jürgen Teich
2008	—	`conf`	Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures. PATMOS Dmitrij Kissler, Andreas Strawetz, Frank Hannig, Jürgen Teich
2008	B	`conf`	ReCoBus-Builder - A novel tool and technique to build statically and dynamically reconfigurable systems for FPGAS. FPL Dirk Koch, Christian Beckhoff, Jürgen Teich
2008	—	`conf`	Reconfigurable HW/SW Architecture of a Real-Time Driver Assistance System. ARC Josef Angermeier, Ulrich Batzer, Mateusz Majer, Jürgen Teich, Christopher Claus, Walter Stechele
2008	—	`conf`	Semi-Automatic Generation of mixed Hardware/Software Prototypes from Simulink Models. MBMV Martin Streubühr, Michael Jäntsch, Christian Haubelt, Jürgen Teich, Axel Schneider
2008	C	`conf`	Symbolic Quasi-Static Scheduling of Actor-Oriented SystemC Models. FDL Jens Gladigau, Christian Haubelt, Jürgen Teich
2008	A	`conf`	Symbolic Reliability Analysis and Optimization of ECU Networks. DATE Michael Glaß, Martin Lukasiewycz, Felix Reimann, Christian Haubelt, Jürgen Teich
2008	B	`conf`	Symbolic Reliability Analysis of Self-healing Networked Embedded Systems. SAFECOMP Michael Glaß, Martin Lukasiewycz, Felix Reimann, Christian Haubelt, Jürgen Teich
2008	—	`conf`	Symbolic Scheduling of SystemC Dataflow Designs. FDL (Selected Papers) Jens Gladigau, Christian Haubelt, Jürgen Teich
2008	Misc	`conf`	Symbolic voter placement for dependability-aware system synthesis. CODES+ISSS Felix Reimann, Michael Glaß, Martin Lukasiewycz, Joachim Keinert, Christian Haubelt, Jürgen Teich
2008	—	`conf`	Symbolische Modellprüfung Aktor-orientierter High-level SystemC-Modelle mit Intervalldiagrammen. MBMV Jens Gladigau, Frank Blendinger, Christian Haubelt, Jürgen Teich
2008	—	`conf`	Synthesis of Multi-dimensional High-Speed FIFOs for Out-of-Order Communication. ARCS Joachim Keinert, Christian Haubelt, Jürgen Teich
2008	—	`conf`	The PAULA Language for Designing Multi-Dimensional Dataflow-Intensive Applications. MBMV Frank Hannig, Holger Ruckdeschel, Jürgen Teich
2008	—	`conf`	Topology-Aware Replica Placement in Fault-Tolerant Embedded Networks. ARCS Thilo Streichert, Michael Glaß, Rolf Wanka, Christian Haubelt, Jürgen Teich
2008	C	`conf`	Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism. DSD Rainer Schaffer, Renate Merker, Frank Hannig, Jürgen Teich
2007	J	`jnl`	A SystemC-Based Design Methodology for Digital Signal Processing Systems. EURASIP J. Embed. Syst. Christian Haubelt, Joachim Falk, Joachim Keinert, Thomas Schlichter, Martin Streubühr, Andreas Deyhle, Andreas Hadert, Jürgen Teich
2007	—	`conf`	A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays: Case Study and Quantitative Evaluation. ERSA Jürgen Teich, Frank Hannig, Holger Ruckdeschel, Hritam Dutta, Dmitrij Kissler, Andrej Stravet
2007	—	`conf`	Actor-Oriented Modeling and Simulation of Sliding Window Image Processing Algorithms. ESTIMedia Joachim Keinert, Joachim Falk, Christian Haubelt, Jürgen Teich
2007	—	`conf`	Bitstream Decompression for High Speed FPGA Configuration from Slow Memories. FPT Dirk Koch, Christian Beckhoff, Jürgen Teich
2007	J	`jnl`	Design space exploration of reliable networked embedded systems. J. Syst. Archit. Thilo Streichert, Michael Glaß, Christian Haubelt, Jürgen Teich
2007	—	`book`	Digitale Hardware/Software-Systeme: Synthese und Optimierung, 2. Auflage Jürgen Teich, Christian Haubelt
2007	J	`jnl`	Dynamically Reconfigurable Architectures. EURASIP J. Embed. Syst. Neil Bergmann, Marco Platzner, Jürgen Teich
2007	J	`jnl`	Efficient control generation for mapping nested loop programs onto processor arrays. J. Syst. Archit. Hritam Dutta, Frank Hannig, Holger Ruckdeschel, Jürgen Teich
2007	C	`conf`	Efficient event-driven simulation of parallel processor architectures. SCOPES Alexey Kupriyanov, Dmitrij Kissler, Frank Hannig, Jürgen Teich
2007	A	`conf`	Efficient hardware checkpointing: concepts, overhead analysis, and implementation. FPGA Dirk Koch, Christian Haubelt, Jürgen Teich
2007	A	`conf`	Interactive presentation: Reliability-aware system synthesis. DATE Michael Glaß, Martin Lukasiewycz, Thilo Streichert, Christian Haubelt, Jürgen Teich
2007	C	`conf`	Mapping Actor-Oriented Models to TLM Architectures. FDL Jens Gladigau, Christian Haubelt, Bernhard Niemann, Jürgen Teich
2007	—	`conf`	Massively Parallel Processor Architectures: A Co-design Approach. ReCoSoC Hritam Dutta, Frank Hannig, Alexey Kupriyanov, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Bernard Pottier
2007	—	`ed.`	Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Erlangen, Germany, March 5-7, 2007 MBMV Christian Haubelt, Jürgen Teich
2007	C	`conf`	Modeling and Synthesis of Hardware-Software Morphing. ISCAS Dirk Koch, Christian Haubelt, Thilo Streichert, Jürgen Teich
2007	—	`conf`	Modeling of Interconnection Networks in Massively Parallel Processor Architectures. ARCS Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Julien Lallet, Olivier Sentieys, Sébastien Pillement
2007	Misc	`ed.`	Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2007, Salzburg, Austria, September 30 - October 3, 2007 CODES+ISSS Soonhoi Ha, Kiyoung Choi, Nikil D. Dutt, Jürgen Teich
2007	J	`jnl`	Reconfigurable Computing Systems (Rekonfigurierbare Rechensysteme). it Inf. Technol. Jürgen Teich
2007	B	`conf`	SAT-decoding in evolutionary algorithms for discrete constrained optimization problems. IEEE Congress on Evolutionary Computation Martin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich
2007	—	`conf`	Simulative Buffer Analysis of Local Image Processing Algorithms Described by Windowed Synchronous Data Flow. ICSAMOS Joachim Keinert, Christian Haubelt, Jürgen Teich
2007	A	`conf`	Solving Multi-objective Pseudo-Boolean Problems. SAT Martin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich
2007	C	`conf`	Symbolic Archive Representation for a Fast Nondominance Test. EMO Martin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich
2007	—	`conf`	System Level Modeling and Performance Simulation for Dynamic Reconfigurable Computing Systems in SystemC. MBMV Martin Streubühr, Carsten Riedel, Christian Haubelt, Jürgen Teich
2007	J	`jnl`	The Erlangen Slot Machine - A Platform for Interdisciplinary Research in Dynamically Reconfigurable Computing (ESM - Eine Hardware-Plattform für interdisziplinäre Forschung im Bereich des dynamischen rekonfigurierbaren Rechnens). it Inf. Technol. Josef Angermeier, Diana Göhringer, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen
2007	J	`jnl`	The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-based Computer. J. VLSI Signal Process. Mateusz Majer, Jürgen Teich, Ali Ahmadinia, Christophe Bobda
2006	—	`conf`	06141 Abstracts Collection -- Dynamically Reconfigurable Architectures. Dynamically Reconfigurable Architectures Jürgen Becker, Jürgen Teich, Gordon J. Brebner, Peter M. Athanas
2006	—	`conf`	06141 Executive Summary -- Dynamically Reconfigurable Architectures. Dynamically Reconfigurable Architectures Jürgen Becker, Jürgen Teich, Gordon J. Brebner, Peter M. Athanas
2006	—	`conf`	A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing. ASAP Hritam Dutta, Frank Hannig, Jürgen Teich, Benno Heigl, Heinz Hornegger
2006	—	`conf`	A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template. ReCoSoC Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich
2006	—	`conf`	A Flexible Reconfiguration Manager for the Erlangen Slot Machine. ARCS Workshops Mateusz Majer, Ali Ahmadinia, Christophe Bobda, Jürgen Teich
2006	—	`conf`	A Generic Framework for Rapid Prototyping of System-on-Chip Designs. CDES Dmitrij Kissler, Alexey Kupriyanov, Frank Hannig, Dirk Koch, Jürgen Teich
2006	—	`conf`	A highly parameterizable parallel processor array architecture. FPT Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich
2006	—	`conf`	An Architecture Description Language for Massively Parallel Processor Architectures. MBMV Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Renate Merker
2006	—	`conf`	An Operating System Infrastructure for Fault-Tolerant Reconfigurable Networks. ARCS Dirk Koch, Thilo Streichert, Steffen Dittrich, Christian Strengert, Christian Haubelt, Jürgen Teich
2006	J	`jnl`	Analysis of Dataflow Programs with Interval-limited Data-rates. J. VLSI Signal Process. Jürgen Teich, Shuvra S. Bhattacharyya
2006	Misc	`conf`	Are current ESL tools meeting the requirements of advanced embedded systems? CODES+ISSS Jürgen Teich
2006	—	`conf`	Bridging the Gap between Relocatability and Available Technology: The Erlangen Slot Machine. Dynamically Reconfigurable Architectures Diana Göhringer, Mateusz Majer, Jürgen Teich
2006	—	`conf`	Controller Synthesis for Mapping Partitioned Programs on Array Architectures. ARCS Hritam Dutta, Frank Hannig, Jürgen Teich
2006	—	`conf`	Dynamic task binding for hardware/software reconfigurable networks. SBCCI Thilo Streichert, Christian Strengert, Christian Haubelt, Jürgen Teich
2006	—	`ed.`	Dynamically Reconfigurable Architectures, 02.04. - 07.04.2006 Dynamically Reconfigurable Architectures Peter M. Athanas, Jürgen Becker, Gordon J. Brebner, Jürgen Teich
2006	C	`conf`	Efficient Representation and Simulation of Model-Based Designs. FDL Joachim Falk, Christian Haubelt, Jürgen Teich
2006	—	`conf`	FPGA core watermarking based on power signature analysis. FPT Daniel Ziener, Jürgen Teich
2006	—	`conf`	Hardware Cost Analysis for Weakly Programmable Processor Arrays. SoC Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich
2006	—	`conf`	Hierarchical Partitioning for Piecewise Linear Algorithms. PARELEC Hritam Dutta, Frank Hannig, Jürgen Teich
2006	J	`jnl`	Higher-Dimensional Packing with Order Constraints. SIAM J. Discret. Math. Sándor P. Fekete, Ekkehard Köhler, Jürgen Teich
2006	B	`conf`	Identifying FPGA IP-Cores Based on Lookup Table Content Analysis. FPL Daniel Ziener, Stefan Assmus, Jürgen Teich
2006	—	`conf`	Improving System Level Design Space Exploration by Incorporating SAT-Solvers into Multi-Objective Evolutionary Algorithms. ISVLSI Thomas Schlichter, Martin Lukasiewycz, Christian Haubelt, Jürgen Teich
2006	J	`jnl`	Mapping a class of dependence algorithms to coarse-grained reconfigurable arrays: architectural parameters and methodology. Int. J. Embed. Syst. Frank Hannig, Hritam Dutta, Jürgen Teich
2006	B	`conf`	Minimizing Communication Cost for Reconfigurable Slot Modules. FPL Sándor P. Fekete, Jan van der Veen, Mateusz Majer, Jürgen Teich
2006	—	`conf`	Modeling and Analysis of Windowed Synchronous Algorithms. ICASSP (3) Joachim Keinert, Christian Haubelt, Jürgen Teich
2006	J	`jnl`	Modeling and Design of Fault-Tolerant and Self-Adaptive Reconfigurable Networked Embedded Systems. EURASIP J. Embed. Syst. Thilo Streichert, Dirk Koch, Christian Haubelt, Jürgen Teich
2006	—	`conf`	Multi-Objective Topology Optimization for Networked Embedded Systems. ICSAMOS Thilo Streichert, Christian Haubelt, Jürgen Teich
2006	—	`conf`	Searching RC5-Keys with Distributed Reconfigurable Computing. ERSA Dirk Koch, Matthiaas Koerber, Jürgen Teich
2006	A	`conf`	Task-accurate performance modeling in SystemC for real-time multi-processor architectures. DATE Martin Streubühr, Joachim Falk, Christian Haubelt, Jürgen Teich, Rainer Dorsch, Thomas Schlipf
2006	—	`conf`	Topic 18: Embedded Parallel Systems. Euro-Par Jürgen Teich, Stefanos Kaxiras, Toomas P. Plaks, Krisztián Flautner
2005	—	`conf`	A New Approach on Many Objective Diversity Measurement. Practical Approaches to Multi-Objective Optimization Sanaz Mostaghim, Jürgen Teich
2005	J	`jnl`	A Practical Approach for Circuit Routing on Dynamic Reconfigurable Devices CoRR Ali Ahmadinia, Christophe Bobda, Ji Ding, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen
2005	C	`conf`	A Practical Approach for Circuit Routing on Dynamic Reconfigurable Devices. IEEE International Workshop on Rapid System Prototyping Ali Ahmadinia, Christophe Bobda, Ji Ding, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen
2005	—	`conf`	A system-level approach to hardware reconfigurable systems. ASP-DAC Christian Haubelt, Stephan Otto, Cornelia Grabbe, Jürgen Teich
2005	—	`conf`	Automatic FIR Filter Generation for FPGAs. SAMOS Holger Ruckdeschel, Hritam Dutta, Frank Hannig, Jürgen Teich
2005	—	`conf`	Co-Design of Massively Parallel Embedded Processor Architectures. ReCoSoC Frank Hannig, Hritam Dutta, Alexey Kupriyanov, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Ronan Keryell, Bernard Pottier, Daniel Chillet, Daniel Ménard, Olivier Sentieys
2005	J	`jnl`	Defragmenting the Module Layout of a Partially Reconfigurable Device CoRR Jan van der Veen, Sándor P. Fekete, Ali Ahmadinia, Christophe Bobda, Frank Hannig, Jürgen Teich
2005	—	`conf`	Defragmenting the Module Layout of a Partially Reconfigurable Device. ERSA Jan van der Veen, Sándor P. Fekete, Mateusz Majer, Ali Ahmadinia, Christophe Bobda, Frank Hannig, Jürgen Teich
2005	A	`conf`	Distributed HW/SW-Partitioning for Embedded Reconfigurable Networks. DATE Thilo Streichert, Christian Haubelt, Jürgen Teich
2005	J	`jnl`	DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices CoRR Christophe Bobda, Ali Ahmadinia, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen
2005	B	`conf`	DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices. FPL Christophe Bobda, Ali Ahmadinia, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen
2005	A	`conf`	Improving EA-based design space exploration by utilizing symbolic feasibility tests. GECCO Thomas Schlichter, Christian Haubelt, Jürgen Teich
2005	C	`conf`	Initial Population Construction for Convergence Improvement of MOEAs. EMO Christian Haubelt, Jürgen Gamenik, Jürgen Teich
2005	B	`conf`	Modeling and analysis of indirect communication in particle swarm optimization. Congress on Evolutionary Computation S. Helwig, Christian Haubelt, Jürgen Teich
2005	—	`conf`	Online hardware/software partitioning in networked embedded systems. ASP-DAC Thilo Streichert, Christian Haubelt, Jürgen Teich
2005	J	`jnl`	Online placement for dynamically reconfigurable devices. Int. J. Embed. Syst. Ali Ahmadinia, Christophe Bobda, Jürgen Teich
2005	—	`conf`	Output Serialization for FPGA-based and Coarse-grained Processor Arrays. ERSA Frank Hannig, Jürgen Teich
2005	A	`conf`	Packet Routing in Dynamically Changing Networks on Chip. IPDPS Mateusz Majer, Christophe Bobda, Ali Ahmadinia, Jürgen Teich
2005	—	`ch.`	Quad-trees: A Data Structure for Storing Pareto Sets in Multiobjective Evolutionary Algorithms with Elitism. Evolutionary Multiobjective Optimization Sanaz Mostaghim, Jürgen Teich
2005	—	`conf`	SPI-Workbench - Modellierung, Analyse und Optimierung eingebetteter Systeme. GI Jahrestagung (2) Christian Haubelt, Marek Jersak, Kai Richter, Karsten Strehl, Dirk Ziegenbein, Rolf Ernst, Jürgen Teich, Lothar Thiele
2005	Misc	`conf`	The Erlangen Slot Machine: A Highly Flexible FPGA-Based Reconfigurable Platform. FCCM Christophe Bobda, Mateusz Majer, Ali Ahmadinia, Thomas Haller, André Linarth, Jürgen Teich, Sándor P. Fekete, Jan van der Veen
2005	—	`conf`	The Erlangen Slot Machine: Increasing Flexibility in FPGA-Based Reconfigurable Platforms. FPT Christophe Bobda, Mateusz Majer, Ali Ahmadinia, Thomas Haller, André Linarth, Jürgen Teich
2005	—	`conf`	Using Symbolic Feasibility Tests during Design Space Exploration of Heterogeneous Multi-Processor Systems. ASAP Thomas Schlichter, Christian Haubelt, Frank Hannig, Jürgen Teich
2004	B	`conf`	A Dynamic NoC Approach for Communication in Reconfigurable Devices. FPL Christophe Bobda, Mateusz Majer, Dirk Koch, Ali Ahmadinia, Jürgen Teich
2004	—	`conf`	A Dynamic Scheduling and Placement Algorithm for Reconfigurable Hardware. ARCS Ali Ahmadinia, Christophe Bobda, Jürgen Teich
2004	A	`conf`	A New Approach for On-line Placement on Reconfigurable Devices. IPDPS Ali Ahmadinia, Christophe Bobda, Marcus Bednara, Jürgen Teich
2004	—	`conf`	Analysis of Dataflow Programs with Interval-Limited Data-Rates. SAMOS Jürgen Teich, Shuvra S. Bhattacharyya
2004	—	`conf`	Basic OS Support for Distributed Reconfigurable Hardware. SAMOS Christian Haubelt, Dirk Koch, Jürgen Teich
2004	B	`conf`	Covering Pareto-optimal fronts by subswarms in multi-objective particle swarm optimization. IEEE Congress on Evolutionary Computation Sanaz Mostaghim, Jürgen Teich
2004	—	`conf`	Dynamic Piecewise Linear/Regular Algorithms. PARELEC Frank Hannig, Jürgen Teich
2004	—	`conf`	Generation of Distributed Arithmetic Designs for Reconfigurable Application. ARCS Workshops Christophe Bobda, Ali Ahmadinia, Jürgen Teich
2004	—	`conf`	High-Speed Event-Driven RTL Compiled Simulation. SAMOS Alexey Kupriyanov, Frank Hannig, Jürgen Teich
2004	A	`conf`	Mapping of Regular Nested Loop Programs to Coarse-Grained Reconfigurable Arrays - Constraints and Methodology. IPDPS Frank Hannig, Hritam Dutta, Jürgen Teich
2004	B	`conf`	Molecular force field parametrization using multi-objective evolutionary algorithms. IEEE Congress on Evolutionary Computation Sanaz Mostaghim, Michael Hoffmann, Peter H. Konig, Thomas Frauenheim, Jürgen Teich
2004	J	`jnl`	Optimal Routing-Conscious Dynamic Placement for Reconfigurable Devices CoRR Ali Ahmadinia, Christophe Bobda, Sándor P. Fekete, Jürgen Teich, Jan van der Veen
2004	B	`conf`	Optimal Routing-Conscious Dynamic Placement for Reconfigurable Devices. FPL Ali Ahmadinia, Christophe Bobda, Sándor P. Fekete, Jürgen Teich, Jan van der Veen
2004	—	`conf`	Platform-independent methodology for partial reconfiguration. Conf. Computing Frontiers Dirk Koch, Jürgen Teich
2004	A	`conf`	Real-Time Configuration Code Decompression for Dynamic FPGA Self-Reconfiguration. IPDPS Ali Ahmadinia, Christophe Bobda, Marcus Bednara, Jürgen Teich
2004	—	`conf`	Regular mapping for coarse-grained reconfigurable architectures. ICASSP (5) Frank Hannig, Hritam Dutta, Jürgen Teich
2004	—	`conf`	Resource Constrained and Speculative Scheduling of an Algorithm Class with Run-Time Dependent Conditionals. ASAP Frank Hannig, Jürgen Teich
2004	—	`conf`	Systematic Integration of Parameterized Local Search Techniques in Evolutionary Algorithms. GECCO (2) Neal K. Bambha, Shuvra S. Bhattacharyya, Jürgen Teich, Eckart Zitzler
2004	J	`jnl`	Systematic integration of parameterized local search into evolutionary algorithms. IEEE Trans. Evol. Comput. Neal K. Bambha, Shuvra S. Bhattacharyya, Jürgen Teich, Eckart Zitzler
2004	—	`conf`	Task scheduling for heterogeneous reconfigurable computers. SBCCI Ali Ahmadinia, Christophe Bobda, Dirk Koch, Mateusz Majer, Jürgen Teich
2003	A	`conf`	A High Performance VLIW Processor for Finite Field Arithmetic. IPDPS Cornelia Grabbe, Marcus Bednara, Joachim von zur Gathen, Jamshid Shokrollahi, Jürgen Teich
2003	—	`conf`	A new approach for reconfigurable massively parallel computers. FPT Christophe Bobda, Klaus Danne, Ali Ahmadinia, Jürgen Teich
2003	—	`conf`	Accelerating design space exploration using pareto-front arithmetics. ASP-DAC Christian Haubelt, Jürgen Teich
2003	J	`jnl`	Automatic Synthesis of FPGA Processor Arrays from Loop Algorithms. J. Supercomput. Marcus Bednara, Jürgen Teich
2003	J	`jnl`	BUILDABONG: A Framework for Architecture/Compiler Co-Exploration for ASIPs. J. Circuits Syst. Comput. Dirk Fischer, Jürgen Teich, Ralph Weper, Michael Thies
2003	C	`conf`	Covering Pareto Sets by Multilevel Evolutionary Subdivision Techniques. EMO Oliver Schütze, Sanaz Mostaghim, Michael Dellnitz, Jürgen Teich
2003	J	`jnl`	Design and Implementation of Digital Linear Control Systems on Reconfigurable Hardware. EURASIP J. Adv. Signal Process. Marcus Bednara, Klaus Danne, Markus Deppe, Oliver Oberschelp, Frank Slomka, Jürgen Teich
2003	—	`conf`	FPGA designs of parallel high performance GF(2 ISCAS (2) Cornelia Grabbe, Marcus Bednara, Jürgen Teich, Joachim von zur Gathen, Jamshid Shokrollahi
2003	B	`conf`	Fault Tolerances Analysis of Distributed Reconfigurable Systems Using SAT-Based Techniques. FPL Rainer Feldmann, Christian Haubelt, Burkhard Monien, Jürgen Teich
2003	J	`jnl`	Higher-Dimensional Packing with Order Constraints CoRR Sándor P. Fekete, Ekkehard Köhler, Jürgen Teich
2003	A	`conf`	Improved Time Domain Simulation of Optical Multimode Intrasystem Interconnects. DATE Jens Gerling, Oliver Stübbe, Jürgen Schrage, Gerd Mrozynski, Jürgen Teich
2003	—	`conf`	ReCoNet: Modeling and Implementation of Fault Tolerant Distributed Reconfigurable Hardware. SBCCI Christian Haubelt, Dirk Koch, Jürgen Teich
2003	A	`conf`	SAT-Based Techniques in System Synthesis. DATE Christian Haubelt, Jürgen Teich, Rainer Feldmann, Burkhard Monien
2003	C	`conf`	Solving Hierarchical Optimization Problems Using MOEAs. EMO Christian Haubelt, Sanaz Mostaghim, Jürgen Teich, Ambrish Tyagi
2003	C	`conf`	Speeding up Online Placement for XILINX FPGAs by Reducing Configuration Overhead. VLSI-SOC Ali Ahmadinia, Jürgen Teich
2003	—	`conf`	Strategies for finding good local guides in multi-objective particle swarm optimization (MOPSO). SIS Sanaz Mostaghim, Jürgen Teich
2003	B	`conf`	Synthesizing passive networks by applying genetic programming and evolution strategies. IEEE Congress on Evolutionary Computation Christian Reinhold, P. Kralicek, Werner John, Jürgen Teich
2003	—	`conf`	Temporal task clustering for online placement on reconfigurable hardware. FPT Ali Ahmadinia, Christophe Bobda, Jürgen Teich
2003	B	`conf`	The role of ε-dominance in multi objective particle swarm optimization methods. IEEE Congress on Evolutionary Computation Sanaz Mostaghim, Jürgen Teich
2002	A	`conf`	(Self-)reconfigurable Finite State Machines: Theory and Implementation. DATE Jürgen Teich, Markus Köster
2002	B	`conf`	Comparison of data structures for storing Pareto-sets in MOEAs. IEEE Congress on Evolutionary Computation Sanaz Mostaghim, Jürgen Teich, Ambrish Tyagi
2002	Misc	`conf`	Efficient architecture/compiler co-exploration for ASIPs. CASES Dirk Fischer, Jürgen Teich, Michael Thies, Ralph Weper
2002	—	`ed.`	Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS Embedded Processor Design Challenges Ed F. Deprettere, Jürgen Teich, Stamatis Vassiliadis
2002	B	`conf`	Energy estimation of nested loop programs. SPAA Frank Hannig, Jürgen Teich
2002	—	`conf`	Exact Partitioning of Affine Dependence Algorithms. Embedded Processor Design Challenges Jürgen Teich, Lothar Thiele
2002	—	`conf`	Flexibility/Cost-Tradeoffs of Platform-Based Systems. Embedded Processor Design Challenges Christian Haubelt, Jürgen Teich, Kai Richter, Rolf Ernst
2002	—	`conf`	Generation of Distributed Loop Control. Embedded Processor Design Challenges Marcus Bednara, Frank Hannig, Jürgen Teich
2002	—	`conf`	Modellierung rekonfigurierbarer Systemarchitekturen. MBMV Christian Haubelt, Jürgen Teich, Kai Richter, Rolf Ernst
2002	A	`conf`	Reconfigurable Implementation of Elliptic Curve Crypto Algorithms. IPDPS Marcus Bednara, M. Daldrup, Joachim von zur Gathen, Jamshid Shokrollahi, Jürgen Teich
2002	—	`conf`	SPI - Workbench für die Analyse Eingebetteter Systeme. Modelle, Werkzeuge und Infrastrukturen zur Unterstützung von Entwicklungsprozessen Marek Jersak, Kai Richter, Dirk Ziegenbein, Rolf Ernst, Christian Haubelt, Frank Slomka, Jürgen Teich
2002	J	`jnl`	SPI - a system model for heterogeneously specified embedded systems. IEEE Trans. Very Large Scale Integr. Syst. Dirk Ziegenbein, Kai Richter, Rolf Ernst, Lothar Thiele, Jürgen Teich
2002	A	`conf`	System Design for Flexibility. DATE Christian Haubelt, Jürgen Teich, Kai Richter, Rolf Ernst
2002	—	`conf`	Tradeoff analysis of FPGA based elliptic curve cryptography. ISCAS (5) Marcus Bednara, M. Daldrup, Jürgen Teich, Joachim von zur Gathen, Jamshid Shokrollahi
2001	B	`conf`	Design Space Exploration for Massively Parallel Processor Arrays. PaCT Frank Hannig, Jürgen Teich
2001	Misc	`conf`	Design space characterization for architecture/compiler co-exploration. CASES Dirk Fischer, Jürgen Teich, Ralph Weper, Uwe Kastens, Michael Thies
2001	J	`jnl`	Extending Partial Suborders. Electron. Notes Discret. Math. Sándor P. Fekete, Ekkehard Köhler, Jürgen Teich
2001	J	`jnl`	FunState-an internal design representation for codesign. IEEE Trans. Very Large Scale Integr. Syst. Karsten Strehl, Lothar Thiele, Matthias Gries, Dirk Ziegenbein, Rolf Ernst, Jürgen Teich
2001	B	`conf`	Higher-Dimensional Packing with Order Constraints. WADS Sándor P. Fekete, Ekkehard Köhler, Jürgen Teich
2001	—	`conf`	Hybrid global/local search strategies for dynamic voltage scaling in embedded multiprocessors. CODES Neal K. Bambha, Shuvra S. Bhattacharyya, Jürgen Teich, Eckart Zitzler
2001	A	`conf`	Optimal FPGA module placement with temporal precedence constraints. DATE Sándor P. Fekete, Ekkehard Köhler, Jürgen Teich
2001	J	`jnl`	Optimization of Dynamic Hardware Reconfigurations. J. Supercomput. Jürgen Teich, Sándor P. Fekete, Jörg Schepers
2001	C	`conf`	Pareto-Front Exploration with Uncertain Objectives. EMO Jürgen Teich
2000	Misc	`conf`	A joined architecture/compiler design environment for ASIPs. CASES Jürgen Teich, Ralph Weper, Dirk Fischer, Stefan Trinkert
2000	—	`conf`	Description and Simulation of Microprocessor Instruction Sets Using ASMs. Abstract State Machines Jürgen Teich, Philipp W. Kutter, Ralph Weper
2000	—	`conf`	EXPLORA - Generic Design Space Exploration during Embedded System Synthesis. DIPES F. Cieslok, H. Esau, Jürgen Teich
2000	J	`jnl`	Evolutionary algorithms for the synthesis of embedded software. IEEE Trans. Very Large Scale Integr. Syst. Eckart Zitzler, Jürgen Teich, Shuvra S. Bhattacharyya
2000	J	`jnl`	Multidimensional Exploration of Software Implementations for DSP Algorithms. J. VLSI Signal Process. Eckart Zitzler, Jürgen Teich, Shuvra S. Bhattacharyya
2000	B	`conf`	Optimizing the efficiency of parameterized local search within global search: a preliminary study. CEC Eckart Zitzler, Jürgen Teich, Shuvra S. Bhattacharyya
2000	J	`jnl`	Regular state machines. Parallel Algorithms Appl. Lothar Thiele, Jürgen Teich, Karsten Strehl
2000	—	`conf`	Tradeoff Analysis and Architecture Design of a Hybrid Hardware/Software Sorter. ASAP Marcus Bednara, Oliver Beyer, Jürgen Teich, Rolf Wanka
1999	—	`conf`	3D exploration of software schedules for DSP algorithms. CODES Jürgen Teich, Eckart Zitzler, Shuvra S. Bhattacharyya
1999	Misc	`conf`	Compile-time Optimization of Dynamic Hardware Reconfigurations. PDPTA Jürgen Teich, Sándor P. Fekete, Jörg Schepers
1999	A	`conf`	FunState - an internal design representation for codesign. ICCAD Lothar Thiele, Karsten Strehl, Dirk Ziegenbein, Rolf Ernst, Jürgen Teich
1999	A*	`conf`	Representation of Function Variants for Embedded System Optimization and Synthesis. DAC Kai Richter, Dirk Ziegenbein, Rolf Ernst, Lothar Thiele, Jürgen Teich
1999	—	`conf`	SPI -- An Internal Representation for Heterogeneously Specified Embedded Systems. MBMV Dirk Ziegenbein, Kai Richter, Rolf Ernst, Lothar Thiele, Jürgen Teich
1999	—	`conf`	Scheduling hardware/software systems using symbolic techniques. CODES Karsten Strehl, Lothar Thiele, Dirk Ziegenbein, Rolf Ernst, Jürgen Teich
1998	A	`conf`	Buffer Memory Optimization in DSP Applications - An Evolutionary Approach. PPSN Jürgen Teich, Eckart Zitzler, Shuvra S. Bhattacharyya
1998	—	`conf`	Combining multiple models of computation for scheduling and allocation. CODES Dirk Ziegenbein, Rolf Ernst, Kai Richter, Jürgen Teich, Lothar Thiele
1998	—	`conf`	Domain-specific interface generation from dataflow specifications. CODES Michael Eisenring, Jürgen Teich
1998	B	`conf`	Interfacing Hardware and Software. FPL Michael Eisenring, Jürgen Teich
1998	—	`conf`	Rapid Prototyping of Dataflow Programs on Hardware/Software Architectures. HICSS (7) Michael Eisenring, Jürgen Teich, Lothar Thiele
1998	A	`conf`	Representation of process mode correlation for scheduling. ICCAD Dirk Ziegenbein, Kai Richter, Rolf Ernst, Jürgen Teich, Lothar Thiele
1998	J	`jnl`	System-Level Synthesis Using Evolutionary Algorithms. Des. Autom. Embed. Syst. Tobias Blickle, Jürgen Teich, Lothar Thiele
1997	—	`conf`	An evolutionary approach to system-level synthesis. CODES Jürgen Teich, Tobias Blickle, Lothar Thiele
1997	—	`book`	Digitale Hardware/Software-Systeme - Synthese und Optimierung. Jürgen Teich
1997	J	`jnl`	Partitioning Processor Arrays under Resource Constraints. J. VLSI Signal Process. Jürgen Teich, Lothar Thiele, Lee Z. Zhang
1997	J	`jnl`	Performance analysis and optimization of mixed asynchronous synchronous systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jürgen Teich, Lothar Thiele, Sundararajan Sriram, Michael Martin
1996	—	`conf`	Scheduling of Partitioned Regular Algorithms on Processor Arrays with Constrained Resources. ASAP Jürgen Teich, Lothar Thiele, Li Zhang
1995	—	`conf`	Minimal Enclosing Parallelogram with Application. SCG Christian Schwarz, Jürgen Teich, Alek Vainshtein, Emo Welzl, Brian L. Evans
1995	—	`conf`	Modeling and simulation of heterogeneous real-time systems based on a deterministic discrete event model. ISSS Jürgen Teich, Lothar Thiele, Edward A. Lee
1993	—	`—`	A compiler for application specific processor arrays. Jürgen Teich
1993	J	`jnl`	Partitioning of processor arrays: a piecewise regular approach. Integr. Jürgen Teich, Lothar Thiele
1992	—	`conf`	A transformative approach to the partitioning of processor arrays. ASAP Jürgen Teich, Lothar Thiele
1991	J	`jnl`	Control generation in the design of processor arrays. J. VLSI Signal Process. Jürgen Teich, Lothar Thiele